LTC690/LTC691

LTC694/LTC695
Microprocessor
Supervisory Circuits

Features Description
n Guaranteed Reset Assertion at VCC = 1V The LTC®690 family, LTC690/LTC691/LTC694/LTC695,
n 1.5mA Maximum Supply Current provides complete power supply monitoring and battery
n Fast (35ns Max) Onboard Gating of RAM Chip control functions for microprocessor reset, battery back-
Enable Signals up, CMOS RAM write protection, power failure warning
n SO-8 and S16 Packaging and watchdog timing. A precise internal voltage reference
n 4.65V Precision Voltage Monitor and comparator circuit monitor the power supply line.
n Power OK/Reset Time Delay: 50ms, 200ms When an out-of-tolerance condition occurs, the reset
or Adjustable outputs are forced to active states and the chip enable
n Minimum External Component Count output unconditionally write-protects external memory.
n 1µA Maximum Standby Current In addition, the RESET output is guaranteed to remain
n Voltage Monitor for Power-Fail logic low even with VCC as low as 1V.
or Low Battery Warning
The LTC690 family powers the active CMOS RAMs with a
n Thermal Limiting
charge pumped NMOS power switch to achieve low drop­
n Performance Specified Over Temperature
out and low supply current. When primary power is lost,
n Superior Upgrade for MAX690 Family
auxiliary power, connected to the battery input pin, powers
Applications the RAMs in standby through an efficient PMOS switch.
n Critical µP Power Monitoring For an early warning of impending power failure, the LTC690
n Intelligent Instruments family provides an internal comparator with a user-defined
n Battery-Powered Computers and Controllers threshold. An internal watchdog timer is also available, which
n Automotive Systems forces the reset pins to active states when the watchdog
input is not toggled prior to a preset timeout period.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.

Typical Application RESET Output Voltage

vs Supply Voltage
5
LT®1086-5 TA = 25°C
VIN ≥ 7.5V 5V EXTERNAL PULL-UP = 10µA
VIN VOUT VCC VOUT POWER TO µP VBATT = 0V
+ + 4
RESET OUTPUT VOLTAGE (V)

10µF ADJ 100µF

0.1µF LTC690/LTC691 0.1µF CMOS RAM POWER
LTC694/LTC695 µP
VBATT 3
SYSTEM
3V
RESET µP RESET
51k
PFO µP NMI 2
PFI I/O LINE
GND WDI
1
10k 690 TA01
0.1µF 100Ω

MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE 0

WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP 0 1 2 3 4 5
FOR MICROPROCESSOR SYSTEMS SUPPLY VOLTAGE (V)
690 TA02

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LTC690/LTC691
LTC694/LTC695
Absolute Maximum Ratings
(Notes 1 and 2)
Terminal Voltage VOUT Output Current....................Short-Circuit Protected
VCC...................................................... – 0.3V to 6.0V Power Dissipation................................................500mW
VBATT................................................... –0.3V to 6.0V Operating Temperature Range
All Other Inputs.....................– 0.3V to (VOUT + 0.3V) LTC690/91/94/95C ................................. 0°C to 70°C
Input Current LTC690/91/94/95I ..............................– 40°C to 85°C
VCC.................................................................200mA Storage Temperature Range ................... –65°C to 150°C
VBATT................................................................50mA Lead Temperature (Soldering, 10 sec.).................. 300°C
GND..................................................................20mA

Pin Configuration
TOP VIEW TOP VIEW

VBATT 1 16 RESET VBATT 1 16 RESET

VOUT 2 15 RESET VOUT 2 15 RESET

VCC 3 14 WDO VCC 3 14 WDO

13 CE IN GND 4 13 CE IN
GND 4
BATT ON 5 12 CE OUT
BATT ON 5 12 CE OUT
LOWLINE 6 11 WDI
LOWLINE 6 11 WDI
OSC IN 7 10 PFO
OSC IN 7 10 PFO
OSC SEL 8 9 PFI
OSC SEL 8 9 PFI
SW PACKAGE
N PACKAGE 16-LEAD WIDE PLASTIC SO
16-LEAD PDIP TJMAX = 110°C, θJA = 130°C/W CONDITIONS: PCB MOUNT ON
TJMAX = 110°C, θJA = 130°C/W FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE

TOP VIEW TOP VIEW

VOUT 1 8 VBATT VOUT 1 8 VBATT

VCC 2 7 RESET VCC 2 7 RESET
GND 3 6 WDI GND 3 6 WDI
PFI 4 5 PFO PFI 4 5 PFO

J8 PACKAGE N8 PACKAGE S8 PACKAGE

8-LEAD CERDIP 8-LEAD PDIP 8-LEAD PLASTIC SO
TJMAX = 110°C, θJA = 130°C/W (N8) TJMAX = 110°C, θJA = 180°C/W CONDITIONS; PCB MOUNT ON
FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE

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 LTC690/LTC691
LTC694/LTC695
Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC691CN#PBF LTC691CN#PBF LTC691CN 16-Lead PDIP 0°C to 70°C
LTC691IN#PBF LTC691IN#PBF LTC691IN 16-Lead PDIP –40°C to 85°C
LTC695CN#PBF LTC695CN#PBF LTC695CN 16-Lead PDIP 0°C to 70°C
LTC695IN#PBF LTC695IN#PBF LTC695IN 16-Lead PDIP –40°C to 85°C
LTC691CSW#PBF LTC691CSW#PBF LTC691CSW 16-Lead Wide Plastic SO 0°C to 70°C
LTC691ISW#PBF LTC691ISW#PBF LTC691ISW 16-Lead Wide Plastic SO –40°C to 85°C
LTC695CSW#PBF LTC695CSW#PBF LTC695CSW 16-Lead Wide Plastic SO 0°C to 70°C
LTC695ISW#PBF LTC695ISW#PBF LTC695ISW 16-Lead Wide Plastic SO –40°C to 85°C
LTC690CN8#PBF LTC690CN8#PBF LTC690CN8 8-Lead PDIP 0°C to 70°C
LTC690IN8#PBF LTC690IN8#PBF LTC690IN8 8-Lead PDIP –40°C to 85°C
LTC694CN8#PBF LTC694CN8#PBF LTC694CN8 8-Lead PDIP 0°C to 70°C
LTC694IN8#PBF LTC694IN8#PBF LTC694IN8 8-Lead PDIP –40°C to 85°C
LTC690CS8#PBF LTC690CS8#PBF 690 8-Lead Plastic SO 0°C to 70°C
LTC690IS8#PBF LTC690IS8#PBF 690 8-Lead Plastic SO –40°C to 85°C
LTC694CS8#PBF LTC694CS8#PBF 694 8-Lead Plastic SO 0°C to 70°C
LTC694IS8#PBF LTC694IS8#PBF 694 8-Lead Plastic SO –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Product Selection Guide

CONDITIONAL
WATCHDOG BATTERY POWER-FAIL RAM WRITE PUSHBUTTON BATTERY
PINS RESET TIMER BACK-UP WARNING PROTECT RESET BACK-UP
LTC690 8 X X X X
LTC691 16 X X X X X
LTC694 8 X X X X
LTC695 16 X X X X X
LTC699 8 X X
LTC1232 8 X X X
LTC1235 16 X X X X X X X

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LTC690/LTC691
LTC694/LTC695
Electrical Characteristics The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Battery Back-Up Switching
Operating Voltage Range VCC 4.75 5.50 V
VBATT 2.00 4.25 V
VOUT Output Voltage IOUT = 1mA VCC – 0.05 VCC – 0.005 V
l VCC – 0.10 VCC – 0.005 V
IOUT = 50mA VCC – 0.50 VCC – 0.250 V
VOUT in Battery Back-Up Mode IOUT = 250µA, VCC < VBATT VBATT – 0.1 VBATT – 0.2 V
Supply Current (Exclude IOUT) IOUT = 50mA 0.6 1.5 mA
l 0.6 2.5 mA
Supply Current in Battery Back-Up Mode VCC = 0V, VBATT = 2.8V 0.04 1 µA
l 0.04 5 µA
Battery Standby Current (+ = Discharge, – = Charge) 5.5 > VCC > VBATT + 0.2V –0.1 +0.02 µA
l –0.1 +0.10 µA
Battery Switchover Threshold, VCC – VBATT Power Up 70 mV
Power Down 50 mV
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage (Note 4) ISINK = 3.2mA 0.4 V
BATT ON Output Short-Circuit Current (Note 4) BATT ON = VOUT Sink Current 35 m
BATT ON = 0V Source Current 0.5 1 25 µA
Reset and Watchdog Timer
Reset Voltage Threshold l 4.5 4.65 4.75 V
Reset Threshold Hysteresis 40 mV
Reset Active Time (LTC690/91) (Note 5) OSC SEL HIGH, VCC = 5V 40 50 60 ms
l 35 50 70 ms
Reset Active Time (LTC694/95) (Note 5) OSC SEL HIGH, VCC = 5V 160 200 240 ms
l 140 200 280 ms
Watchdog Timeout Period, Internal Oscillator Long Period, VCC = 5V 1.2 1.6 2.00 sec
l 1 1.6 2.25 sec
Short Period, VCC = 5V 80 100 120 ms
l 70 100 140 ms
Watchdog Timeout Period, External Clock (Note 6) Long Period 4032 4097 Clock
Short Period 960 1025 Cycles
Reset Active Time PSRR 1 ms/V
Watchdog Timeout Period PSRR, Internal OSC 1 ms/V
Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3.5V l 200 ns
RESET Output Voltage at VCC = 1V ISINK = 10µA, VCC = 1V 4 200 mV
RESET and LOWLINE Output Voltage (Note 4) ISINK = 1.6mA, VCC = 4.25V 0.4 V
ISOURCE = 1µA, VCC = 5V 3.5 V
RESET and WDO Output Voltage (Note 4) ISINK = 1.6mA, VCC = 5V 0.4 V
ISOURCE = 1µA, VCC = 4.25V 3.5 V

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 LTC690/LTC691
LTC694/LTC695
Electrical Characteristics The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESET, RESET, WDO, LOWLINE Output Source Current 1 3 25 µA
Output Short-Circuit Current (Note 4) Output Sink Current 25 mA
WDI Input Threshold Logic Low 0.8 V
Logic high 3.5
WDI Input Current WDI = VOUT l 4 50 µA
WDI = 0V l –50 –8
Power-Fail Detector
PFI Input Threshold VCC = 5V l 1.25 1.3 1.35 V
PFI Input Threshold PSRR 0.3 mV/V
PFI Input Current ±0.01 ±25 nA
PFO Output Voltage (Note 4) ISINK = 3.2mA 0.4 V
ISOURCE = 1µA 3.5
PFO Short-Circuit Source Current (Note 4) PFI = HIGH, PFO = 0V 1 3 25 µA
PFI = LOW, PFO = VOUT 25 mA
PFI Comparator Response Time (Falling) ∆VIN = –20mV, VOD = 15mV 2 µs
PFI Comparator Response Time (Rising) (Note 4) ∆VIN = 20mV, VOD = 15mV 40 µs
with 10kΩ Pull-Up 8
Chip Enable Gating
CE IN Threshold VIL 0.8 V
VIH 2
CE IN Pull-Up Current (Note 7) 3 µA
CE OUT Output Voltage ISINK = 3.2mA 0.4 V
ISOURCE = 3.0mA VOUT – 1.50
ISOURCE = 1µA, VCC = 0V VOUT – 0.05
CE Propagation Delay VCC = 5V, CL = 20pF 20 35 ns
l 20 45
CE OUT Output Short-Circuit Current Output Source Current 30 mA
Output Sink Current 35
Oscillator
OSC IN Input Current (Note 7) ±2 µA
OSC SEL Input Pull-Up Current (Note 7) 5 µA
OSC IN Frequency Range OSC SEL = 0V l 0 250 kHz
OSC IN Frequency with External Capacitor OSC SEL = 0V, COSC = 47pF 4 kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms
may cause permanent damage to the device. Exposure to any Absolute (50ms typically) while the LTC694 and LTC695 have longer minimum
Maximum Rating condition for extended periods may affect device reset active time of 140ms (200ms typically). The reset active time of
reliability and lifetime. the LTC691 and LTC695 can be adjusted (see Table 2 in Applications
Note 2: All voltage values are with respect to GND. Information section).
Note 3: For military temperature range parts or for the LTC692 and Note 6: The external clock feeding into the circuit passes through the
LTC693, consult the factory. oscillator before clocking the watchdog timer (See Block Diagram).
Note 4: The output pins of BATT ON, LOWLINE, PFO, WDO, RESET and Variation in the timeout period is caused by phase errors which occur
RESET have weak internal pull-ups of typically 3µA. However, external when the oscillator divides the external clock by 64. The resulting variation
pull-up resistors may be used when higher speed is required. in the timeout period is 64 clocks plus one clock of jitter.
Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.

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LTC690/LTC691
LTC694/LTC695
Block Diagram
M2
VBATT VOUT
M1
VCC

CHARGE
PUMP
–
C2 BATT ON
+

LOWLINE
+
C1
–
CE OUT
1.3V

GND
CE IN

–
C3 PFO
PFI +

RESET
OSC IN
OSC RESET PULSE
OSC SEL GENERATOR
RESET

WATCHDOG WDO
TRANSITION TIMER
WDI
DETECTOR 690 BD

Pin Functions
VCC: 5V Supply Input. The VCC pin should be bypassed GND: Ground pin.
with a 0.1µF capacitor. BATT ON: Battery On Logic Output from Comparator C2.
VOUT: Voltage Output for Backed Up Memory. Bypass with BATT ON goes low when VOUT is internally connected to
a capacitor of 0.1µF or greater. During normal operation, VCC. The output typically sinks 35mA and can provide
VOUT obtains power from VCC through an NMOS power base drive for an external PNP transistor to increase the
switch, M1, which can deliver up to 50mA and has a typical output current above the 50mA rating of VOUT. BATT ON
on resistance of 5Ω. When VCC is lower than VBATT, VOUT goes high when VOUT is internally switched to VBATT.
is internally switched to VBATT. If VOUT and VBATT are not PFI: Power Failure Input. PFI is the noninverting input
used, connect VOUT to VCC.
to the power-fail comparator, C3. The inverting input is
VBATT: Back-Up Battery Input. When VCC falls below VBATT, internally connected to a 1.3V reference. The power failure
auxiliary power, connected to VBATT, is delivered to VOUT output remains high when PFI is above 1.3V and goes
through PMOS switch, M2. If back-up battery or auxiliary low when PFI is below 1.3V. Connect PFI to GND or VOUT
power is not used, VBATT should be connected to GND. when C3 is not used.

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 LTC690/LTC691
LTC694/LTC695
Pin Functions
PFO: Power Failure Output from C3. PFO remains high WDO: Watchdog Logic Output. When the watchdog input
when PFI is above 1.3V and goes low when PFI is below remains either high or low for longer than the watchdog
1.3V. When VCC is lower than VBATT, C3 is shut down and timeout period, WDO goes low. WDO is set high whenever
PFO is forced low. there is a transition on the WDI pin, or LOWLINE goes
RESET: Logic Output for µP Reset Control. Whenever low. The watchdog timer can be disabled by floating WDI
VCC falls below either the reset voltage threshold (4.65V, (see Figure 11).
typically) or VBATT, RESET goes active low. After VCC returns CE IN: Logic input to the ChipEnable gating circuit. CE IN
to 5V, reset pulse generator forces RESET to remain active can be derived from microprocessor’s address line and/
low for a minimum of 35ms for the LTC690 /LTC691 (140ms or decoder output. See Applications Information section
for the LTC694/LTC695). When the watchdog timer is and Figure 5 for additional information.
enabled but not serviced prior to a preset timeout period,
CE OUT: Logic Output on the ChipEnable Gating Circuit.
reset pulse generator also forces RESET to active low for
When VCC is above the reset voltage threshold, CE OUT is
a minimum of 35ms for the LTC690/LTC691 (140ms for a buffered replica of CE IN. When VCC is below the reset
the LTC694/5) for every preset timeout period (see Figure voltage threshold CE OUT is forced high (see Figure 5).
11). The reset active time is adjustable on the LTC691/
LTC695. An external pushbutton reset can be used in OSC SEL: Oscillator Selection Input. When OSC SEL is
connection with the RESET output. See Pushbutton Reset high or floating, the internal oscillator sets the reset active
in Applications Information section. time and watchdog timeout period. Forcing OSC SEL low,
allows OSC IN be driven from an external clock signal or
RESET: RESET is an active high logic output. It is the external capacitor be connected between OSC IN and GND.
inverse of RESET.
OSC IN: Oscillator Input. OSC IN can be driven by an external
LOW�LINE: Logic Output from Comparator C1. LOWLINE clock signal or external capacitor can be connected between
indicates a low line condition at the VCC input. When VCC OSC IN and GND when OSC SEL is forced low. In this
falls below the reset voltage threshold (4.65V typically),
configuration the nominal reset active time and watchdog
LOWLINE goes low. As soon as VCC rises above the reset
timeout period are determined by the number of clocks or
voltage threshold, LOWLINE returns high (see Figure 1).
set by the formula (see Applications Information section).
LOWLINE goes low when VCC drops below VBATT (see
When OSC SEL is high or floating, the internal oscillator is
Table 1).
enabled and the reset active time is fixed at 50ms typical
WDI: Watchdog Input, WDI, is a three level input. Driving for the LTC691 and 200ms typical for the LTC695. OSC
WDI either high or low for longer than the watchdog timeout IN selects between the 1.6 seconds and 100ms typical
period, forces both RESET and WDO low. Floating WDI watchdog timeout periods. In both cases, the timeout
disables the watchdog timer. The timer resets itself with period immediately after a reset is 1.6 seconds typical.
each transition of the watchdog input (see Figure 11).

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LTC690/LTC691
LTC694/LTC695
Typical Performance Characteristics
Power Failure Input Threshold
VOUT vs IOUT VOUT vs IOUT vs Temperature
5.00 2.80 1.308
VCC = 5V VCC = 0V VCC = 5V
VBATT = 2.8V VBATT = 2.8V 1.306
TA = 25°C TA = 25°C
4.95

PFI INPUT THRESHOLD (V)

2.78
1.304

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

4.90 SLOPE = 125Ω

1.302
SLOPE = 5Ω 2.76
1.300
4.85

1.298
2.74
4.80
1.296

4.75 2.72 1.294

0 10 20 30 40 50 0 100 200 300 400 500 –50 –25 0 25 50 75 100 125
LOAD CURRENT (mA) LOAD CURRENT (µA) TEMPERATURE (°C)
690 G01 690 G02 690 G03

Reset Active Time Reset Active Time Reset Voltage Threshold

vs Temperature LTC690-1 vs Temperature LTC694-5 vs Temperature
58 232 4.66
VCC = 5V VCC = 5V

RESET VOLTAGE THRESHOLD (V)

56 224 4.65
RESET ACTIVE TIME
RESET ACTIVE TIME

54 216 4.64

52 208 4.63

50 200 4.62

48 192 4.61

46 184 4.60
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
690 G04 690 G05 690 G06

Power-Fail Comparator Power-Fail Comparator Power-Fail Comparator Response

Response Time Response Time Time with Pull-Up Resistor
6 6 6
PFO OUTPUT VOLTAGE (V)

PFO OUTPUT VOLTAGE (V)

VCC = 5V
PFO OUTPUT VOLTAGE (V)

VCC = 5V VCC = 5V
5 TA = 25°C 5 TA = 25°C 5 TA = 25˚C
4 4 4
3 VPFI + 3 3
PFO
2 1.3V – 30pF 2 VPFI + 2
PFO 5V
1 1 1.3V – 30pF 1
VPFI + 10k
0 0 0 PFO
1.3V – 30pF

1.305V 1.315V 1.315V

VPFI = 20mV STEP VPFI = 20mV STEP VPFI = 20mV STEP
1.285V 1.295V 1.295V

0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 180 0 2 4 6 8 10 12 14 16 18

TIME (µs) TIME (µs) TIME (µs)
690 G07 690 G08 690 G09

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 LTC690/LTC691
LTC694/LTC695
Applications Information
Microprocessor Reset of the precision voltage comparator C1. When VCC falls
below the reset voltage threshold, LOWLINE goes low.
The LTC690 family uses a bandgap voltage reference
LOWLINE returns high as soon as VCC rises above the
and a precision voltage comparator C1 to monitor the
reset voltage threshold.
5V supply input on VCC (see Block Diagram). When VCC
falls below the reset voltage threshold, the RESET output
Battery Switchover
is forced to active low state. The reset voltage threshold
accounts for a 5% variation on VCC, so the RESET output The battery switchover circuit compares VCC to the VBATT
becomes active low when VCC falls below 4.75V (4.65V input, and connects VOUT to whichever is higher. When
typical). On power-up, the RESET signal is held active low VCC rises to 70mV above VBATT, the battery switchover
for a minimum of 35ms for the LTC690/LTC691 (140ms comparator, C2, connects VOUT to VCC through a charge
for the LTC694/LTC695) after reset voltage threshold is pumped NMOS power switch, M1. When VCC falls to
reached to allow the power supply and microprocessor to 50mV above VBATT, C2 connects VOUT to VBATT through a
stabilize. The reset active time is adjustable on the LTC691/ PMOS switch, M2. C2 has typically 20mV of hysteresis to
LTC695. On power-down, the RESET signal remains active prevent spurious switching when VCC remains nearly equal
low even with VCC as low as 1V. This capability helps hold to VBATT. The response time of C2 is approximately 20µs.
the microprocessor in stable shutdown condition. Figure During normal operation, the LTC690 family uses a charge
1 shows the timing diagram of the RESET signal. pumped NMOS power switch to achieve low dropout and
The precision voltage comparator, C1, typically has 40mV low supply current. This power switch can deliver up to
of hysteresis which ensures that glitches at VCC pin do 50mA to VOUT from VCC and has a typical on resistance
not activate the RESET output. Response time is typically of 5Ω. The VOUT pin should be bypassed with a capaci-
10µs. To help prevent mistriggering due to transient loads, tor of 0.1µF or greater to ensure stability. Use of a larger
VCC pin should be bypassed with a 0.1µF capacitor with bypass capacitor is advantageous for supplying current
the leads trimmed as short as possible. to heavy transient loads.
The LTC691 and LTC695 have two additional outputs: When operating currents larger than 50mA are required
RESET and LOWLINE. RESET is an active high output from VOUT, or a lower dropout (VCC-VOUT voltage differential)
and is the inverse of RESET. LOWLINE is the output is desired, the LTC691 and LTC695 should be used.

V2 V2
VCC V1 V1 = RESET VOLTAGE THRESHOLD V1
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

RESET t1 t1

t1 = RESET ACTIVE TIME

LOW LINE

690 F01

Figure 1. Reset Active Time

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LTC690/LTC691
LTC694/LTC695
Applications Information
These products provide BATT ON output to drive the base farad-size double layer capacitors, can be used for short
of external PNP transistor (Figure 2). If higher currents term memory back-up instead of a battery. The charging
are needed with the LTC690 and LTC694, a high current resistor for both capacitors and rechargeable batteries
Schottky diode can be connected from the VCC pin to the should be connected to VOUT since this eliminates the
VOUT pin to supply the extra current. discharge path that exists when the resistor is connected
to VCC (Figure 3).
ANY PNP POWER TRANSISTOR
VOUT – VBATT
I=
R
5

3 BATT ON 2 R
5V VCC VOUT
5V VCC VOUT
0.1µF LTC691 0.1µF
LTC695 0.1µF LTC690 0.1µF
1
VBATT LTC691
GND LTC694
3V
4 LTC695
VBATT
690 F02

3V GND

Figure 2. Using BATT ON to Drive External PNP Transistor

690 F03

The LTC690 family is protected for safe area operation Figure 3. Charging External Battery Through VOUT
with short-circuit limit. Output current is limited to ap-
proximately 200mA. If the device is overloaded for long Replacing the Back-Up Battery
period of time, thermal shutdown turns the power switch
off until the device cools down. The threshold temperature When changing the back-up battery with system power
for thermal shutdown is approximately 155°C with about on, spurious resets can occur while battery is removed
10°C of hysteresis which prevents the device from oscil- due to battery standby current. Although battery standby
lating in and out of shutdown. current is only a tiny leakage current, it can still charge
up the stray capacitance on the VBATT pin. The oscillation
The PNP switch used in competitive devices was not chosen cycle is as follows: When VBATT reaches within 50mV of
for the internal power switch because it injects unwanted VCC, the LTC690 switches to battery back-up. VOUT pulls
current into the substrate. This current is collected by the VBATT low and the device goes back to normal operation.
VBATT pin in competitive devices and adds to the charging The leakage current then charges up the VBATT pin again
current of the battery which can damage lithium batteries. and the cycle repeats.
The LTC690 family uses a charge pumped NMOS power
switch to eliminate unwanted charging current while If spurious resets during battery replacement pose no
achieving low dropout and low supply current. Since no problems, then no action is required. Otherwise, a resistor
current goes to the substrate, the current collected by from VBATT to GND will hold the pin low while changing
VBATT pin is strictly junction leakage. the battery. For example, the battery standby current is
1µA maximum over temperature and the external resistor
A 125Ω PMOS switch connects the VBATT input to VOUT required to hold VBATT below VCC is:
in battery back-up mode. The switch is designed for very
low dropout voltage (input-to-output differential). This VCC − 50mV
R≤
feature is advantageous for low current applications such 1µA
as battery back-up in CMOS RAM and other low power
With VCC = 4.5V, a 4.3M resistor will work. With a 3V bat-
CMOS circuitry. The supply current in battery back-up
tery, this resistor will draw only 0.7µA from the battery,
mode is 1µA maximum.
which is negligible in most cases.
The operating voltage at the VBATT pin ranges from 2.0V
to 4.25V. High value capacitors, such as electrolytic or
690ff

10 For more information www.linear.com/690

 LTC690/LTC691
LTC694/LTC695
Applications Information
If battery connections are made through long wires, a input of battery-backed up CMOS RAM. CE OUT can also
10Ω to 100Ω series resistor and a 0.1µF capacitor are be used to drive the Store or Write input of an EEPROM,
recommended to prevent any overshoot beyond VCC due EAROM or NOVRAM to achieve similar protection. Figure
to the lead inductance (Figure 4). 5 shows the timing diagram of CE IN and CE OUT.

10Ω
CE IN can be derived from the microprocessor’s address
VBATT decoder output. Figure 6 shows a typical nonvolatile CMOS
4.3M 0.1µF LTC690 RAM application.
LTC691
LTC694
LTC695 Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
GND

690 F04
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL STATUS
Figure 4. 10Ω/0.1µF Combination Eliminates Inductive VCC C2 monitors VCC for active switchover.
Overshoot and Prevents Spurious Resets During Battery
VOUT VOUT is connected to VBATT through an internal PMOS switch.
Replacement
VBATT The supply current is 1µA maximum.
Table 1 shows the state of each pin during battery back-up. BATT ON Logic high. The open-circuit output voltage is equal to VOUT .
When the battery switchover section is not used, connect PFI Power failure input is ignored.
VBATT to GND and VOUT to VCC . PFO Logic low
RESET Logic low
Memory Protection RESET Logic high. The open-circuit output voltage is equal to VOUT.
The LTC691 and LTC695 include memory protection cir- LOWLINE Logic low
cuitry that ensures the integrity of the data in memory by WDI Watchdog input is ignored.
preventing write operations when VCC is at invalid level. WDO Logic high. The open-circuit output voltage is equal to VOUT.
Two additional pins, CE IN and CE OUT, control the Chip CE IN ChipEnable Input is ignored.
Enable or Write inputs of CMOS RAM. When VCC is 5V, CE OUT Logic high. The open-circuit output voltage is equal to VOUT.
CE OUT follows CE IN with a typical propagation delay of OSC IN OSC IN is ignored.
20ns. When VCC falls below the reset voltage threshold or OSC SEL OSC SEL is ignored.
VBATT, CE OUT is forced high, independent of CE IN. CE
OUT is an alternative signal to drive the CE, CS, or Write

V2
VCC V1 V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

CE IN

CE OUT VOUT = VBATT

VOUT = VBATT
690 F05

Figure 5. Timing Diagram for CE IN and CE OUT

690ff

For more information www.linear.com/690 11

LTC690/LTC691
LTC694/LTC695
Applications Information
5V VCC VOUT VCC Power-Fail Warning
+ 0.1µF
0.1µF LTC691 10µF 62512
LTC695 RAM The LTC690 family generates a Power Failure Output (PFO)
CE OUT CS for early warning of failure in the microprocessor’s power
20ns PROPAGATION DELAY GND
VBATT
CE IN FROM DECODER
supply. This is accomplished by comparing the Power
3V RESET Failure Input (PFI) with an internal 1.3V reference. PFO
GND RESET goes low when the voltage at the PFI pin is less than 1.3V.
TO µP
690 F06 Typically PFI is driven by an external voltage divider (R1 and
R2 in Figures 8 and 9) which senses either an unregulated
Figure 6. A Typical Nonvolatile CMOS RAM Application
DC input or a regulated 5V output. The voltage divider ratio
can be chosen such that the voltage at the PFI pin falls
below 1.3V several milliseconds before the 5V supply falls
5V VCC VOUT
+
VCC
below the maximum reset voltage threshold 4.75V. PFO is
0.1µF 62128
0.1µF LTC690
LTC694
10µF
RAM normally used to interrupt the microprocessor to execute
CS CS1 shutdown procedure between PFO and RESET or RESET.
VBATT RESET CS2
3V GND GND The power-fail comparator, C3, does not have hysteresis.
690 F07
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
Figure 7. Write Protect for RAM with LTC690 or LTC694 pin as shown in Figures 8 and 9. The upper and lower
trip points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the sum-
VIN ≥ 7.5V LT1086-5
VIN VOUT 5V ming junction at the PFI pin.
VCC
+ +
10µF ADJ 100µF
0.1µF
LTC690/LTC691  R1 R1
VH = 1.3V  1+ +
 R2 R3 
R4 LTC694/LTC695
R3 10k
R1 300k
51k PFO
PFI GND When PFO output is high, the series combination of R3
R2
10k
TO µP
690 F08 and R4 source current into the PFI summing junction.
 R1 (5V − 1.3V) R1
Figure 8. Monitoring Unregulated DC Supply VL = 1.3V  1+ −
with the LTC690’s Power-Fail Comparator  R2 1.3V (R3 + R4) 
R1
Assuming R4 << R3,VHYSTERESIS = 5V
VIN ≥ 6.5V LT1086-5 R3
5V
VIN VOUT VCC
+ + R4 0.1µF Example 1: The circuit in Figure 8 demonstrates the use
10µF ADJ 10µF R1
10k LTC690/LTC691
27k
R3
LTC694/LTC695 of the power-fail comparator to monitor the unregulated
2.7M
PFO
power supply input. Assuming the the rate of decay of
PFI GND the supply input VIN is 100mV/ms and the total time to
R2
8.2k 1690 F09
execute a shutdown procedure is 8ms. Also the noise of
TO µP
R5 VIN is 200mV. With these assumptions in mind, we can
3.3k
reasonably set VL = 7.5V which 1.25V greater than the sum
of maximum reset voltage threshold and the dropout volt-
Figure 9. Monitoring Regulated DC Supply age of LT1086-5 (4.75V + 1.5V) and VHYSTERESIS = 850mV.
with the LTC690’s Power-Fail Comparator

690ff

12 For more information www.linear.com/690

 LTC690/LTC691
LTC694/LTC695
Applications Information
R1 5V
VHYSTERESIS = 5V = 850mV
R3 VCC
VBATT
R3 ≈ 5.88 R1 PFO
LOW-BATTERY SIGNAL
TO µP I/O PIN
R1
1M
LTC691
Choose R3 = 300k and R1 = 51k. Also select R4 = 10k PFI LTC695
which is much smaller than R3. 3V
R2
1M CE IN I/O PIN
 51k (5V − 1.3V) 51k  CE OUT GND
7.5V = 1.3V  1+ −
 R2 1.3V (310k)  RL 690 F10
20K

R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalcu­ OPTIONAL TEST LOAD
late VL,
Figure 10. Back-Up Battery Monitor with Optional Test Load
 51k (5V − 1.3V) 51k 
VL = 1.3V  1+ − = 7.32V
 10k 1.3V (310k) 
Watchdog Timer
 51k 51k  The LTC690 family provides a watchdog timer function
VH = 1.3V  1+ − = 8.151V to monitor the activity of the microprocessor. If the mi-
 10k 300k 
croprocessor does not toggle the Watchdog Input (WDI)
(7.32V − 6.25V) within a selected timeout period, RESET is forced to ac-
= 10.7ms tive low for a minimum of 35ms for the LTC690/LTC691
100mV / ms
(140ms for the LTC694/LTC695). The reset active time is
VHYSTERESIS = 8.151V − 7.32V = 831mV adjustable on the LTC691/LTC695. Since many systems
can not service the watchdog timer immediately after a
The 10.7ms allows enough time to execute shutdown reset, the LTC691 and LTC695 have longer timeout period
procedure for microprocessor and 831mV of hysteresis (1.0 second minimum) right after a reset is issued. The
would prevent PFO from going low due to the noise of VIN. normal timeout period (70ms minimum) becomes effective
Example 2: The circuit in Figure 9 can be used to measure following the first transition of WDI after RESET is inac-
the regulated 5V supply to provide early warning of power tive. The watchdog timeout period is fixed at 1.0 second
failure. Because of variations in the PFI threshold, this minimum on the LTC690 and LTC694. Figure 11 shows
circuit requires adjustment to ensure the PFI compara- the timing diagram of watchdog timeout period and reset
tor trips before the reset threshold is reached. Adjust R5 active time. The watchdog timeout period is restarted as
such that the PFO output goes low when the VCC supply soon as RESET is inactive. When either a high-to-low
reaches the desired level (e.g., 4.85V). or low-to-high transition occurs at the WDI pin prior to
timeout, the watchdog time is reset and begins to time
Monitoring the Status of the Battery out again. To ensure the watchdog time does not time
C3 can also monitor the status of the memory back-up out, either a high-to-low or low-to-high transition on the
battery (Figure 10). If desired, the CE OUT can be used to WDI pin must occur at or less than the minimum timeout
apply a test load to the battery. Since CE OUT is forced high period. If the input to the WDI pin remains either high or
in battery back-up mode, the test load will not be applied low, reset pulses will be issued every 1.6 seconds typically.
to the battery while it is in use, even if the microprocessor The watchdog time can be deactivated by floating the WDI
is not powered. pin. The timer is also disabled when VCC falls below the
reset voltage threshold or VBATT.

690ff

For more information www.linear.com/690 13

LTC690/LTC691
LTC694/LTC695
Applications Information
The LTC691 and LTC695 provide an additional output GND when OSC SEL is forced low. In these configura-
(Watchdog Output, WDO) which goes low if the watchdog tions, the nominal reset active time and watchdog timeout
timer is allowed to time out and remains low until set high period are determined by the number of clocks or set by
by the next transition on the WDI pin. WDO is also set high the formula in Table 2. When OSC SEL is high or floating,
when VCC falls below the reset voltage threshold or VBATT. the internal oscillator is enabled and the reset active time
The LTC691 and LTC695 have two additional pins OSC SEL is fixed at 35ms minimum for the LTC691 and 140ms
and OSC IN, which allow reset active time and watchdog minimum for the LTC695. OSC IN selects between the 1
timeout period to be adjusted per Table 2. Several con- second and 70ms minimum normal watchdog timeout
figurations are shown in Figure 12. periods. In both cases, the timeout period immediately
after a reset is at least 1 second.
OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and
VCC = 5V
WDI

t1 = RESET ACTIVE TIME

t2 = NORMAL WATCHDOG TIME-OUT PERIOD
WDO t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY
AFTER A RESET

t2 t3
RESET

t1 t1
690 F11

Figure 11. Watchdog Timeout Period and Reset Active Time

EXTERNAL CLOCK EXTERNAL OSCILLATOR

3 8 3 8
5V VCC OSC SEL 5V VCC OSC SEL

LTC691 LTC691
LTC695 LTC695

4 7 4 7
GND OSC IN GND OSC IN

INTERNAL OSCILLATOR INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG 100ms WATCHDOG

3 8 FLOATING 3 8 FLOATING
5V VCC OSC SEL 5V VCC OSC SEL
OR HIGH OR HIGH

LTC691 LTC691
LTC695 LTC695

4 7 FLOATING 4 7
GND OSC IN OR HIGH GND OSC IN

690 F12

Figure 12. Oscillator Configurations

690ff

14 For more information www.linear.com/690

 LTC690/LTC691
LTC694/LTC695
Applications Information
Table 2. LTC691 and LTC695 Reset Active Time and Watchdog Timeout Selections
WATCHDOG TIME-OUT PERIOD RESET ACTIVE TIME
IMMEDIATELY
NORMAL AFTER RESET
OSC SEL OSC IN (Short Period) (Long Period) LTC691 LTC695
Low External Clock Input 1024 clks 4096 clks 512 clks 2048 clks
400ms 1.6sec 200ms 800ms
Low External Capacitor* •C •C •C •C
70pF 70pF 70pF 70pF

Floating or High Low 100ms 1.6 sec 50ms 200ms

Floating or High Floating or High 1.6 sec 1.6 sec 50ms 200ms
184,000
*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is fOSC (Hz) =
C(pF) • 1025

Pushbutton Reset
The LTC690 family does not provide a logic input for direct 5V VCC RESET RESET
connection to a pushbutton. However, a pushbutton in 0.1µF 100Ω MPU
series with a 100Ω resistor connected to the RESET output LTC690/LTC691
LTC694/LTC695 (e.g. 6805)
pin (Figure 13) provides an alternative for manual reset.
Connecting a 0.1µF capacitor to the RESET pin debounces GND 690 F13

the pushbutton input.

The 100Ω resistor in series with the pushbutton is required Figure 13. The External Pushbutton Reset
to prevent the ringing, due to the capacitance and lead
inductance, from pulling the RESET pins of the MPU and
LTC69X below ground. 5V VCC RESET RESET

If a dedicated pushbutton reset input is desired, the LTC1235

MPU
(e.g. 6805)
LTC1235 is a good choice (Figure 14). It has all the func-
PBRST
tions of the LTC695 and provides pushbutton reset as an GND 690 F14

extra feature. Its pushbutton is internally debounced and

invokes the normal 200ms reset sequence. This eliminates
the need for the 100Ω resistor and 0.1µF capacitor. It also
Figure 14. The External Pushbutton Reset with the LTC1235
provides a more consistent reset pulse.

690ff

For more information www.linear.com/690 15

LTC690/LTC691
LTC694/LTC695
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)

.030 ±.005 .050 BSC .045 ±.005 .398 – .413

TYP (10.109 – 10.490)
NOTE 4
N 16 15 14 13 12 11 10 9

.420 .325 ±.005

MIN
NOTE 3 .394 – .419
(10.007 – 10.643)

1 2 3 N/2 N/2

RECOMMENDED SOLDER PAD LAYOUT

1 2 3 4 5 6 7 8

.291 – .299
(7.391 – 7.595)
NOTE 4 .037 – .045
.093 – .104
.010 – .029 × 45° (0.940 – 1.143)
(2.362 – 2.642)
(0.254 – 0.737)
.005
(0.127)
RAD MIN 0° – 8° TYP

.050
.009 – .013 (1.270) .004 – .012
(0.229 – 0.330) NOTE 3 BSC (0.102 – 0.305)
.014 – .019
.016 – .050
(0.356 – 0.482)
(0.406 – 1.270)
TYP
NOTE:
INCHES
1. DIMENSIONS IN S16 (WIDE) 0502
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

690ff

16 For more information www.linear.com/690

 LTC690/LTC691
LTC694/LTC695
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)

.400*
.300 – .325 .045 – .065 .130 ±.005
(10.160)
MAX (7.620 – 8.255) (1.143 – 1.651) (3.302 ±0.127)

8 7 6 5
.065
(1.651)
.255 ±.015* .008 – .015 TYP
(6.477 ±0.381) (0.203 – 0.381) .120
(3.048) .020
+.035 MIN (0.508)
.325 –.015
MIN

( )
1 2 3 4 .100 .018 ±.003
+0.889 (2.54)
8.255 (0.457 ±0.076) N8 REV I 0711
–0.381
BSC
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)

.189 – .197
.045 ±.005 (4.801 – 5.004)
.050 BSC NOTE 3
8 7 6 5

.245
MIN .160 ±.005
.150 – .157
.228 – .244
(3.810 – 3.988)
(5.791 – 6.197)
NOTE 3

.030 ±.005
TYP
1 2 3 4
RECOMMENDED SOLDER PAD LAYOUT

.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.004 – .010
.008 – .010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

.016 – .050
.014 – .019 .050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 REV G 0212

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

690ff

For more information www.linear.com/690 17

LTC690/LTC691
LTC694/LTC695
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)

.770*
(19.558)
MAX

16 15 14 13 12 11 10 9

.255 ±.015*
(6.477 ±0.381)

1 2 3 4 5 6 7 8

.300 – .325 .130 ±.005 .045 – .065

(7.620 – 8.255) (3.302 ±0.127) (1.143 – 1.651)

.020
(0.508)
MIN .065
.008 – .015
(1.651)
(0.203 – 0.381) TYP
+.035
.325 –.015
.120

( )
.100 .018 ±.003
+0.889 (3.048) (2.54) (0.457 ±0.076)
8.255
–0.381 MIN BSC N16 REV I 0711

NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

690ff

18 For more information www.linear.com/690

 LTC690/LTC691
LTC694/LTC695
Revision History (Revision history begins at Rev D)

REV DATE DESCRIPTION PAGE NUMBER

D 3/10 Removed “UL Recognized” and UL File Number From Features 1
E 4/10 Removed LTC690MJ8 3
F 3/13 Corrected top mark for LTC690CS8 and LTC690IS8 3

690ff

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
Forofmore
tion that the interconnection information
its circuits www.linear.com/690
as described herein will not infringe on existing patent rights. 19
LTC690/LTC691
LTC694/LTC695
Typical Application
Capacitor Back-Up with 74HC4016 Switch Write Protect for Additional RAMs

5V 5V VCC VOUT VCC

VCC VOUT +
0.1µF LTC691 10µF 0.1µF 62512
0.1µF 0.1µF RAM A
LTC691 LTC695
R1
10 11 12 14 LTC695 CE OUT CS
10k
20ns PROPAGATION
1 2 VBATT DELAY
74HC4016 VBATT LOWLINE
CE IN CSA
R2 3V
30k 7 13 LOWLINE
+
100µF GND GND
VCC
0.1µF 62128
LTC690 TA03
RAM B
CSB CS1

CS2

VCC
0.1µF 62128
RAM C
CSC CS1
CS2

OPTIONAL CONNECTION FOR

ADDITIONAL RAMs
690 TA04

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LTC2916 Voltage Supervisor with 9 Selectable Thresholds 9 Pin-Selectable Thresholds, 1.5V to 5.5V Supply, Manual Reset
LTC2917 Voltage Supervisor with 27 Selectable Thresholds 9 Pin-Selectable Thresholds, 3 Tolerances, 1.5V to 5.5V Supply,
and Watchdog Timer Adjustable Watchdog Timer
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Power-Fail Output Supply, Power-Fail Warning, Manual Reset
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Power-Fail Output Manual Reset

690ff

20 Linear Technology Corporation

LT 0313 REV F • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/690
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/690  LINEAR TECHNOLOGY CORPORATION 1992