Computer Architecture
Falah Hassan Ali
University of Toronto
• Base address
32-bit segment starting address
• Granularity (G)
Indicates whether the segment size is in
» 0 = bytes, or
» 1 = 4KB
• Segment Limit
20-bit value specifies the segment size
» G = 0: 1byte to 1 MB
» G = 1: 4KB to 4GB, in increments of 4KB
• D/B bit
Code segment
» D bit: default size operands and offset value
– D = 0: 16-bit values
– D = 1: 32-bit values
Data segment
» B bit: controls the size of the stack and stack pointer
– B = 0: SP is used with an upper bound of FFFFH
– B = 1: ESP is used with an upper bound of FFFFFFFFH
Cleared for real mode
Set for protected mode
• S bit
Identifies whether
» System segment, or
» Application segment
• Descriptor privilege level (DPL)
Defines segment privilege level
• Type
Identifies type of segment
» Data segment: read-only, read-write, …
» Code segment: execute-only, execute/read-only, …
• P bit
Indicates whether the segment is present.
• Three types of segment descriptor tables
Global descriptor table (GDT)
» Only one in the system
» Contains OS code and data
» Available to all tasks
Local descriptor table (LDT)
» Several LDTs
» Contains descriptors of a program
Interrupt descriptor table (IDT
» Used in interrupt processing
• Segmentation Models
Pentium can turn off segmentation
Flat model
» Consists of one segment of 4GB
» E.g. used by UNIX
Multi-segment model
» Up to six active segments
» Can have more than six segments
– Descriptors must be in the descriptor table
» A segment becomes active by loading its descriptor into one of the segment
registers.
M ixed-mode operation
Possible to combine 16-bit and 32-bit operands and addresses
D/B bit indicates the default size
» 0 = 16 bit mode
» 1 = 32-bit mode
Pentium provides two override prefixes
» One for operands
» One for addresses
• Pentium uses default segments depending on the purpose of the memory reference
Instruction fetch
» CS register
Stack operations
» 16-bit mode: SP
» 32-bit mode: ESP
Accessing data
» DS register
» Offset depends on the addressing mode
PAGING MECHANISM
Paging 4KB for earlier version before Pentium
Paging 4MB for 8086 Pentium Processor
Mapping directory and page number onto the memory address.
Assignments:
1- Consider a logical address space of eight pages of 1024 words each, mapped onto a physical address
space of 32 frames. How many bits are there in the logical address and how many bits are there in
the physical address?
2- If a memory reference takes 200 nanoseconds, how long does a paged memory reference take?
3- Why segmentation and paging sometimes combined into one scheme?
4- Consider the content of descriptor is 20009200000000BB and the offset is 11000045h, whilst the
content of PDBR is 0. What are the directory number and base address?
5- Assume the linear address is 10012000h and the content of the descriptor in the page table is
1002A0FF. What is the address of stored byte?
6- Assume the linear address is 10012000h and the content of PDE is 100000FF. Find the base address
of page table?
7- Show how many bytes or memory cells can page directory address up to?
8- Suppose the base address of page directory, table, and frame is 0. The base address of PDE, PTE,
and frame are 0X080, 0X03F, and 0X011 respectively. What is the linear address?
9- Assume the directory, page, and frame numbers are 92, 63, and 12 respectively. Show the linear
address that proposed by the processor.
