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EE5320: Analog IC Design Chaitanya Kumar EE19S062 Dept. of Electrical Engg. IIT Madras Chennai 600036

The document contains the details of an analog IC design assignment completed by a student. It includes: 1) Plots of device parameters like threshold voltage, transconductance, and output resistance versus operating point. 2) The schematic and design details of a common source amplifier with specified performance targets. 3) The schematic and AC/transient response of a source follower used for level shifting with required input and output specifications.

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Chaitanya Kumar
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151 views24 pages

EE5320: Analog IC Design Chaitanya Kumar EE19S062 Dept. of Electrical Engg. IIT Madras Chennai 600036

The document contains the details of an analog IC design assignment completed by a student. It includes: 1) Plots of device parameters like threshold voltage, transconductance, and output resistance versus operating point. 2) The schematic and design details of a common source amplifier with specified performance targets. 3) The schematic and AC/transient response of a source follower used for level shifting with required input and output specifications.

Uploaded by

Chaitanya Kumar
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EE5320: Analog IC Design

Chaitanya Kumar
EE19S062
Dept. of Electrical Engg.
IIT Madras
Chennai 600036

Assignment 3
1 a) VTH vs L

NMOS

PMOS
b) Vgs -Vth vs Vov
c) gm Vs Vov
d) gm/Id vs Vov
e) ft vs Vov
f) Setting Vov
-Vov vs Vgs curve remains constant (nearly) for a particular width
-Vov vs Vgs curve plotted for each length both for pmos and nmos and found the corresponding
Vgs to bais it.

Nmos

Pmos
Rds Vs Vov

Nmos 130 nm

Pmos 130nm

Nmos 250nm
Pmos 250nm

Nmos 360nm

Nmos 500nm
Pmos 500nm

g) Self Gain vs Vov

L = 130nm left graph is Pmos Right is Nmos

L = 500nm left graph is Pmos Right is Nmos


L = 360nm right graph is Pmos left is Nmos

L = 250nm Nmos
L = 250nm Pmos

2.

Schematic
Input: Nmos (W/L = 360um/600nm)
Active Load: Pmos (W/L = 148.64um/600nm)
Current in the common source branch = 564.48 uA

Design method:
-Selected gm of input = 12.56 mS from UGB requirement. Vdsat of Nmos to be 75mV. Vdsat of
Pmos to be 219 mV (couldn’t to further down as the transition frequency of the pmos was
limited).
-From the above parameters selected W/L and current required in nmos by plotting parameters
such as gm, Vdsat vs current density. Then iterated the length iterated by increasing the length
to get desired gds.
- W/L of pmos was selected from a fixed current of 565.48 uA and a Vdsat of 219 mV. Then
iterated by increasing length to get a gds of 125 uS keeping the W/L constant.
-Biasing the output DC to desired value. Used a negative feedback through opamp around the
Nmos. Setting output to desired value and then used capacitive coupling at the gate of nmos to
provide the input.

AC Responce
Gain vs Output DC voltage.

3. a)
Since level shift up was required so used pmos source follower.
For Input device: (current = 30.3mA)
- Gm = 125.6 mS computed from 3 dB bandwidth
- Vgs =0.8 V Required as per question
- W/L = 635um/130nm (initialy determined by plotting vgs, gm vs current density followed
by some tweaking to increase the gm to compensate for parasitics.
For Load device:
- Vdsat = 0.5 V
- Gds = 6.975mS
- W/L = 570um/130nm

AC Responce
Transient Responce (Settling time = 2.27 nS)

Calculated Capacitance = 323.31 fF (Ggd + Cgs(1-Av))

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