TGA2512

X Band Low Noise Amplifier

Key Features
• Typical Frequency Range: 5 - 15 GHz
• 1.4 dB Nominal Noise Figure
• 27 dB Nominal Gain
• Bias: 5 V, 160 mA Gate Bias
5 V, 90 mA Self Bias
• 0.15 um 3MI pHEMT Technology
• Chip Dimensions 2.05 x 1.20 x 0.10 mm
(0.081 x 0.047 x 0.004 in)

Product Description Primary Applications

The TriQuint TGA2512 is a wideband LNA with
• X-Band Radar
AGC amplifier for EW, ECM, and RADAR • EW, ECM
receiver or driver amplifier applications.
Offering high gain 27dB typical from 5-15GHz, • Point-to-Point Radio
the TGA2512 provides excellent noise
performance with typical midband NF 1.4dB,
while the balanced topology offers good return Measured Fixtured Data
loss typically 15dB. Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA

40
The TGA2512 is designed for maximum ease
30 GAIN
of use. The large input FETs can handle up to
S-Parameter (dB)

21dBm input power reliably, while the build-in 20

gain control provides 15dB of typical gain 10
control range. The part is also assembled in 0
self-biased mode, using a single +5V supply
connection from either side of the chip, or in -10 IRL
gate biased mode, allowing the user to control -20
the current for a particular applications. ORL
-30
-40
In self-biased mode the TGA2512 offers 6dBm
5 6 7 8 9 10 11 12 13 14 15
typical P1dB, while in gate-biased mode the
typical P1dB is over 13dBm. The small size of Frequency (GHz)
2.46mm2 allows ease of compaction into Multi- 5.0
Chip-Modules (MCMs). 4.5
4.0
Noise Figure (dB)

3.5
The TGA2512 is 100% DC and RF tested on-
3.0
wafer to ensure performance compliance.
2.5
2.0
Lead-Free & RoHS compliant.
1.5
1.0
0.5
0.0
5 6 7 8 9 10 11 12 13 14 15
Frequency (GHz)

Datasheet subject to change without notice

1
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May 2009 © Rev -
 TGA2512

TABLE I
MAXIMUM RATINGS 1/

SYMBOL PARAMETER VALUE NOTES

Vd Drain Voltage [3.5 + (0.0125)(Id)] V 2/ 3/
Vg Gate Voltage Range -1 TO +0.5 V
Id Drain Current (gate biased) 240 mA 2/ 4/
⏐Ig⏐ Gate Current 7.04 mA 4/
PIN Input Continuous Wave Power 21 dBm
PD Power Dissipation 1.56 W 2/ 5/
TCH Operating Channel Temperature 200 °C 6/ 7/
Mounting Temperature (30 Seconds) 320 °C
TSTG Storage Temperature -65 to 150 °C

1/ These ratings represent the maximum operable values for this device.

2/ Combinations of supply voltage, supply current, input power, and output power shall not exceed PD.

3/ Unit for Id is mA

4/ Total current for the entire MMIC.

5/ When operated at this bias condition with a base plate temperature of 70°C, the median life is
3.4E5.

6/ Junction operating temperature will directly affect the device median time to failure (Tm). For maximum
life, it is recommended that junction temperatures be maintained at the lowest possible levels.

7/ These ratings apply to each individual FET.

TABLE II
DC PROBE TESTS
(Ta = 25 °C, Nominal)

SYMBOL PARAMETER MIN. TYP. MAX. UNITS

VBVGS, Q1 Breakdown Voltage Gate-Source -30 -5 V

VP, Q1,2,4,5,6 Pinch-Off Voltage -0.7 -0.1 V

Q1, Q4, Q5 are 400 um FETs. Q2, Q6 are 300 um FETs.

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May 2009 © Rev -
 TGA2512

TABLE III
ELECTRICAL CHARACTERISTICS
(Ta = 25 0C Nominal)

PARAMETER Gate Bias Self Bias UNITS

Frequency Range 5 - 15 5 - 15 GHz
Drain Voltage, Vd 5.0 5.0 V
Drain Current, Id 160 90 mA
Gate Voltage, Vg -0.1 - V
Small Signal Gain, S21 27 24 dB
Input Return Loss, S11 15 15 dB
Output Return Loss, S22 20 20 dB
Noise Figure, NF 1.4 1.4 dB
Output Power @ 1dB Gain Compression, P1dB 13 6 dBm
OIP3 24 16 dBm

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May 2009 © Rev -
 TGA2512

TABLE IV
THERMAL INFORMATION

PARAMETER TEST CONDITIONS TCH θJC Tm

(°C) (°C/W) (HRS)

Vd = 5 V
θJC Thermal Resistance 100 37.6 5.8E+6
Id = 160 mA Gate Bias
(channel to Case)
Pdiss = 0.80 W

Vd = 5 V
θJC Thermal Resistance 82.7 28.2 4.1E+7
Id = 90 mA Self Bias
(channel to Case)
Pdiss = 0.45 W

Note: Assumes eutectic attach using 1.5 mil 80/20 AuSn mounted to a 20 mil CuMo
Carrier at 70°C baseplate temperature. Worst case condition with no RF applied, 100% of
DC power is dissipated.

Median Lifetime (Tm) vs. Channel Temperature

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May 2009 © Rev -
 TGA2512
Measured Fixtured Data

Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA

34
32
30
28
26
G ain (dB)

24
22
20
18
16
14
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)
5.0

4.5

4.0

3.5
Noise Figure (dB)

3.0

2.5

2.0

1.5

1.0

0.5

0.0
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)

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May 2009 © Rev -
 TGA2512
Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA

0
-5
-10
Input Return Loss (dB)

-15
-20
-25
-30
-35
-40
-45
-50
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)

0
-5
-10
O utput Return Loss (dB)

-15
-20
-25
-30
-35
-40
-45
-50
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)

6
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May 2009 © Rev -
 TGA2512
Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA

16

14

12

10
P1dB (dBm)

0
6 7 8 9 10 11 12 13 14 15 16
Frequency (GHz)
28

26

24

22

20
OIP3 (dBm)

18

16

14

12

10

8
6 7 8 9 10 11 12 13
Frequency (GHz)

7
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May 2009 © Rev -
 TGA2512
Measured Fixtured Data
Bias Conditions: Gate Bias Vd = 5 V, Id = 160 mA Over Temperature

35

30
Gain Over Temperature (dB)

25

20

15

10

-40C
5 +25C
+70C

0
2 4 6 8 10 12 14 16 18 20
Frequency (GHz)

8
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May 2009 © Rev -
 TGA2512
Measured Fixtured Data
Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA

34

32

30

28

26
Gain (dB)

24

22

20

18

16

14
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)
5.0

4.5

4.0

3.5
Noise Figure (dB)

3.0

2.5

2.0

1.5

1.0

0.5

0.0
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)

9
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May 2009 © Rev -
 TGA2512
Measured Fixtured Data

Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA

0

-5

-10
Input Return Loss (dB)

-15

-20

-25

-30

-35

-40

-45

-50
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)

-5

-10
Output Return Loss (dB)

-15

-20

-25

-30

-35

-40

-45

-50
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (GHz)

10
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May 2009 © Rev -
 TGA2512
Measured Fixtured Data
Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA

16

14

12

10
P1dB (dBm)

0
6 7 8 9 10 11 12 13 14 15 16
Frequency (GHz)

28

26

24

22
OIP3 (dBm)

20

18

16

14

12

10

8
6 7 8 9 10 11 12 13
Frequency (GHz)

11
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May 2009 © Rev -
 TGA2512
Measured Fixtured Data

Bias Conditions: Self Bias Vd = 5 V, Id = 90 mA Over Temperature

30

25
Gain Over Temperature (dB)

20

15

10

5 -40C
+25C
+70C
0
2 4 6 8 10 12 14 16 18 20
Frequency (GHz)

12
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May 2009 © Rev -
 TGA2512
Measured Fixtured Data

Self Biased variation over Vctrl

30
Vctrl=0 v
Vctrl=3V
25 Vctrl=3.2V
Vctrl=3.5V
Vctrl=4 V
Vctrl=5 V
20
Vctrl=6V
Gain (dB)

15

10

0
2 4 6 8 10 12 14 16 18
Frequency (GHz)
5.0

4.5

4.0

3.5
Noise Figure (dB)

3.0

2.5
Vctrl=0V
2.0 Vctrl=2V
Vctrl=2.25V
1.5 Vctrl=2.5V
Vctrl=2.75V
1.0 Vctrl=3V
Vctrl=3.5V
0.5 Vctrl=4V
Vctrl=5V
0.0
2 4 6 8 10 12 14 16 18
Frequency (GHz)

13
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 TGA2512

Mechanical Drawing

0.095 0.642 0.914 1.086 1.327 1.755

(0.004) (0.025) (0.036) (0.043) (0.052) (0.069)

1.200
(0.047)
1.105
2 3 4 5 6 (0.044)

RC B RC B

NE

0.145
(0.006)
1 7 0.145
(0.006)
0.095 13 12 11 10 9 8
(0.004)
0

0 0.642 0.914 1.086 1.327 1.675 1.815 1.955 2.050

(0.025) (0.036) (0.043) (0.052) (0.060) (0.072) (0.077) (0.081)

Units: millimeters (inches)

Thickness: 0.100 (0.004)
Chip edge to bond pad dimensions are shown to center of bond pad
Chip size tolerance: +/- 0.051 (0.002)
GND is back side of MMIC
Bond pad #1 (RF In) 0.100 x 0.200 (0.004 x 0.008)
Bond pad #2, 3, 8, 12, 13 (Vs) 0.100 x 0.100 (0.004 x 0.004)
Bond pad #4, 11 (Vg) 0.100 x 0.100 (0.004 x 0.004)
Bond pad #5, 10 (Vctrl) 0.100 x 0.100 (0.004 x 0.004)
Bond pad #6, 9 (Vd) 0.100 x 0.100 (0.004 x 0.004)
Bond pad #7 (RF Out) 0.100 x 0.200 (0.004 x 0.008)

GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.

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 TGA2512

Recommended Chip Assembly Diagram

Option 1: Self Bias - No Gain Control

Vd

100pF

RF In RF Out

All DC connections may be brought in from either side of the chip (Use Pad 6 or 9)
0.01uF external Cap is recommended on Drain
Bias: Vd = 5V (Id = ~90mA)

GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.

15
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May 2009 © Rev -
 TGA2512

Recommended Chip Assembly Diagram (Con’t)

Option 2: Self Bias - With Gain Control

Vctrl Vd

100pF 100pF

RF In RF Out

All DC connections may be brought in from either side of the chip (Use Pad 5 or 10, and Pad 6 or 9)
0.01uF external Caps are recommended on Drain line
Bias: Vd = 5V (Id = ~90mA), Vctrl = 0 to +5V for Gain adjustment

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May 2009 © Rev -
 TGA2512

Recommended Chip Assembly Diagram (Con’t)

Option 3: Gate Bias - With Gain Control

Vg Vctrl Vd

100pF 100pF 100pF

RF In RF Out

All DC connections may be brought in from either side of the chip (Use Pad 4 or 11, Pad 5 or 10, and Pad 6 or 9)
0.01uF external Caps are recommended on Drain, Gate line, 10 ohm external
series R between 100pF cap and 0.01uF cap is recommended for Gate line
Source connections (Pad 2, 3, 8, 12, 13) are bonded to ground. All five bond wires are required for stability.
Bias: Vd = 5V , Vctrl = 0 to +5V for Gain adjustment
Vg = Range, -0.5 to 0, typically ~ -0.1 will provide ~160mA of Id.

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 TGA2512

Equivalent DC schematic

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 TGA2512

Assembly Process Notes

Reflow process assembly notes:

0
• Use AuSn (80/20) solder with limited exposure to temperatures at or above 300 C (30 seconds max).
• An alloy station or conveyor furnace with reducing atmosphere should be used.
• No fluxes should be utilized.
• Coefficient of thermal expansion matching is critical for long-term reliability.
• Devices must be stored in a dry nitrogen atmosphere.

Component placement and adhesive attachment assembly notes:

• Vacuum pencils and/or vacuum collets are the preferred method of pick up.
• Air bridges must be avoided during placement.
• The force impact is critical during auto placement.
• Organic attachment can be used in low-power applications.
• Curing should be done in a convection oven; proper exhaust is a safety concern.
• Microwave or radiant curing should not be used because of differential heating.
• Coefficient of thermal expansion matching is critical.

Interconnect process assembly notes:

• Thermosonic ball bonding is the preferred interconnect technique.

• Force, time, and ultrasonics are critical parameters.
• Aluminum wire should not be used.
0
• Maximum stage temperature is 200 C.

GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.

19
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May 2009 © Rev -