Properties and Definitions of Digital ICs

Performance specifications:
1. The range of input and output voltages.
2. Noise margin.
3. Fan-in and Fan-out.
4. Propagation Delay.
5. Power consumption.

1. The range of input and output voltages:

The digital integrated circuit is represented by five basic logic gates
operations:
NOT AND OR NAND NOR
Inverting and non-inverting elements are the fundamental building
blocks for all digital logic families

Buffers are used to regenerate (repeat), logic voltage levels, making

degraded high levels higher and degraded low levels lower. Also used
for driving and gate isolating purposes.
Ideal Transient Characteristic:
 Upon transition of the input from logic 0 to logic1, the output
immediately and without delay, switches from logic1to logic 0 and
vice versa.
 Typically the switching speed is not instantaneous and a delay
between output and input is present.
 Current drawn from the supply voltage for an ideal logic gate is zero,
giving power dissipation of zero.

 In actual digital circuits the power dissipated is minimized for

optimum design
 Logic1: is ideally at the supply voltage level
 logic 0: is ideally at the ground level (zero volt)
 Transition between output states ideally occurs abruptly at an input
equal to the half of the supply voltage
 VCC
 Logic 0 : 0 ≤ VIN ≤ 2
VCC
 Logic 1 : ≤ VIN ≤ VCC
2
VCC
 VIN = : cause unpredictable result and must avoided
2

VIL : Maximum input voltage that can be understood as logic 0 for the
next inverter.
VIH : Minimum input voltage that can be understood as logic1 for the
next gate.
VOL : Output low voltage: logic 0.
VOH : Output high voltage: logic 1.
VOH , VOL , VIL , VIH : Referred as critical voltages of the VTC
𝐕𝐎𝐇 > 𝐕𝐈𝐇 𝐕𝐈𝐋 > 𝐕𝐎𝐋
Manufacturer usually specify the worst case values of VOH , VOL , VIL , VIH
VM (Mid-point voltage): the point at which the inverter switch from one
state to the other

VM = VOUT = VIN and it is ideally appears at the center of the

transition region
Mid-point voltage (VM ) is play an important role in the design of the
inverter.

Logic Swing
Magnitude of voltage difference between the high and low output
voltage levels:
𝐕𝐋𝐒 = 𝐕𝐎𝐇 − 𝐕𝐎𝐋
Transition Width
In the transition region, the output is undefined. The width of the
transition region is a measure of confusion, and it is defined by
 𝐕𝐓𝐖 = 𝐕𝐈𝐇 − 𝐕𝐈𝐋

2. Noise in Digital Circuit:

The insensitivity of the output to the exact value of input voltage

within allowed regions is a great advantage of the digital integrated
circuit over analog counterpart.
Extraneous noise voltages must have magnitudes less than the
voltages noise margins
NMH : Noise margin high voltage
NMH = VOH − VIH
NML : Noise margin low voltage
NML = VIL − VOL
3. Fan-Out and Fan-In:
A gate draws an input current from the input signal and also delivers
current to the load gate(s). The gate acts as the load for the input
signal and as the driver for the load gates. Just as there are four
voltages, there are four currents associated with a gate and its load,
and they are defined as follows:
IOH: is the current flowing into the output terminal when it is in the
high state (logic 1).
IOL: is the current flowing into the output terminal when it is in the
low state (logic 0).
IIL: is the current flowing into the input terminal when a specified
low voltage level (logic 0) is applied to the input.
IIH: is the current flowing into the input terminal when a specified
low voltage level (logic 1) is applied to the input.
 A gate must be capable of accepting more than one input. The
number of independent input nodes is known as the fan-in.
 Fan-out is illustrated in Figure below. More precisely, fan-out is
defined as the maximum number of load gates of similar design that
can be connected to the output of a logic gate without changing its
logic state.
Since logic gates draw a different amount of current in the logic low and
logic high states, the fan-out N is given by:
 𝐈𝐎𝐇 𝐈𝐎𝐋
𝐍𝐇 = ′ 𝐚𝐧𝐝 𝐍𝐋 = ′
𝐈𝐈𝐇 𝐈𝐈𝐋

Example:
An inverter, in Figure, drives identical inverters and has VOL= 0.3V,
IOL=2mA, VOH=2.4V, IOH =100 µA, and VCC=5V.The input currents
drawn by each load inverter are IIH=0.18mA (at logic 1) and IIL=10µA
(at logic 0).
a) If there are 5 load inverters, determine the value of pull-up
resistance RP that will ensure a logic1output of VOH=2.4V?
b) If RP =4kΩ, find the fan-out N?
Solution:
a) At high output, all load inverters are connected to the driving
inverter, and each draws 0.18mA. Because of the resistance RP, the
output voltage will be lower than VCC. thus,

vO = VCC − R p (NIIH + IOH )

To ensure that: vO ≥ VOH = 2.4V.

We calculate the value of RP (for N=5) as:

 VCC − VOH (5 − 2.4)V
Rp = = = 2.6kΩ
NIIH + IOH 5 × 0.18mA + 10µA

At low output, each load inverter draws IIL = 10µA.Thus,

VCC = VOL + R p (IOL + NIIL )
VCC − VOL (5 − 0.3)V
Rp = = = 2.29kΩ
IOL + NIIL 2mA + 5 × 10µA
Since the value of R p should be in the range 2.29kΩ ≤ R p ≤ 2.6kΩ .
Let us choose R p = 2.5kΩ.
b) For R p = 4kΩ, we get the value of N at logic 1:
VCC − VOH IOH (5 − 2.4)V 0.1mA
N= − = − = 3.06 = 3
R p IIH IIH 4kΩ × 0.18mA 0.18mA
If we choose N=4, vO < VOH = 2.4V, and the inverter will be in the
logic 0 region.
4. Propagation Delay:
A switching device such as a bipolar transistor exhibits junction
capacitances. As a result, the output of an inverter may not respond
immediately to the input signal. In addition, the load gate(s) offers a
certain amount of capacitance CL to the driving inverter, as shown. CL
is the equivalent input capacitance of the load gate(s), including any
capacitance due to the wiring connection.

The input and output responses of the inverter will show finite rise time
(tr) and fall time (tf), as shown in figure (b).
tr :is the time required for the waveform to rise from 10% to 90% of its
final (high) value.
tf :is the time required for the waveform to fall from 10% to 90% of its
final (low) value.

There is a delay time between the input and output waveform; this time
is commonly known as the propagation delay time (tpd).
tpd: is defined as the time between when the input pulse waveform is at
50% of its logic high value and when the corresponding output pulse
waveform is at 50% of its logic high value.
For two edges (falling and rising), there are two delay times, denoted
as:
tPHL: for the high-to-low logic.
tPLH: for the low-to-high logic.
tpd: the average of tPHL and tPLH is the average propagation time:
 𝐭 𝐏𝐇𝐋 + 𝐭 𝐏𝐋𝐇
𝐭 𝐩𝐝 =
𝟐

tcyc (Cycle time): is the time between identical points of successive

cycles in a signal waveform.
 Practical digital systems are usually designed to operate with a cycle
time 20 to 50 times the propagation time of a single gate.
fclk (The clock frequency): which is the mutual of the cycle time, is
more often used.
5. Power Dissipation:
The power dissipation has static and dynamic components. As an
example, consider the inverter in Figure (a), where CL is the load
capacitance (normally the input capacitances of load gate).

The power consumed by an inverter depends on its logic state.

 Logic 0: When the switch S1 is closed, the current is drawn from
the supply. The power delivered by the supply is called the static
power. Thus, the static power at logic 0 is given by:
𝟐
𝐕𝐂𝐂
𝐏𝐨𝐧 =
𝐑 𝐏 + 𝐑 𝐨𝐧
Ron: The on-state switches resistance, R on ≪ R P .
 Logic 1: When the switch S1 is open, a small leakage current Ileakage
flows through the switch. The power delivered by the supply is
called the static power.Thus, the static power at logic 1 is given by:
𝟐
𝐕𝐂𝐂
𝐏𝐨𝐟𝐟 =
𝐑 𝐏 + 𝐑 𝐨𝐟𝐟
Roff: The off-state switch resistance, R off ≫ R P .
The static power is usually expressed as an average value. So the
average static power dissipation becomes:
𝟏
𝐏𝐬𝐭𝐚𝐭𝐢𝐜 = (𝐏𝐨𝐧 + 𝐏𝐨𝐟𝐟 )
𝟐
Since Poff ≅ 0
 𝟐
𝐕𝐂𝐂
𝐏𝐬𝐭𝐚𝐭𝐢𝐜 =
𝟐𝐑 𝐏

An inverter also consumes power each time it changes state.

 𝐭 − = 𝟎:
The input is high and the switch is closed. Thus, CL is discharged,
and it has no charge, as shown in Figure (a).
 𝐭 + = 𝟎:
CL will charge exponentially to the supply voltage VCC through RP,
as shown in Figure (b). The charging current will also flow
through RP, and thus power will be dissipated in RP.
 The next time:
The input becomes high, the switch is closed, as shown in Figure
(c), and CL discharges through the switch resistance Ron.
The energy stored in the CL is dissipated as heat in Ron. Therefore,
every time the capacitor CL is charged or discharged,
𝟏 𝟐
𝐄= 𝐂𝐋 𝐕𝐂𝐂
𝟐
An amount of energy must be provided by the power supply. The
𝟐
energy per cycle is 𝐂𝐋 𝐕𝐂𝐂 . The dynamic power dissipation is given by:
 𝟐
𝐏𝐝𝐲𝐧𝐚𝐦𝐢𝐜 = 𝒇𝐜𝐥𝐤 𝐂𝐋 𝐕𝐂𝐂
fclk : is the clock frequency of the inverter in hertz.
Therefore, the total power that must be supplied by the power supply is
given by:
𝐏𝐃 = 𝐏𝐬𝐭𝐚𝐭𝐢𝐜 + 𝐏𝐝𝐲𝐧𝐚𝐦𝐢𝐜

 Low 𝐏𝐃 and short propagation delay (high-speed operation) are both

desirable for digital logic circuit but both conflict with each other.
 Reducing the 𝐏𝐃 by reducing the supply voltage result in decreasing
the driving capability of the logic gate and thus lead to increase the
𝐭 𝐩𝐝 and reduce the operation speed consequently.
𝐏𝐃𝐏 = 𝐭 𝐩𝐝 𝐏𝐃
PDP: energy consumed by inverter for each transition in Jules unit.
PDP is a figure of merit for comparing logic gates. A small value of
PDP indicates that a circuit has a fast switching speed and dissipates
very little power.
Example:
The inverter shown in Figure has VOL = 0.3V, VOH =2.4V, VCC = 5V,
Ron = 500Ω , Roff =∞, RP = 2.6k Ω, CL = 5pF, and fclk = 10 MHz.
(a) Find the delay times for the output voltage to rise from 0.3V to
2.4V (tPLH) and to fall from 5V to 0.3V (tPHL)?
(b) Find the power dissipation PD?
Solution:
a) When the S1 is open, CL charges exponentially from 0.3V to 5V. The
output voltage vO(t) can be given as:
vO (t) = vO (t = ∞) + [vO (t = 0)−vO (t = ∞)]e−t⁄τ
For vO (t = 0) = 0.3V and vO (t = ∞) = 5V
 vO (t) = 5 − 4.7e−t⁄τ
vO (t) = 2.4V and τ = R P CL = 2.6kΩ × 5pF = 13ns
2.4 = 5 − 4.7e−t⁄13ns
tPLH=7.7ns
When the S1 is closed, CL discharges exponentially from 5V to 0.3V.
The output voltage vO(t) can be given as:

vO (t) = vO (t = 0)e−t⁄τ
vO (t)to fall from 2.4V to 0.3V
τ = R on CL = 500Ω × 5pF = 2.5ns
0.3 = 2.4e−t⁄2.5ns
tPHL=5.2ns
2
VCC 52
b)Pstatic = = = 4.03mW
2(R P + R on ) 2(2.6kΩ + 500Ω)
2
Pdynamic = 𝑓clk CL VCC = 500MHz × 5pF × 52 = 1.25mW

PD = Pstatic + Pdynamic = 4.03 + 1.25 = 5.28mW.

t PHL + t PLH 5.2 + 7.7
t pd = = = 6.45ns
2 2
PDP = t pd PD = 6.45ns × 5.28mW = 34.06pJ