ARM Instruction Set:
Data Processing Instructions
CMPE 364
Microprocessor Based Design
SPRING 2021
Slides prepared by Dr. Qutaibah Malluhi
Some slides are adapted from slides by Dr. M. Almeer 1
Modified by Dr. Loay Ismail
Data Processing Instruction Format
Most Data Processing Instructions follow:
MNEMONIC DST, SRC1, SRC2
Mnemonic is a short name for the operation
Like ADD, SUB, UMUL, EOR
Destination is first register listed (a GP Register = r0 – r15)
If immediate/constant data is used, it is always the last
operand
Will represent hexadecimal numbers with the prefix 0x and
binary numbers with the prefix 0b.
Data Processing Instruction Format
Most data processing instructions can process one of their
operands using the barrel shifter.
If you use the S suffix on a data processing instruction, then it
updates the flags in the CPSR.
Transfer, Arithmetic and Logical operations update the carry
flag C, negative flag N, zero flag Z and overflow flag V.
The C carry flag is set from the result of the barrel shift as the last
bit shifted out.
The N negative flag is set to bit 31 of the result.
The Z zero flag is set if the result is zero.
The V overflow flag is set if the result leads to an overflow.
Examples of ADD Instructions
ADD r0, r2, r5
ADD r3, r1, #0x2b Hex immediate
ADD r3, r11, #16 Dec. immediate
ADDS r4, r0, r2 sets the flags
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Data Processing Instructions Summary
Register movement operations:
MOV, MVN
Arithmetic operations Covered in this
ADD, ADDC, SUB, SUBC, RSB, RSC set of slides
Bit-wise logical operations
AND, EOR, ORR, BIC
Multiplication instructions
MUL, UMUL, SMUL, MLA, UMLAL, SMLAL
Comparison operations
TST, TEQ, CMP, CMN
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Register Transfer Instructions
MOV and MVN
6
MOV Instruction
Copies N (the source) into a destination register Rd, where N is a
register or immediate value.
Useful for setting initial values and transferring data between
registers
MOV DST, SRC
Syntax: <instruction>{<cond>}{S} Rd, N
MOV Move a 32-bit value into a register Rd = N
MVN Move the NOT of the 32-bit value into a register Rd = ∼N
MOV Instruction
This example shows a simple move instruction. The MOV instruction takes
the contents of register r5 and copies them into register r7, in this case,
taking the value 5, and overwriting the value 8 in register r7.
PRE r5=5
r7=8
MOV r7, r5 ; let r7 = r5
POST r5=5
r7=5
MOV Instruction
Operand N is either a register Rm or a constant preceded by #.
Example
given the instruction shown below, get r3 and r9 after execution.
Assume r3 = 0xFEEA082C and r9 = 0x8000AC40?
MOV r3, r9
Solution
r3 = 0x8000AC40 and r9 remains the same.
MOV Instruction
Example
Determine r1 after execution on next instruction assuming it contains
0x2E059401?
MOV r1, #0x0000009C
Solution
r1 = 0x0000009C
MOV Instruction
Example
Determine r10 after execution on next instruction assuming it contains
0x2E059401?
MOV r10, #384
Solution
Hex of 384 = 256 + 128
r10 = 0x00000180
MVN Instruction
Move Negative Instruction.
Has same effect of MOV instruction but copies the one’s
complement of the source to destination.
Source: general purpose register or immediate
MVN DST, SRC
MVN Instruction
Example: Determine the content of r2 and r5 after the execution
of the following instruction. Assume r2 = 0xA6E9F004, r5 =
0xCE00A824?
MVN r2, r5
Solution:
r2 = 0x31FF57DB, r5 = SAME.
MVN Instruction
Example: Determine the content of r4 after the execution of the
following instruction?
MVN r4, #24
Solution:
BEFORE: #24 = 0000 0000 0000 0000 0000 0000 0001 10002
#24 = 0x00000018.
AFTER: r4 = 1111 1111 1111 1111 1111 1111 1110 01112
r4 = 0xFFFFFFE7.
Arithmetic Instructions
ADD, ADDC, SUB, SUBC, RSB, RSC
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Arithmetic Instructions
The arithmetic instructions implement addition and subtraction
of 32-bit signed and unsigned values.
Syntax: <instruction>{<cond>}{S} Rd, Rn, N
ADC add two 32-bit values and carry Rd = Rn + N + carry
ADD add two 32-bit values Rd = Rn + N
SUB subtract two 32-bit values Rd = Rn − N
RSB reverse subtract of two 32-bit values Rd = N − Rn
SBC subtract with carry of two 32-bit values Rd = Rn − N − !(carry flag)
RSC reverse subtract with carry of two 32-bit values Rd = N − Rn − !(carry flag)
N is the result of the shifter operation. The syntax of shifter operation will be shown later.
ADD Instruction
ADD instruction adds 2 source operands SRC1 and SRC2, and
stores the result in destination register DST.
The first source operand must be general purpose register, while
the other can be a register or an immediate operand.
ADD DST, SRC1, SRC2
ADD Examples
Example:
Get r0, r3, and r9 after the next instruction, if
r0 =0x00014009
r3 =0x00326018
ADD r9, r0, r3
Answer:
r9 = 0x0033A021
r0 and r3 No Change
ADD Examples
Example:
Get r1 and r6 after the next instruction, if
r6 = 0xFFFFFFFE (-2?)
ADD r1, r6, #24
Answer:
r1 = 0x00000016 = 22.
SUB Instruction
The SUB instruction subtracts the 2nd source (SRC2) from the 1st
source (SRC1) and replaces the result in destination register (DST).
SUB DST, SRC1, SRC2
EXAMPLE: Get r4 if
r2 = 0x000006A0
r1 = 0x000003C4
SUB r4, r2, r1
SOLUTION: r4 = 0x000002DC
SUB Instruction
EXAMPLE: Get r4 if r2 = 0x000008E0?
SUB r4, r2, #0xFFFFFFFE (-2)
SOLUTION:
r4 = 0x000008E0 – 0xFFFFFFFE = 0x000008E2
RSB Instruction
RSB is Reverse Subtract Instruction.
Subtracts SRC1 from SRC2
RSB DST, SRC1, SRC2
EXAMPLE: Show how the subtracts occur? If
r3 = 0x000006BE,
r9 = 0x000009AC
RSB r8, r3, r9
SOLUTION: r8 = r9 – r3 = 0x000002EE
RSB Instruction
EXAMPLE:
Write Assembly instruction to subtract r7 from 1000 and replace
result in r7?
SOLUTION:
RSB r7, r7, #1000
EXAMPLE
Write a single code to convert the sign of r1 register without
knowing its content?
SOLUTION:
RSB r1, r1, #0
ADC Instruction: Add with Carry
Add with Carry bit
ADC DST, SRC1, SRC2
Adds the SRC1 with SRC2 with Carry bit in CPSR register and
places result in DST.
SRC1 should be a register, while SRC2 can be a register or a
immediate operand.
ADC Instruction: Add with Carry
EXAMPLE: Get r6 after the execute of next instruction if
r11 = 0x000E5FA9
r10 = 0x00005204
CF = 1
ADC r6, r11, r10
SOLUTION:
r11 = r10 + r11 + C = 0x000EB1AE
ADC Instruction: Add with Carry
EXAMPLE: Get r4 after the execution of next instruction, if
r2 = 0x80040608 and CPSR = 0x50000010?
ADC r4, r2, #134 ; (0x86)
SOLUTION:
r4 = r2 + 134 + 0 = 0x8004068E
Multiword Arithmetic Example
Write instructions to add a 64-bit integer contained in r2 and r3
to another 64-bit integer contained in r0 and r1, and place the
result in r4 and r5.
Solution:
ADDS r4, r0, r2 ; adding the least significant words
ADC r5, r1, r3 ; adding the most significant words
carry
r1 r0
+
r3 r2
r5 r4
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SBC Instruction
SBC is subtract with carry.
Subtracts the SRC2 and complement of carry bit in CPSR
register from SRC1 and places the result in DST
DST = SRC1 – SRC2 – Not(C)
SBC DST, SRC1, SRC2
EXAMPLE: Get r4 if r2 = 0x000006A0 and r1 = 0x000003C4, and
CPSR = 0x00000010?
SBC r4, r2, r1
SOLUTION: 000006A0 – 000003C4 – 1 = 000002DB
Multiword Subtraction Example
Write instructions to subtracts a 64-bit integer contained in r2
and r3 from another 64-bit integer contained in r0 and r1, and
place the result in r4 and r5.
Solution:
SUBS r4, r0, r2 ; Subtract the least significant words
SBC r5, r1, r3 ; Subtract the most significant words
Borrow
When two’s complement is used:
r1 r0 Borrow Carry=0
- No Borrow Carry=1
r3 r2
r5 r4
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RSC Instruction
RSC: Reverse Subtract with Carry
Subtracts SRC1 And complement of Carry from SRC2
and places the result in DST register.
DST = SRC2 – SRC1 – Not C
RSC DST, SRC1, SRC2
RSC Example
EXAMPLE: Get r3, if CPSR = 0x0000010,
r0 = 0x08009420,
r2 = 0x014520C0,
RSC r3, r2, r0
SOLUTION:
r3 = r0 – r2 – 1 = 08009420 – 014520C0 – 1 = 0x06BB735F
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Bitwise Logical Instructions
AND, EOR, ORR, BIC
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Logical Instructions
Logical instructions perform bitwise logical operations on the
two source registers.
Allow individual bit manipulation: at bit level
Syntax: <instruction>{<cond>}{S} Rd, Rn, N
AND logical bitwise AND of two 32-bit values Rd = Rn & N
ORR logical bitwise OR of two 32-bit values Rd = Rn | N
EOR logical exclusive OR of two 32-bit values Rd = Rn ⊕ N
BIC logical bit clear (AND NOT) Rd = Rn & ∼N
AND Instruction
Performs bitwise AND of two source operands, SRC1 and SRC2, and stores
the result in DST.
AND DST, SRC1, SRC2
SRC1 is a GP register, while SRC2 could be GP register or an immediate
operand. DST must be a GP register.
EXAMPLE: r1=0x1A89F045, r12=0x96231E8D
AND r4, r1, r12
Get r4 = ?, show bit by bit solution
SOLUTION: 1A89F045 0001 1010 1000 1001 1111 0000 0100 0101
0x12011005 96231E8D 1001 0110 0010 0011 0001 1110 1000 1101
12011005 0001 0010 0000 0001 0001 0000 0000 0101
AND Instruction
EXAMPLE: write an AND instruction to clear every bit except bits
16, 17, and 19 of register r4?
SOLUTION:
mask = 0000 0000 0000 1011 0000 0000 0000 0000
= 0x000B0000
AND r4, r4, 0x000B0000
Show in bit by bit.
ORR Instruction
Performs bitwise Inclusive OR of SRC1 and SRC2 and places the result in
DST.
SRC1 is a register while SRC2 could be a register or an immediate operand.
ORR DST, SRC1, SRC2
EXAMPLE: r6 = 0xEF486EE9, r1=0x80182ACF, what is r1 after the following
instruction?
ORR r1, r1, r6
SOLUTION: ???
0xEF586EEF EF486EE9 1110 1111 0100 1000 0110 1110 1110 1001
80182ACF 1000 0000 0001 1000 0010 1010 1100 1111
EF586EEF 1110 1111 0101 1000 0110 1110 1110 1111
ORR Instruction
EXAMPLE
Set bit positions 7 and 9 in register r0 to 1 without touching other 30
bits in the same register?
SOLUTION:
Will use an ORR instruction, ORing r1 register with a 32-bit Mask.
Mask will be = 0x --------?
ORR r0, r0, #0x00000280
EOR (Exclusive OR) Instruction
Exclusive OR which performs Exclusive OR of 2 sources, SRC1
And SRC2, and places result in DST.
EOR DST, SRC1, SRC2
SRC1: GP register, SRC2: GP register or immediate operand,
DST must be GP register.
Very useful instruction for comparison to see which bit position
they differ.
Also used in encryption and decryption with keys
EOR Instruction
EXAMPLE: Get r9? if r5 = 0x7C5D6B21, r8 = 0x9624EC30?
EOR r9, r5, r8
ANSWER:
r9 = 0xEA798711.
EXAMPLE: Invert bit 30 of r0 using a single instruction?
SOLUTION:
MASK = 0100 0000 0000 0000 0000 0000 0000 0000
= 0x40000000
EOR r0, r0, 0x40000000
BIC (Bit Clear ) Instruction
Bit Clear Instruction clears 1 bit or more in the first source
register SRC1, and stores the result in DST register
The bit positions needed for clear should be placed in SRC2
register.
bit=1 means clear and bit=0 means do not change
BIC DST, SRC1, SRC2
DST = SRC1 AND !SRC2
BIC (Bit Clear ) Instruction
Example: using a single instruction clear bit-5 in register r0?
Solution:
Mask = 0000 0000 0000 0000 0000 0000 0010 0000 =
= 0x20
BIC r0, r0, #0x20
Summary of Common Utilization of Bitwise Logical Operations
Operator Common Usage
AND Selectively mask (clear) bits
Use 0 in the position to be masked and 1 elsewhere
OR Selectively set bits
Use 1 in the position to be set and 0 elsewhere
EOR Selectively complement bits
Use 1 in the position to be complemented and 0 elsewhere
Identify which bits are different
1 in the result indicates the corresponding operand bits are different
BIC Selectively clear bits
Use 1 in the position to be masked and 0 elsewhere
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