Introduction to Embedded
System I/O Architectures
and Buses
A single bus architecture was used on
early computers.
Processor Memory I/O
Hardware
System Bus
But Modern systems are more complex and
actually contain a hierarchy of different busses!
MBED board
96MHz 32-bit ARM Cortex
M3, 32KB RAM, 512KB flash
C++ libraries
Free web-based software
tools
Programmed via USB
Ethernet, USB slave
2xSPI, 2xI2C, 3xUART,
1xCAN
GPIO, 6xPWM, 6xADCs,
1xDAC
40-pin DIP, 0.1" pitch
www.mbed.org
Mbed ARM Cortex M3
processor on NXP 1768
SoC microcontroller
chip
•512K FLASH and 32K
SRAM
•Note all of the I/O
features (bottom half of
figure) are attached to
the processor using an
internal bus, ARM’s
AHB
NXP LPC 1768 Block Diagram
A First Generation Bus Example: ISA
• ISA bus used in early PCs for Plug-in Cards
• Address Bus (SAx)
– Originally 16 bits then expanded to 24
• Data Bus (SDx)
– 8 bits then expanded to16 bits
– EISA later expanded it to 32 bits
• Bus Status Signals
– MEMR, MEMW, IOR, IOW
• 5V TTL signals
Digital Logic Review:
A simple address decoder circuit for
4-bit address (A3..A0) = 0xA = 1010B
A3
Address
A2 Decoder
A1 Output
A0
Would need to decode more address bits in an actual system
Tri-state logic gate outputs
are used to drive most bus signals
tri-state
control input output control
0 0 High Z input
0 1 High Z
1 0 0
1 1 1 input output
(bus)
New third High Z state means “not connected”
Hardware allows only one tri-state gate at a time to drive a bus signal!
Works just like a large multiplexer:
One of several inputs connects to the output
Open Collector (OC) Output
• Older and slower alternative to tri-state outputs –
can connect multiple OC outputs together
• OC gate outputs only have a circuit to drive
output low (nothing in circuit to pull high)
• 1 external resistor (1-10Kohm?) is added to pull
it high (when nothing drives it low)
• Multiple OC outputs can be tied together and
any one could pull it low
• OC is still used on I2C SDA and SCL pins
• An OC bus will not work without the resistor!
Legacy PC I/O address assignments
I/0 address range I/O device
000h – 200h Reserved for Internal Devices:
Interrupt & DMA controllers, timers
278h - 27Fh Parallel Printer (LPTx:)
2E8h - 2EFh Serial Port 4 (COM4:)
2F8h - 2FFh Serial Port 2 (COM2:)
378h - 37Fh Parallel Printer (LPT1:)
3B0h - 3BBh MDA Adapter
3BCh - 3BFh Parallel Printer (LPTx:)
3C0h - 3CFh VGA/EGA Adapter
3D0h - 3DFh CGA Adapter
3E8h - 3EFh Serial Port 3 (COM3:)
3F0h - 3F7h Floppy Controller
3F8h - 3FFh Serial Port 1 (COM1:)
Original PC design only decoded low 10 I/O address bits to save
hardware. Each I/O device must have a unique address on a bus!
An Example ISA Bus I/O Write Operation
Bus Clock
Addr ess Valid Addr ess
I/O Write
Data Valid Data
Clock data into a
register on this edge!
An Example ISA Bus I/O Read Operation
Bus Clock
Valid Address
Address
I/O Read
Data Valid Data
Typical I/O Input Port
Hardware Operation
Bus I/O Read Command
Device’s I/O Address Decoded
Address Tri-state
Address Bus Decoder Control
Circuit Data bit x
Data Bus bit x in from
I/O Device
One tri-state
gate is needed
for each bit on
the data bus
Typical I/O Output Port Hardware
Operation
R
Address e
Address Bus Decoder g
Circuit Data Bus i Data out to
s I/O Device
t
e
r
Device’s I/O Address Decoded
Bus I/O Write Command Clock
Options for Building Custom I/O ICs
• Full custom VLSI devices and Application
Specific Integrated Circuits (ASICs) have very
high setup costs – a very large volume is
required to recover development cost. Typically
can be made only by the major chip vendors.
• Field Programmable Gate Arrays (FPGAs) are
programmed by the end user. Low development
costs, but higher unit costs, slower clock rates,
and higher power levels. – only a moderate
volume needed to recover development costs
Using an HDL to design I/O hardware
-- VHDL-based Address Decoder for 0x3E0
PORT_IO_DECODE <= '1' WHEN ADDRESS = X"3E0" AND
AEN='0' ELSE '0';
-- VHDL-based I/O Input Port - use tri state buffers
DATA <= PORT_DATA_IN WHEN PORT_IO_DECODE = '1' AND
IOR = '0' ELSE "ZZZZZZZZ";
-- VHDL-based I/O Output Port – use a register (with DFFs)
PROCESS
BEGIN
-- clock on positive edge of ISA IOW
WAIT UNTIL IOW'EVENT AND IOW='1';
-- use address decoder output for the DFF clock enable
IF PORT_IO_DECODE = '1' THEN
-- save data on ISA data bus in register
PORT_DATA_OUT <= DATA;
END IF;
END PROCESS;
Software for I/O port transfers
• Can use in-line assembly language in
C/C++
• Most C/C++ compilers have built-in
function calls for I/O port input and output
• Other languages may have support for I/O
and/or typically can call C/C++ routines,
but details vary
• On RISC processors (i.e., ARM), pointers
can be used to directly access I/O ports
In-line Assembly Example for X86
// I/O Input Routine // I/O Output Routine
__asm{ __asm{
mov dx, IO_address mov dx,IO_address
in al, dx mov al,IO_data
mov IO_data,al out dx, al
} }
Problems: Does not port to other processors and many people do not
understand assembly language!
ARM Assembly Language
• See mbed wiki page on ARM assembly
language:
– https://developer.mbed.org/cookbook/Assemb
ly-Language
• I/O registers (ports) are memory mapped
on RISC processors, so Load and Store
instructions can be used directly for I/O
(unlike “in” and “out” special case on X86)
Example X86 I/O Port R/W Functions
• READ_PORT_UCHAR(I/O_Address)
– Returns 8-bit input value from input port
• WRITE_PORT_UCHAR(I/O_Address,I/O_Data)
– Sends 8-bit data value to output port
• Used in some versions of Windows
• Typically used in code for low-level device
drivers
ARM I/O Registers
• On RISC processors, I/O registers are memory
mapped, but not on X86 processors.
• C pointers set to the correct address are the
fastest way to access these I/O registers (faster
than function calls). Pointers are used in mbed’s
I/O API library code.
• Wiki page with details and examples at:
– https://developer.mbed.org/users/4180_1/notebook/cc
-io-register-names/
