PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
ARCHITECTURE AND
ORGANIZATION
MODULE 2, LESSON 1:
A TOP-LEVEL VIEW OF COMPUTER FUNCTION
AND INTERCONNECTION
By: MS. RACHELLE N. CAMACHO, MIT
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computers These Days
Consists of a CPU(s), Memory, and I/O components
Components are interconnected to achieve basic
functions.
We can characterize a computer by:
Describing the external behavior of each component (e.g. data
and Control Signals)
Describing the interconnection structure and controls required to
manage it
Chapter 3 focuses on basic structures used for computer
component interconnection (Bus, Point to Point, PI
Express, etc.)
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Components
Most computer designs take advantage of the Von Neumann
Architecture
Four components:
Control Unit
Arithmetic logic Unit
Memory
I/O
Three key concepts:
Data and instructions are stored in a single read-write memory.
The contents of this memory are addressable by location, without regard to
the type of data contained there.
Execution occurs in a sequential fashion (unless explicitly modified) from one
instruction to the next
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Components
Hardwired or Software?
Instead of rewiring the hardware for each new
program, the programmer can supply a new set
of control signals.
Program is a sequence of steps.
At each step, some arithmetic or logical
operation is performed on some data.
For each step, a new set of control signals is
needed.
Use a unique code for each possible set of
control signals
As to the general-purpose hardware a segment
that can accept a code and generate control
signals
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Components
Software
A sequence of codes or instructions
Part of the hardware interprets each instruction and generates control signals.
Provide a new sequence of codes for each new program instead of rewiring the
hardware.
Major components
CPU
Instruction interpreter
Module of general-purpose arithmetic and logic functions
I/O Components
Input module
– Contains basic components for accepting data and instructions and converting them into an
internal form of signals usable by the system
Output module
– Means of reporting results
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Components
Memory can be interpreted as
either instructions or as data
You also need registers for
exchanging data between the
CPU and the I/O module
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Components: Top-Level View
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
The basic function of a computer is to run programs
At the simplest level, you can view the work of the computer as
fetching and executing instructions (two step cycle)
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
Fetch and Execute
At the beginning of each instruction cycle the processor fetches an instruction
from memory
The program counter (PC) holds the address of the instruction to be fetched
next
The processor increments the PC after each instruction fetch so that it will fetch
the next instruction in sequence.
The fetched instruction is loaded into the instruction register (IR)
The processor interprets the instruction and performs the required action.
Processor-memory: Data may be transferred from processor to memory or from memory to
processor.
Processor-I/O: Data may be transferred to or from a peripheral device by transferring between
the processor and an I/O module.
Data processing: The processor may perform some arithmetic or logic operation on data.
Control: An instruction may specify that the sequence of execution be altered
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
Example
Consider a machine with
these characteristics
Single data register called
accumulator
Data and instructions are 16
bits
Uses 4 Bit Opcodes
Characteristics of a Hypothetical Machine
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
Example Program
How would an
example program
execute on this
machine.
Let’s take a look
Example of Program Execution (contents of memory and
registers in hexadecimal)
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
We begin in the upper left.
The program counter
contains 300 (the address of
the first instruction)
The instruction is stored as
1940 in Hex
Instruction gets loaded into
the instruction register.
Program counter will be
incremented Example Program- Step 1
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
The author writes this is
Hexadecimal, so the first
four bits correspond to the
first hex digit.
The 1st four bits (0001) in
the IR indicate to load the
Accumulator with the
contents of the address 940.
Example Program- Step 2
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
Fetch the next instruction
(5941) into the instruction
register from location 301
The program counter is also
incremented
Example Program- Step 3
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
Instruction (0101) says to
add contents of address 941
to the accumulator..
So we have a total of 3+2 = 5
in the accumulator
Example Program- Step 4
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
The next instruction 2941 is
fetched from location 302
and loaded into the
instruction register.
The program counter gets
incremented
Example Program- Step 5
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Computer Function
Instruction 2 (0010) says to
store the value from the
accumulator in location 941
So, 5 is transferred into
memory location 941
This took 3 cycles, but
different machine may
require different amounts
Example Program- Step 6
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Instruction Cycle State Diagram
Start at the instruction
address calculation
and proceed through
the maze.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Interrupts
Almost all computers provide a
way to interrupt normal
processor operations
Interrupts are a way to improve
efficiency since I/O can be a
bottleneck.
Several Types of Interrupts
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Interrupt Example
Idea is that the
processor wants to do
other things while
waiting for I/O
Program with 3 writes
Upper 1/3 no interrupt
Middle – interrupts
that require only shorts
bits of I/O
Lower Program with
long I/O waits Program Flow of Control without and
with Interrupts
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Interrupts
The user program doesn’t need to contain code to
accommodate interrupts.
To deal with them, we add an interrupt cycle to our original
instruction cycle.
Processor suspends operation of the current program and
saves status.
Sets the program counter to start of interrupt handler routine.
When interrupt handler is done, the process resumes its
original program.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Multiple Interrupts
What happens when you have more than one (1)
interrupt
There are two approaches
Disable interrupts is in progress
– Simple to implement
– Things are in order
– Doesn’t deal with relative priority
Set Priorities for Interrupts
– Most important tasks get done first
– This is bit trickier to implement
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
I/O Function
Can have I/O modules that exchange data directly with the processor.
Processor can read data from or write data to an I/O module
Processor identifies a specific device that is controlled by a particular I/O
module
I/O instructions rather than memory referencing instructions.
In some cases it is desirable to allow I/O exchanges to occur directly with
memory.
The processor grants to an I/O module the authority to read from or write to
memory so that the I/O memory transfer can occur without tying up the
processor.
The I/O module issues read or write commands to memory relieving the
processor of responsibility for the exchange.
This operation is known as direct memory access (DMA)
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Revised Instruction Cycle with Interrupts
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Interconnection Structures
Recall three types of components:
I/O, Processor and Memory
Each will have different forms of
input and output.
We need to have a way of allowing
these to communicate with one
another.
Interconnection Structure: The
collection of paths connecting the
various modules
Computer Modules
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Interconnection Structures
Memory Processor I/O to Processor I/O to or
to to processor to I/O from
processor memory memory
The previous slide
An I/O
shows the data to be module is
allowed to
exchanged. exchange
The interconnection Processor Processor
data
directly
reads an Processor reads data Processor
structure needs to instruction writes a from an I/O sends data
with
or a unit of memory
unit of data
support the following data from to memory
device via
an I/O
to the I/O
device
without
going
types of transfers memory module
through the
processor
using direct
memory
access
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Bus Interconnection
The bus was the most dominant way of interconnecting for
decades.
While point to point has taken over, you can still see bus
interconnection in embedded systems.
Bus: A communication pathway connecting two or more
devices.
Shared transmission medium
Only one device can transmit at a time.
System Bus: A bus that connects major components (e.g.
processor and memory)
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Bus Interconnection
Signals transmitted by any one device are
A communication pathway connecting two or
available for reception by all other devices
more devices.
• Key characteristics is that it is a shared transmission
attached to the bus.
• I two devices transmit during the same time period
medium
their signals will overlap and become garbled
There are three
Typically consists of multiple communication Computer systems contain a number of different different types of
lines buses that provide pathways between buses
• Each line is capable of transmitting signals components at various levels off the computer
representing binary 1 and binary 0. system hierarchy.
• Data
• Address
• Control
System bus The most common computer interconnection
• A bus that connects major computer structures are based on the use of one or more
components (processor, memory, I/O) system buses
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Data Bus
Data lines that provide a path for moving data among
system modules.
May consist of 32, 64, 128, or more separate lines.
The number of lines is referred to as the width of the
data bus
The number of lines determines how many bits can be
transferred at a time.
The width of the data bus is a key factor in determining
overall system performance.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Address Bus
Used to designate the source or destination of the data
on the data bus
If the processor wishes to read aa word of data from
memory it puts the address of the desired word on the
address lines.
Width determines the maximum possible memory
capacity of the system.
Also used to address I/O ports
The Higher order bits are used to select a particular
module on the bus and the lower order bits select a
memory location of I/O port within the module.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Control Bus
Used to control the access and the use of the data and
address lines..
Because the data and address lines are shared by all
components there must be a means of controlling their
use.
Control signals transmit both command and timing information
among system modules.
Timing signals indicate the validity of data and address
information.
Command signals specify operations to be performed
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Bus Operation
If one module wishes to send data to another, it must do two things:
Obtain the use of the bus
Transfer data via the bus
If one module wishes to request data from another module, it must
Obtain the use of the bus
Transfer a request to the other module over the appropriate control and address lines.
Wait for that second module to send the data.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Point-to-point Interconnect
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Quick Path Interconnect
Synchronizing wide buses and multi-core chips create
difficulties with bus interconnections.
Intel’s Quick Path Interconnect (QPI) was introduced to
help lower latency, increase data rate, and give better
scalability
Significant Characteristics of QPI
Multiple Direct Connections
Layered Protocol Architecture
Packetized Data Transfer
QPI in Multicore Computer
QPI links (green) form a switching fabric
Direct connections between pairs of processors
Able to connect through the I/O Hub Multicore Configuration Using
QPI
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Layered Protocol
QPI is defined as four layer model
Physical
Actual wires carry signals
Unit of Transfer is 20 bit (Phit)
Link
Transmission and Flow Control
Unit of Transfer is 80 bit (Flit)
Routing
Framework for directing packets through fabric
Protocol
QPI Layers
High-level set of rules for exchanging packets of
data between devices.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Physical Layer
The QPI port consists of
84 individual links
Lane: Each data path
consists of a pair of wires
that transmits data one
bit at a time.
There re 20 data lanes in
each direction
6.4 GigaTransfers/Second
Physical Interface of the Intel QPI
means 16GB/second Interconnect
32 GB/s if bidirectional
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Link Layer
Responsible for Transmission and Flow Control
QPI performs flow control and error control at the
Flit (80 bit) level
Typically, the message is 72 bits with an 8 bit error
code
The low control function insures that you don’t
send data faster than you can receive it via a credit
scheme
Error Control checks for errors via an 8-bit CRC
Value
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Routing and Protocol Layers
Routing Layer Protocol Layer
What it says on the tin Rules for exchanging packets of data
Used to determine the course that a between devices
packet will traverse across the Packet is defined as the unit of
available system interconnects transfer.
Defined by firmware and describe the One key function performed at this
possible path that a packet can follow level is a cache coherency protocol
which deals with making sure that
main memory values held in multiple
caches are consistent.
A typical data packet payload is a
block of data being sent to or from a
cache
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Peripheral Component Interconnect (PCI)
A popular high bandwidth, processor independent
bus that can function as a mezzanine or peripheral
bus
Delivers better system performance for high speed
I/O subsystems
Intel began work on this on 1990, but released
patents to public domain and maintained by the
PCCI Special Interest Group.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Link Layer
Point-to-point interconnect scheme intended to
replace bus-based schemes such as PCI
Key requirement is high capacity to support the
needs of higher data rate I/O devices, such as
Gigabit Ethernet
Another requirement deals with the need to
support time dependent data streams.
Chipset – connects the processor and memory
subsystem to PCI Express
Switch – manages multiple PCIe Streams
Endpoint – An I/O device or controller that
implement PCIe
Bridge – allow older PCI device to be connected
to PCIe based systems Typical Configuration Using PCIe
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
It’s Layered Too
Like QPI, it’s a layered protocol
architecture
Physical
Consists of wires carrying signals
Receipt of 1’s and 0’s
Point to Point
Data Link
Responsible for reliable transmission and flow
control
Transaction PCIe Protocol Layers
Receives read and write requests from the
software above the TL and creates request
packets for transmission to a destination via
the link layer
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
Transaction Layer Supports Four Address Spaces
Memory I/O
The memory space includes system
This address space is used for legacy PCI
main memory and PCIe I/O devices
devices, with reserved address ranges
Certain ranges of memory addresses
used to address legacy I/O devices
map into I/O devices
Configuration Message
This address space enables the TL to This address space is for control signals
read/write configuration registers related to interrupts, error handling, and
associated with I/O devices power management.
PhilCST
PHILIPPINE COLLEGE OF SCIENCE & TECHNOLOGY
OLD NALSIAN ROAD, BRGY. NALSIAN, CALASIAO, PANGASINAN
END OF MODULE 2, LESSON 1
