IEEE SOLID-STATE CIRCUITS SOCIETY/IEEE SAN FRANCISCO SECTION, BAY AREA COUNCIL/UNIV.

OF PA

2001
IEEE

4, 5, 6, 7, 8
FEBRUARY
CIRCUITS

SAN FRANCISCO
MARRIOTT HOTEL
THE INTERNET AGE:
CONFERENCE THEME
SOLID-STATE

CONFERENCE

DIGITAL CONVERGENCE
TECHNOLOGIES DRIVING
INTERNATIONAL
ADVANCE PROGRAM

WEB REGISTRATION: Hotel and Conference • ELECTRONIC PROJECTION: All Sessions

NEW! TWO WORKSHOPS:CMOS RF Circuits; Microprocessors NEW!
 ISSCC VISION STATEMENT

The International Solid-State Circuits Conference is the foremost global

forum for presentation of advances in solid-state circuits and systems-on-a-
chip. The Conference offers a unique opportunity for engineers working at
the cutting edge of IC design and use to maintain technical currency, and
to network with leading experts.

Conference Highlights

ISSCC 2001 offers a Short Course, “CMOS RF Circuits.” The course will
be held at the San Francisco Marriott Hotel on Thursday, February 8th, the
day after the closing of ISSCC 2001. Short Course sessions will be filled
on a first-come-first-served basis. You can register early and online to
ensure your place in the Short Course. Otherwise, if you register by mail,
you will be notified of your time slot, if available, prior to the Conference.
Further information can be found on pages 64 and 65 of this booklet.
ISSCC 2001 offers a choice of up to 3 of a total of 6 Tutorials on Sunday,
February 4th, the day before the official opening of the Conference. A
maximum of 3 Tutorials can be attended. Registration on-line will provide
instant, immediate confirmation of which Tutorials you can attend and at
what time. Registration by mail is an available option, but, in this case,
confirmation of your tutorial assignment will be delayed to sometime prior
to the Conference. Further information can be found on pages 62 and 63
of this booklet.
On Monday, February 5th, there will be a Social Hour for all registrants from
5:00PM to 6:30PM in the Golden Gate Hall (on the level above the
Ballroom). Author interviews will be held each day at the close of the
afternoon sessions in the South Grand Assembly (outside the Yerba Buena
Ballroom).

CONFERENCE INFORMATION

The timing of papers permits session-hopping without missing

important material. This Program shows the starting time for each paper.
Taking of pictures and videos during sessions is not permitted. A printed
supplement with speakers’ visuals will be sent to all registered attendees
within one month of the conclusion of ISSCC 2001.
A CD-ROM containing both the ISSCC 2001 Digest of Technical Papers
and the Visual Supplement (formerly the Slide Supplelment), will be sent
in late Spring to speakers and all attendees paying the member or non-
member Conference registration fee.

Contacts for further information are:

Conference Arrangements: Courtesy Associates, 2000 L St., NW, Ste 710,
Washington DC 20036, 202-973-8667; email: [email protected]
Press Information: Kenneth C. Smith, University of Toronto, Dept. of Elec.
& Comp. Eng., 10 King’s College Road, Toronto, ON M5S 3G4, Canada
Phone: 416-978-5033 FAX: 416-971-2286 email: [email protected]
Registration: ISSCC2001/SeminarSource.com
FAX: 888-833-9037, Phone: 888-833-9036

ISSCC 2001 is sponsored by the IEEE Solid-State Circuits Society. Co-

sponsors are the IEEE San Francisco Section and Bay Area Council, and
the University of Pennsylvania.
For ISSCC, see website: http://www.isscc.org

2
 CONTENTS

PAPER SESSIONS
Plenary Session................................................................................ 4
Non-Volatile Memory......................................................................... 6
Oversampling Converters ................................................................. 8
High-Speed Digital Interfaces ........................................................... 10
Gigabit Optical Communications I..................................................... 12
CMOS Image Sensors with Embedded Processors .......................... 14
DISCUSSION SESSIONS
E1 Does Fabless Mean Futureless for Imaging? .............................. 16
E2 10 Years of RF-CMOS – But How Many Products Today? .......... 16
E3 Has Scaling Created a Microprocessor Monster? ........................ 17
E4 How Will Future Portable Systems Store and Access
Data: Disk, Semiconductor Memory, Emerging Technology,
or via the Internet?............................................................................ 17
PAPER SESSIONS
TD: Advanced Technologies ............................................................. 18
Nyquist ADCs.................................................................................... 20
Integrated Multimedia Processors..................................................... 22
Wireless Building Blocks I................................................................. 24
SRAM ............................................................................................... 26
Signal Processing for Storage and Coding........................................ 28
Wireless LAN.................................................................................... 30
Gigabit Optical Communications II.................................................... 32
Microprocessors ............................................................................... 34
Integrated MEMS and Display Drivers .............................................. 36
Conference Timetable .................................................................... 40-41
Registration and Reservation Forms........................................Inserts
DISCUSSION SESSIONS
E5 Embedded DRAM: Curiosity or Workhorse?................................ 38
E6 Broadband Access – Who Will Win the Race: Copper, Fiber or
Wireless?.......................................................................................... 38
E7 100cubed: Science or Fiction? Is It Possible to Design a
100mm2 System-on-Chip with 100M Transistors in 100
days?................................................................................................ 39
E8 Are Startups Killing Innovation?................................................... 39
PAPER SESSIONS
TD: 3D Technologies and Measurement Techniques........................ 42
3G Wireless...................................................................................... 44
Voiceband, xDSL and Gigabit Ethernet Circuits and Transceivers .... 46
Multi-Gigahertz Microprocessor Technologies .................................. 48
Signal Processing for Communications ............................................ 50
TD: System-on-a-Chip ...................................................................... 52
Analog Techniques ........................................................................... 54
DRAM............................................................................................... 56
Clock Generation and Distribution..................................................... 58
Wireless Building Blocks II................................................................ 60
Tutorials .......................................................................................... 62
Short Course ................................................................................... 64
Workshop On Microprocessor Design.......................................... 66
SSCTC Workshop ........................................................................... 67
Information...................................................................................... 68
Committees ..................................................................................... 71
Conference Space Layout ................................................................ 76-77

3
 SESSION 1 SALON 7-9

PLENARY SESSION – INVITED PAPERS

Chair: John Trnka, IBM Corp., Rochester, MN

ISSCC Executive Committee Chair
Associate Chair: Glenn Gulak, University of Toronto,
Toronto, Canada
ISSCC Program Committee Chair

FORMAL OPENING OF CONFERENCE 8:30 AM

1.1 i-mode: 21st Century Mobile Internet 8:40 AM

Kei-ichi Enoki, NTT DoCoMo, Tokyo, Japan

Mobile telephone services in Japan are expanding rapidly. The number of

users exceeds 60M, surpassing the number of fixed phone subscribers. In
this market, much attention has been focused on “i-mode.” i-mode has
commanded an increasing number of subscribers since service began,
2/22/99, reaching 12M subscribers in 18 months. i-mode mobile phones
feature browsers that read HTML, and send and receive e-mail or obtain
information off of the Web. i-mode offers information on 1,100 portal sites
from 600 companies, with contents covering: airline and concert tickets,
book and CD sales, downloads of games, animations, and ringer tones,
horoscopes, restaurant guides, news and weather forecasts, and banking
and trading. There are already >23k independent Web sites accessible by
inputting URL address, and >200 search engines. In the future, i-mode will
feature Java technology and Secure Socket Layer (SSL) functions, and in
the era of IMT2000 (3rd Generation), image transmission will become a
reality.
The i-mode will change how things are done and assist in creating new
industries, not only in mobile communications, but also in many other
businesses. It will be at the core of an IT revolution as a Mobile Internet
Platform, and contribute to constructing a more affluent society.
Progress in IC technologies will have a significant effect on i-mode
evolution. The key to i-mode evolution is processors that handle audio
signals and execute a variety of applications. This paper discusses the
current status and future of i-mode services, and IC and other component
technologies in the context of these services.

ISSCC, SSCS, JSSC, & IEEE AWARD PRESENTATIONS 9:30 AM

BREAK 10:00 AM

4
 Monday, February 5th 8:30 AM

1.2 Broadband Access: the Last Mile 10:15 AM

L. Cloetens, Alcatel Microelectronics, Zaventem, Belgium

Driven by deregulation, a multitude of new transmission technologies have

been deployed and standardized in recent years.
The classical plain old telephony service (POTS) network is reused for DSL
applications. Optical fiber is increasingly deployed in new networks, though
its cost is still high. Air interface is used in sparsely-populated areas when
deployment speed is needed. Although all these media intend to bring
broadband to the home, they do it differently, using transmission principles,
which affect parameters such as line coding and equalization. They offer
different bandwidths (less for twisted pair, highest for optical fiber) and
differ in network topology (point-to-point or point-to-multi-point).
Because of complex evolving standards, proposed architectures are at
least partly based on programmable platforms consisting of DSPs,
standard processors, and control memories. This approach is
complemented by downloadable software. Design is dominated by analog
aspects. Achieving transmission performance with reasonable power
consumption needs to be tackled by new structures for analog drivers,
power amplifiers, ADCs, and DACs.
Three families of access technology are discussed: DSL, best-known of the
broadband technologies, outpacing the others in deployment speed;
wireless in the local loop (WLL) and local multipoint distribution system
(LMDS); and point-to-multipoint optical (PON) offering large bandwidth.

1.3 Microprocessors for the New Millennium – 11:05 AM

Challenges, Opportunities and New Frontiers
Patrick P. Gelsinger, Intel Corp., Hillsboro, OR

As designs become more complex, technology scaling more difficult, and

power issues more pressing, “business as usual” no longer suffices, if the
industry is to continue its long-standing tradition of microprocessor
innovation. To provide means for system performance advancements and
power management, there must be focus on all aspects of the computing
platform – architecture, micro-architecture, bus memory, and I/O
performance – much more than in the past.
Multithreading and multi-core computer micro-architectures will increase
both general-purpose and networking processor MIPS. Transaction-
focused server processors will benefit from large on-die caches. Special-
purpose architectures and circuit techniques will be required to deliver
performance with higher efficiency. Future microprocessors will evolve as
integration of DSP capabilities becomes imperative to enable such
applications as media-rich communications, computer vision, and speech
recognition. These advances in processing natural data will lead to a
change in the computing paradigm from today’s data-based, machine-
based computing to tomorrow’s knowledge-based, human-based
computing. As the Internet becomes more integral to businesses and
consumers, there will be new uses for and users of microprocessors.
All this can be accomplished only with wired and wireless high-bandwidth
Internet connectivity, driven by high-performance compute servers to fulfill
the demand of computing in the Internet economy. This is computing
anytime, anywhere, anyway the user wants it.

CONCLUSION 11:55 AM

5
 SESSION 2 SALON 1-6

NON-VOLATILE MEMORY

Chair: Mark Bauer, Intel, Folsom, CA

Associate Chair: Takayuki Kawahara, Hitachi, Tokyo, Japan

2.1 A 3.3V 1Gb Multi-Level NAND Flash Memory with Non-

Uniform Threshold Voltage Distribuition
1:30 PM
T. Cho, Y. Lee, E. Kim, J. Lee, S. Choi, S. Lee, D. Kim, W. Han, Y. Lim, J.
Lee, J. Choi, K. Suh
Samsung Electronics, Kyunggi, Korea

A 1Gb NAND flash memory with 2b per cell uses 0.15µm CMOS and
achieves simultaneous operation of 4 independent banks with 1.6MB/s
program throughput. Fusing enables changing to 512Mb 1b per cell NAND
flash memory. Wordline ramping minimizes noise and peak current. Disturb
mechanisms and noise related VTH distribution shifts are minimized to
improve read margins.

2.2 A 126.6mm2 AND-Type 512Mb Flash Memory with 1.8V

Power Supply
2:00 PM
T. Ishii1, K. Oshima1, H. Sato1, S. Noda1, J. Kishimoto1, H. Kotani1, A.
Nozoe , K. Furusawa , T. Yoshitake , M. Kato , M. Takahashi , A. Sato1, S.
1 1 1 1 1

Kubono2, K. Manita2, K. Kouda3, T. Nakayama3, A. Hosogane3

1
Hitachi Ltd., Tokyo, Japan
2
Hitachi ULSI Systems Co., Ltd., Tokyo, Japan
3
Mitsubishi Electric Corporation, Tokyo, Japan

A 512Mb AND-type flash memory in 0.18µm CMOS achieves a die size of

126.6mm2, uses a multilevel technique, and adapts to 1.8V operation. In
addition, a read-modify-write mode enables programming free from pre-
programmed states.

2.3 A 1.8V 64Mb 100MHz Flexible Read-while-Write Flash

Memory
2:30 PM
B. Pathak, G. Christensen, M. Goldman, R. Haque, J. Jorgensen, R.
Kajley, T. Ly, F. Marvin, S. Monasa, Q. Nguyen, D. Pierce, A. Sendrowski,
I. Sharif, H. Shimoyoshi, A. Smidt, R. Sundaram, M. Taub, R. Trivedi, P.
Walimbe, A. Cabrera, E. Yu
Intel Corporation, Folsom, CA

A flash memory with flexible multi-partition architecture allows

programming or erasing in one partition while reading from another
partition. The 64Mb memory uses a 0.18µm process that has a 0.32µm2
cell. The device has 18ns asynchronous page mode access and
synchronous burst reads up to 100MHz with zero wait state.

BREAK 3:00 PM

6
 Monday, February 5th 1:30 PM

2.4 An Embedded 1.2V read Flash Memory Module in a 0.18µm

Logic Process.
3:15 PM
T. Ditewig1, R. Cuppens1, K. Chen2, V. Frowijn2, F. Jetten2, W. Kalkman2,
M. Malabry2, A. Slenter2, M. Storms2, N. Tandan2, S. Teuben2, J. Grácio3
1
Philips Research laboratories, Eindhoven, The Netherlands
2
Philips Semiconductors
3
TIM AG

An embedded flash memory module has 1.2V read capability and a 1.5V
program/erase capability. The flash cell is 2-transistor FN-NOR in a
0.18µm logic process. Design techniques improve observability and reduce
test time.

2.5 A Highly-Reliable 1T1C 1Mb FRAM with Novel Ferro-

Programmable Redundancy Scheme
3:45 PM
C. Ohno1, H. Yamazaki1, H. Suzuki1, E. Nagai1, H. Miyazawa1, K. Saigoh1,
T. Yamazaki1, Y. Chung2, W. Kraus2, D. Verhaeghe2, G. Argos2, J.
Walbert2, S. Mitra2
1
Fujitsu Limited, Tokyo, Japan
2
Ramtron International Corporation, Colorado Springs, CO

Two key design techniques improve margins of the 1T1C, 1Mb FeRAM.
One is a redundancy scheme utilizing the same ferroelectric capacitor as
used in the memory cell, which can be implemented without additional
process steps. The other is an externally controllable dummy cell reference
that mimics memory cell properties and also finds weak cells prior to repair.

2.6 A Nonvolatile Ferroelectric RAM with Common-Plate Folded

Bit-line Cell and Enhanced Data Sensing Scheme
4:15 PM
B. Jeon, M. Choi, Y. Song, K. Kim
Samsung Electronics Co., Kyunggi, Korea

A 4Mb 1T1C FeRAM with a common-plate folded bit-line architecture

achieves low noise without cell area penalty in nonvolatile ferroelectric
RAM. The decoder of common plate scheme reduces area to about 62%
that of a conventional separate-plate scheme. The chip area is reduced by
9.2% to 111 mm2. The bit-line capacitance imbalance is resolved without
speed loss or area penalty.

2.7 A 76mm2 8Mb Chain Ferroelectric Memory

4:45 PM
D. Takashima, Y. Takeuchi, T. Miyakawa, Y. Itoh, R. Ogiwara, M.
Kamoshida, K. Hoya, S. Doumae, T. Ozaki, H. Kanaya, M. Aoki, K.
Yamakawa, I. Kunishima, Y. Oowaki
Toshiba Corporation, Yokohama, Japan

An 8Mb chain FeRAM uses 0.25µm 2-metal CMOS technology. A one-

pitch-shift cell realizes 5.2µm2 cell area. A chain architecture with a
hierarchical wordline scheme gives 76mm2 die. Random access time is
40ns, and cycle time is 70ns at 3.0V.

CONCLUSION 5:15 PM

7
 SESSION 3 SALON 7

OVERSAMPLING CONVERTERS

Chair: David Robertson, Analog Devices, Wilmington, MA

Associate Chair: Axel Thomsen, Cirrus Logic, Austin, TX

3.1 A 13.5mW, 185MSample/s ǻȈ-Modulator for UMTS/GSM

Dual-Standard IF Reception
1:30 PM
T. Burger, Q. Huang
Swiss Federal Institute of Technology (ETH), Zurich, Switzerland

To accommodate drastically different symbol rates, signal bandwidth and

SNR requirements between WCDMA and GSM, the IF frequency, sample-
rate and converter architecture are optimized for a dual-standard ǻȈ-
modulator. In the system and circuit design, attention is given to low power
consumption to achieve 135 mW at 185 MSample/s. Measured dynamic
range is 53dB for WCDMA and 84dB for GSM.

3.2 A 5mW Ȉǻ Modulator with 84dB Dynamic Range for

GSM/EDGE
2:00 PM
O. Oliaei, P. Clement, P. Gorisse
Motorola SPS, Toulouse, France

A Ȉǻ modulator in 0.35µm technology for GSM/EDGE applications has

13MHz clock. Frequency is 13 MHz. The modulator achieves 84dB
dynamic range and 82dB peak SNDR over 180kHz bandwidth. Power
dissipation is 5mW from 1.8/2.4V supplies. Active area is 0.4mm2.

3.3 A Quadrature Data Dependent DEM Algorithm to Improve

Image Rejection of a Complex Ȉǻ Modulator
2:30 PM
L. Breems1, C. Dijkmans1, J. Huijsing2
1
Philips Research Labs, Eindhoven, The Netherlands
2
TU Delft, Delft, The Netherlands

A data-dependent DEM algorithm is controlled by the quadrature

bitstreams of a complex Ȉǻ modulator. The quadrature feedback paths of
the modulator are dynamically matched, without increasing the in-band
noise. Test chips with an initial 20% mismatch have a typical image
rejection ratio of 61dB with DEM.

BREAK 3:00 PM

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 Monday, February 5th 1:30 PM

3.4 A 2.5V Broadband Multi-Bit Ȉǻ Modulator with 95dB

Dynamic Range
3:15 PM
K. Vleugels1, S. Rabii2, B. Wooley1
1
Stanford University, Stanford, CA
2
Atheros Communications, Inc.

A cascaded multi-bit Ȉǻ modulator uses double sampling to achieve a

conversion rate of at least 4MSample/s at an oversampling ratio of 16.
Partitioned data-weighted averaging extends the dynamic range to 95dB.
The circuit, integrated in 0.5µm CMOS, dissipates 150mW from a 2.5V
supply.

3.5 A 1V 10.7MHz Switched-Opamp Bandpass Ȉǻ Modulator

Using Double-Sampling Finite-Gain-Compensation
Technique
3:45 PM
V. Cheung, H. Luong, W. Ki
Hong Kong University of Science & Technology, Hong Kong, China

A 1V 10.7MHz switched-opamp bandpass Ȉǻ modulator uses modified

double-sampling finite-gain-compensation. In a standard 0.35µm CMOS
process at 1V supply, the modulator achieves 42.8MHz effective sampling
frequency with 42.3dB peak SNDR while dissipating 12mW in 1.3mm2 chip
area.

3.6 A Low-Power Reconfigurable Analog-to-Digital Converter

4:15 PM
K. Gulati, H. Lee
Massachusetts Institute of Technology, Cambridge, MA

A reconfigurable analog-to-digital converter digitizes signals over a 1Hz -

10MHz bandwidth and 6 to 16b resolution with adaptive power
consumption. The converter achieves this by reconfiguring between
pipeline and ǻȈ architectures and adjusting circuit parameters and bias
currents.

CONCLUSION 4:45 PM

9
 SESSION 4 SALON 8

HIGH-SPEED DIGITAL INTERFACES

Chair: Kerry Bernstein, IBM Microelectronics, Essex Junction, VT

Associate Chair: Paul Landman, Texas Instruments, Dallas, TX

4.1 A Serial-Link Transceiver Based on 8GSample/s A/D and

D/A Converters in 0.25µm CMOS
1:30 PM
W. Ellersick1, V. Stojanovic1, M. Horowitz1, S. Modjtahedi2, C. Yang2
1
Stanford University, Stanford, CA
2
University of California, Los Angeles, CA

On-chip VCOs generate 16 clock phases which drive an 8-way interleaved

4b A/D input receiver and an 8-way interleaved 8b D/A transmitter. 4GHz
bandwidth is achieved by inductors that distribute the I/O capacitance and
a transmit equalizer. Digital calibration adjusts the sample timing to 10ps,
the input and output accuracy to <1 LSB and 3 LSBs, respectively.

4.2 A 2Gb/s 21CH Low-Latency Transceiver Circuit for Inter-

Processor Communication
2:00 PM
T. Tanahashi1, M. Kurisu1, H. Yamaguchi1, T. Nedachi1, M. Arai1, S.
Tomari , T. Matsuzaki , K. Nakamura , M. Fukaishi , S. Naramoto2, T.
1 1 1 1

Sato2
1
NEC Corp., Tokyo, Japan
2
NEC Engineering Ltd., Kawasaki, Japan

A 20-data-channel transceiver with a control channel allows uncoded data

transfer with 13ns latency. A digital DLL with a ring-interpolator tracks
phase with 20ps resolution. A pre-emphasis driver enables 2Gb/s
transmission per channel over a 7m cable at 1.5V. The effective full-duplex
bandwidth reaches 10GB/s.

4.3 3.2GHz 6.4Gb/s/wire Signaling in 0.18µm CMOS

2:30 PM
M. Haycock, S. Mooney
Intel Corporation, Hillsboro, OR

Simultaneous bidirectional signaling provides 6.4Gb/s/wire with random

data on a 22b point-to-point bus over 15cm on a PCB. The signaling rate
decreases to 2.4Gb/s/wire over 122cm through 2 connectors. The I/O
circuits have closed-loop slew rate control and are part of a 6.6M transistor
router component that consumes 21W, packaged in a 31x31mm2 OLGA
substrate.

BREAK 3:00 PM

10
 Monday, February 5th 1:30 PM

4.4 5Gb/s Bidirectional Balanced-Line Link Compliant with

Plesiochronous Clocking
3:15 PM
H. Tamura1, M. Kibune1, Y. Takahashi1, Y. Doi1, T. Chiba2, H. Higashi1, H.
Takeuchi1, H. Ishida1, K. Gotoh1
1
Fujitsu Laboratories LTD., Kawasaki, Japan
2
Fujitsu Hokkaido Digital Technology, Hokkaido, Japan

A 6ns-latency 12mW 5Gb/s bidirectional link for short-haul (<5m) balanced

lines uses an on-chip switched-capacitor hybrid with echo-canceling
capability. The clock-recovery circuit, based on a phase interpolator,
makes the link tolerant to a 100ppm difference between the frequencies of
the transmit and receive clocks.

4.5 A 2Gb/s/pin 4-PAM Parallel Bus Interface with Transmit

Crosstalk Cancellation & Equalization and Integrating
Receivers
3:45 PM
J. Zerbe, P. Chau, C. Werner, W. Stonecypher, H. Liaw, G. Yeh, T. Thrush,
S. Best, K. Donnelly
Rambus Inc., Mountain View, CA

A 2Gb/s/pin single-ended 4-PAM parallel bus interface uses transmit

crosstalk cancellation and equalization techniques as well as integrating
data receivers to improve system margin in low-cost packaging despite
inherent coupling noise and data distortion.

4.6 Digitally-Controlled DLL and I/O Circuits for 500Mb/s/pin x16

DDR SDRAM
4:15 PM
J. Lee, K. Kim, C. Yoo, S. Lee, O. Na, C. Lee, H. Song, J. Lee, Z. Lee, K.
Yeom, H. Chung, I. Seo, M. Chae, Y. Choi, S. Cho
Samsung Electronics, Kiheug, Korea

DLL and improved I/O circuits are for 500Mb/s/pin DDR SDRAM. This
digitally-controlled DLL has inherent duty cycle correction capability,
enabling fast re-locking upon standby-mode exit. Data input circuits, such
as internal delay control and digital sense amplifier, reduce setup/hold
window to 0.3ns. The output data driver has 62% decreased pattern-
dependent skew.

4.7 Circuit Design for a 2.2GB/s Memory Interface

4:45 PM
S. Sidiropoulos, A. Abhyankar, C. Chen, K. Chang, T. Chin, N. Hays, J.
Kim, Y. Li, G. Tsang, A. Wong, D. Stark
Rambus Inc, Mountain View, CA

A 2.2GB/s signaling interface for main memory uses a DLL which allows
for in-system timing calibration with 1.4o resolution, and output drivers with
limited positive feedback to increase voltage margin. In a 0.25µm CMOS
process, the prototype chips operate to 2.6GB/s.

CONCLUSION 5:15 PM

11
 SESSION 5 SALON 9

GIGABIT OPTICAL COMMUNICATIONS I

Chair: Rick Walker, Agilent Technologies, Palo Alto, CA

Associate Chair: H. Tamura, Fujitsu Laboratories, Kawasaki, Japan

5.1 An Offset-Cancelled CMOS Clock Recovery/Demux with a

Half-Rate Linear Phase Detector for 2.5Gb/s Optical
Communication
1:30 PM
P. Larsson
Lucent Technologies, Holmdel, NJ

A 2.5Gb/s optical receiver clock-recovery circuit in 0.25µm CMOS features

4mV sensitivity and offset cancellation to enable an integrated limiting
amplifier. A linear phase detector using a half-rate clock relaxes speed
requirements. An active on-chip loop filter capacitor gives <0.1dB jitter
peaking.

5.2 Fully-Integrated SONET OC48 Transceiver in Standard

CMOS
2:00 PM
A. Momtaz, J. Cao, M. Caresosa, A. Hairapitian, D. Chung, K. Vakilian, M.
Green, B. Tan, K. Jen, I. Fujimori, G. Gutierrez, Y. Cai
Newport Communication, Irvine, CA

A fully-integrated transceiver in standard 0.18µm CMOS exceeds all

SONET OC-48 requirements. The serial interfaces are 2.488 or 2.667Gb/s
CML and the parallel ones are 622 or 666Mb/s LVDS. The output clock
rms jitter is 1ps and total power consumption including all the input/output
interfaces is 500mW.

5.3 A 10Gb/s CMOS Clock and Data Recovery Circuit with

Frequency Detection
2:30 PM
J. Savoj, B. Razavi
UCLA, Los Angeles, CA

A 10Gb/s phase-locked clock and data recovery circuit incorporates a

multiphase LC oscillator and a half-rate phase/frequency detector with
automatic data retiming. In 0.18µm CMOS technology, the circuit exhibits
1.43GHz capture range and 0.8ps rms jitter with length 223-1 PRBS. The
power dissipation is 91mW from a 1.8V supply.

BREAK 3:00 PM

12
 Monday, February 5th 1:30 PM

5.4 A 10Gb/s 16:1 Multiplexer and 10GHz Clock Synthesizer in

0.25µm SiGe BiCMOS
3:15 PM
H. Cong, S. Logan, M. Loinaz, K. O'Brien, E. Perry, G. Polhemus, J.
Scoggins, K. Snowdon, M. Ward
Lucent Technologies, Holmdel, NJ

A 10Gb/s 16:1 multiplexer, 10GHz clock generator, and 6×16b input data
buffer are integrated in SiGe BiCMOS. The chip exhibits SONET generated
jitter of 0.048UIpp with 0.04dB maximum jitter peaking and dissipates 1.6W
from 3.3V. The input data buffer accommodates ±2.4ns input data phase
drift at 622Mb/s.

5.5 A Single-Chip 10Gb/s Transceiver LSI using SiGe

SOI/BiCMOS
3:45 PM
S. Ueno1, K. Watanabe1, T. Kato1, T. Shinohara2, K. Mikami2, T.
1 1 1 1
Hashimoto , A. Takai , K. Washio , R. Takeyari , T. Harada
1
Hitachi, Ltd., Yokohama, Japan
2
Hitachi ULSI Systems Co., Ltd., Tokyo, Japan

A fully-integrated single-chip SiGe SOI/BiCMOS transceiver LSI for 10Gb/s

applications combines 4b FIFO, 10GHz PLL, 16:1 MUX, 10Gb/s input data
decision circuit, clock and data-recovery circuit, 1:16 DeMUX, data loop
back function, and self-testing using 223-1 PRBS generator. The die is
5.6x5.3mm2 and consumes 2.6W from 3.3/2.5V.

5.6 40Gb/s Clock and Data Recovery / 1:4 DEMUX IC in SiGe

Technology
4:15 PM
M. Reinhold1, C. Dorschky1, R. Pullela2, P. Mayer1, P. Paschke1, Y.
Baeyens1, J. Mattia3, F. Kunz1
1
Lucent Technologies, Nuremberg, Germany
2
Gtran
3
Big Bear Networks

A 40Gb/s clock and data recovery (CDR) IC with 1:4 demultiplexer

(DEMUX) is fabricated in a SiGe technology. The architecture provides
robust operation combined with a high level of integration, dissipating 4.8W
from a 5.5 V supply.

CONCLUSION 4:45 PM

13
 SESSION 6 SALON 10-15

CMOS IMAGE SENSORS WITH EMBEDDED PROCESSORS

Chair: Philip Wong, IBM T.J. Watson Research Center, Yorktown

Heights, NY
Associate Chair: Fritz Kub, Naval Research Lab, Washington, DC

6.1 A 10kframes/s 0.18µm CMOS Digital Pixel Sensor with Pixel-

Level Memory
1:30 PM
S. Kleinfelder, S. Lim, X. Liu, A. El Gamal
Stanford University, Stanford, CA

A 352x288 pixel CMOS image sensor with pixel-level single-slope ADC

and 8b 3T DRAM cells achieves 9.4x9.4µm2 pixel in standard 0.18µm
CMOS. Continuous 10kframes/s (1Gpixels/s) 8b per pixel snap-shot image
acquisition is achieved with 0.1% rms temporal noise and 0.18% rms FPN.

6.2 A Miniature Imaging Module for Mobile Applications

2:00 PM
J. Hurwitz1, S. Smith1, A. Murray1, P. Denyer1, J. Thomson1, S. Anderson1,
E. Duncan1, A. kinsey1, B. Paisley1, E. Christison1, B. laffoley1, J. Vittu1, R.
Bechignac1, R. Henderson1, M. Panaghiston1, P. Pugibet1, H. Hendry1, K.
Findlater2
1
ST Microelectronics, Edinburgh, United Kingdom
2
Edinburgh University, Edinburgh, United Kingdom

A miniature mobile imaging module combines a 0.5µm CMOS CIF imager

with a 0.18µm co-processor within a compact lensed package. It provides
15frames/s ITU-Rec.656 data with 50mW consumption. Automatic flicker-
detection is one of the features that help the camera function in a mobile
application.

6.3 Arbitrated Address Event Representation Digital Image

Sensor
2:30 PM
E. Culurciello1, R. Etienne-Cummings1, K. Boahen2
1
Johns Hopkins University, Baltimore, MD
2
Unversity of Pennsylvania, Philadelphia, PA

80x60 (1/8 VGA) address event imager in 0.6µm CMOS converts light
intensity into a one-bit code (a spike). The read-out of each spike is
initiated by the pixel. The dynamic range is 200dB for a pixel and 120dB for
the array. It uses 3.4mW at a spike rate of 200kHz. It is capable of 8.3k
effective frames/s.

BREAK 3:00 PM

14
 Monday,February 5th 1:30 PM

6.4 A 48kframes/s CMOS Image Sensor for Real-Time 3-D

Sensing and Motion Detection
3:15 PM
S. Yoshimura1, T. Sugiyama2, K. Yonemoto2, K. Ueda
1
Sony-Kihara Research Center, Inc., Tokyo, Japan
2
Sony Corporation, Tokyo, Japan

A CMOS image sensor with 192x124 pixels realizes video-rate range

sensing with 500µm depth resolution, motion detection, and 12b digital
image output. Each pixel consists of four current copier cells as a frame
memory block and a chopper comparator. The imager operates at
48kframes/s maximum rate and dissipates 1.6W for range sensing and 2W
for digital imaging at 3.3V in a 0.35µm process.

6.5 A 128x128 CMOS Imager with 4x128 Bit-Serial Column-

Parallel PE Array
3:45 PM
H. Yamashita1, C. Sodini2
1
Toshiba, Yokohama, Japan
2
Massachusetts Institute of Technology, Cambridge, MA

A 4x128 fine-grained bit-serial processing element array configured with

four 1x128 SIMD processors is embedded in 128x128 pixel CMOS imager
columns. The prototype imager chip performs ~220operations/pixel at
20MHz clock, which potentially affords pixel-rate color processing for VGA
format image.

6.6 A Signal-Processing CMOS Image Sensor using a Simple

Analog Operation
4:15 PM
Y. Muramatsu, S. Kurosawa, M. Furumiya, H. Ohkubo, Y. Nakashiba
NEC Corporation, Kanagawa, Japan

A high-density CMOS image sensor has a normal mode and three signal-
processing function modes: wide dynamic-range mode, motion-detection
mode, and edge-extraction mode. Small pixel and real-time operation are
achieved by using a 4 transistor pixel scheme and column-parallel on-chip
analog operation.

6.7 Autoscaling CMOS APS with Customized Increase of

Dynamic Range.
4:45 PM
O. Yadid-Pecht, A. Belenky
Ben-Gurion University, Beer-Sheva, Israel

A 64x64 CMOS active pixel sensor uses autoscaling and a floating-point

representation to achieve wide dynamic-range linear output. The chip
features a new architecture enabling a customized number of additional
bits per pixel readout, with minimal effect on the sensor spatial and
temporal resolution.

CONCLUSION 5:15 PM

15
 DISCUSSION SESSIONS

E1 Does Fabless Mean Futureless for Imaging?

(Salon 1-6)
Organizer: Albert Theuwissen, Philips Semiconductors, Eindhoven, The
Netherlands
Moderator: Daniel Mc Grath, Atmel, San Jose, CA

CCDs are claimed to be too expensive because of dedicated fabrication

process. The promises of CMOS imaging include integration and low-cost
due to standard processes. There is a trend toward modified CMOS
processes to improve imaging performance. Is this necessary for electronic
imaging in all of its forms? Will foundries be able to do this? Will it make
business sense? Does this mean that the fabless model is a dinosaur?

Panelists:
Hideshi Abe, Sony, Kanagawa, Japan
Ed Chen, TSMC, Hsin-chu, Taiwan,
Bedrich Hosticka, Fraunhoffer Institute, Duisburg, Germany,
Jed Hurwitz, ST Vision, Edinburgh, UK,
Sabrina Kemeny, Photobit, Pasadena, CA
Woodward Yang, Harvard, Cambridge, MA and Hyundai, Korea

E2 10 Years of RF-CMOS - But How Many Products Today?

(Salon 7)
Organizer/Moderator: Rudolf Koch, Infineon Technologies, Munich,
Germany

After 10 years of design effort on RF CMOS building blocks and numerous

papers on VCOs, there are still no volume-production products employing
only >0.5GHz CMOS and with no bipolar. Does it just take long for a new
technique to mature or, is CMOS still not advanced enough? Is the digital
sub-µm CMOS supply voltage too low for RF circuits? Is system-on-chip
integration with RF CMOS too complex for today's design tools or is
interfacing a high-impedance MOST with low-impedance RF filters etc. too
complex and sensitive? Are bipolar RF designers old-fashioned and
conservative? Will CMOS ever make it for RF?

Panelists:
Barry Gilbert, Analog Devices, Beaverton, OR
Sven Mattison, Ericsson, Lund, Sweden
Michiel Steyaert, KU Leuven, Belgium
Josef Fenk, Infineon Technologies, Munich, Germany
Frank Op't Eynde, Alcatel Microelectronics, Zaventem, Belgium
Tsuneo Tsukahara, NTT, Kanagawa, Japan

16
 DISCUSSION SESSIONS

E3 Has Scaling Created a Microprocessor Monster?

(Salon 8)
Organizer: Kerry Bernstein, IBM Microelectronics, Essex Jct., VT
Moderator: David Greenhill, Sun Microsystems, Palo Alto, CA

With generations of aggressively-scaled CMOS technologies and

innovative schemes such as parallelism, speculative branching, out-of-
order instruction execution, and pipelining architects have improved
performance at the cost of power and die area. Has scaling enabled
impractically complex designs? Can superior throughput be achieved with
architectural simplicity? Is microarchitecture out of ideas? Where will added
performance come from? Does scaling reduce the need for good circuits?
Are there fundamental barriers ahead?

Panelists:
Kazuo Yano, Hitachi Ltd., Tokyo, Japan
David Harris, Mudd College, Claremont, CA
Ruby Lee, Princeton Univ. Princeton, NJ
Robert Montoye, IBM, Austin, TX
Yale Patt, Univ. of Texas, Austin, TX
David Patterson, UC Berkeley, CA

E4 How Will Future Portable Systems Store and Access Data:

Disk, Semiconductor Memory, Emerging Technology, or via
the Internet?
(Salon 9)
Organizer: J. Miyamoto, Toshiba, Yokohama, Japan/ T. Kawahara,
Hitachi, Tokyo, Japan
Moderator: Gregory Atwood, Intel Corporation, Santa Clara, CA

What technology will dominate in replacing disk-based mass-storage

media - flash, ferro, mag-ram, etc? Or will the market for portable mass
storage diminish as data and/or software become easily accessible via
high-speed internet?

Panelists:
Carlos Paz de Araujo, Symetrix, Colorado Springs, CO
Boaz Eitan, Saifun Semiconductors, Netanya, Israel
Saied Tehrani, Motorola, Tempe, Arizona
Koji Sakui, Toshiba Corporation,Yokohama, Japan
Albert Fazio, Intel Corporation, Santa Clara, CA
David Foote, IBM, San Jose, CA
Tatsuro Takahashi, Kyoto University, Kyoto, Japan

17
 SESSION 7 SALON 1-6

TD: ADVANCED TECHNOLOGIES

Chair: Bill Martino, Motorola, Austin, TX

Associate Chair: Scott Willingham, Silicon Laboratories, Austin, TX

7.1 Genetic Applets: Biological Integrated Circuits for Cellular

Control
8:30 AM
T. Gardner
Cellicon Biotechnologies, Jamaica Plain, MA

Technological advances in the biological sciences, coupled with increasing

technical and economic challenges for silicon-based computing, generate
interest in biocomputing. A genetic flip-flop and a genetic clock, recently
implemented bacterial cells, may form the basic elements of a biochemical
integrated circuit that operates in a living cell.

7.2 The Design and Measurement of Molecular Electronic

Switches and Memories
9:00 AM
M. Reed1, J. Chen1, D. Price2, A. Rawlett2, J. Tour2, W. Wang1
1
Yale University, New Haven, CT
2
Rice University, Houston, TX

Molecular-scale devices have recently become possible with self-assembly

techniques. Examples of a number of simple molecular devices and circuits
include a negative-resistance device that exhibits peak-to-valley ratios
exceeding 1000:1 and a molecular memory cell with refresh times
exceeding 10 minutes.

7.3 Strained Si Surface Channel MOSFETS for High-

Performance CMOS Technology
9:30 AM
K. Rim
IBM T.J. Watson Research Center, Yorktown Heights, NY

Biaxial tension enhances in-plane transport of both electrons and holes in

silicon, and can improve the current drive of CMOS devices independent of
geometric scaling and electrostatic design. Device performance
enhancements and issues to be addressed before the realization of
strained Si CMOS technology are discussed.

BREAK 10:00 AM

18
 Tuesday, February 6th 8:30 AM

7.4 FinFET - A Quasi-Planar Double-Gate MOSFET

10:15 AM
S. Tang, L. Chang, N. Lindert, Y. Choi, W. Lee, X. Huang, V. Subramanian,
J. Bokor, T. King, C. Hu
University of California, Berkeley, CA

The quasi-planar FinFET structure has device characteristics similar to

those of the conventional MOSFET. Inserting FinFET into CMOS
technology requires no change in circuit architecture or layout/design tools,
providing a smooth transition to post-planar CMOS technology. 2D mixed-
mode simulations show FinFET circuit performance exceeds that of
advanced single-gate MOSFETs.

7.5 Ultra-Miniature, High-Q Filters and Duplexers using FBAR

Technology
10:45 AM
R. Ruby, P. Bradley, J. Larson, Y. Oshmyansky, D. Figueredo
Agilent Technologies, Newark, CA

An ultra-miniature PCS duplexer uses thin-film bulk acoustic resonator

technology. FBAR resonators are made using aluminum nitride for
piezoelectric material and silicon as substrate. It has better than -52dB
rejection of the Rx filter in the Tx band and pass-band insertion losses are
on the order of 2dB (Tx) and 3dB (Rx). Performance is comparable to that
of much larger ceramic duplexers.

7.6 A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM

11:15 AM
P. Naji, M. Durlam, S. Tehrani, J. Calder, M. Deherrera
Motorola, Tempe, AZ

A 256kb nonvolatile magnetoresistive RAM (MRAM) is based on a memory

cell defined by a single transistor (1T) and a single magnetic tunnel
junction (MTJ) with read and write cycles <50ns. The memory organization
is 16kx16. Measured read power consumption is 24mW at 3V and 20MHz.

CONCLUSION 11:45 AM

19
 SESSION 8 SALON 7

NYQUIST ADCs

Chair: Paul Hurst, UC Davis, Davis, CA

Associate Chair: Akira Matsuzawa, Matsushita, Osaka, Japan

8.1 A 6b 1.3GSample/s A/D Converter in 0.35µm CMOS

8:30 AM
M. Choi, A. Abidi
University of California Los Angeles, Los Angeles, CA

Using array averaging and a wideband track-and-hold, a 6b flash ADC

achieves better than 5.5 effective bits for input frequencies to 600MHz at
1GSample/s, and 5 effective bits for 650MHz input at 1.3GSample/s. It
consumes 500mW from 3.3V and occupies 0.8mm2 in 0.35µm CMOS.

8.2 A 6b 1.1GSample/s CMOS A/D Converter

9:00 AM
G. Geelen
Philips Semiconductors, Eindhoven, Netherlands

A 6b flash ADC incorporating an averaging/interpolating technique

achieves 1.1GSample/s in 0.35µm 3.3V CMOS. Measured ENOB is >5b
up to 450MHz input at 900MSample/s. Chip area is 0.35 mm2 and power
consumption is 300mW.

8.3 A 1.8V 10b 100MSample/s CMOS Pipelined ADC

9:30 AM
Y. Park, F. Tsay, S. Karthikeyan, E. Bartolome
Texas Instruments, Dallas, TX

A 100MHz ADC for low-power applications uses a 0.18µm digital CMOS

process. The design achieves 9.4 ENOB for a 50MHz input at full sampling
rate, and consumes a total of 180mW with 2.5mm2 core in a single 1.8V
power supply.

BREAK 10:00 AM

8.4 A 2.5V 12b 54MSample/s 0.25µm CMOS ADC in 1mm2

10:15 AM
H. van der Ploeg, G. Hoogzaad, H. Termeer, M. Vertregt, R. Roovers
Philips Research Labs., Eindhoven, Netherlands

Background digital offset extraction and analog compensation remove

offset of the critical analog components. The calibrated two-step ADC
achieves -70dB THD in the Nyquist band with a 2.5V supply. The ADC in
0.25µm CMOS measures 1.0mm2 and dissipates 295mW.

20
 Tuesday, February 6th 8:30 AM

8.5 A 3V 14b 75MSample/s CMOS ADC wtih 85dB SFDR at

Nyquist
10:45 AM
D. Kelly, W. Yang, I. Mehr, M. Sayuk, L. Singer
Analog Devices Inc., Wilmington, MA

A 14b multi-bit pipeline ADC achieves 0.6LSB DNL and 2LSB INL without
calibration. Typical SNR is 73dB, while SFDR is >85dB for input frequency
up to Nyquist. The 7.8mm2 ADC in 0.35µm double-poly triple-metal
process operates with a 2.7V to 3.6V power supply, and consumes 340mW
at 3V.

8.6 A 14b 40MSample/s Pipelined ADC with DFCA

11:15 AM
P. Yu, S. Shehata, A. Joharapurkar, P. Chugh, A. Bugeja, X. Du, S. Kwak,
Y. Papantonopoulos, T. Kuyel
Texas Instruments, Dallas, TX

A DAC and feedback capacitor averaging (DFCA) used in a pipelined ADC

achieves 84dB SFDR and 74db SNR. External mismatch noise
cancellation digitally improves SNR. Excluding output drivers, the 0.6µm
double-poly BiCMOS ADC dissipates 860mW from 3.3V supply.

CONCLUSION 11:45 AM

21
 SESSION 9 SALON 8

INTEGRATED MULTIMEDIA PROCESSORS

Chair: Ivo Bolsens, IMEC, Leuven, Belgium

Associate Chair: Yukihito Oowaki, Toshiba, Kanagawa, Japan

9.1 A 90mW MPEG4 Video Codec LSI with the Capability for
Core Profile
8:30 AM
T. Hashimoto1, S. Kuromaru1, M. Matsuo1, H. Nakajima1, Y. Kohashi1, K.
Ishida , T. Mori-iwa , M. Ohashi , K. Hashimoto , T. Yonezawa1, M.
1 1 1 1

Hamada1, T. Nakamura1, M. Toujima1, Y. Sugisawa1, T. Kondo1, H.

Otsuki1, M. Arita1, H. Fujimoto1, H. Toida1, H. Ito2
1
Matsushita Electric Industrial Co., Fukuoka, Japan
2
Matsushita Communication Industrial Co., Ltd., Yokohama, Japan

A single-chip MPEG4 video codec LSI with 20Mb embedded DRAM

performs a QCIF 15Hz H.263 codec, a Simple at L1 codec, and Core at L1
decoding. It consumes 90mW at 54MHz. This chip integrates a
programmable DSP, 8 dedicated hardware engines, and interface units on
a 75.68mm2 die using 0.18µm 1.8V quad-metal CMOS technology.

9.2 A 80/20MHz 160mW Multimedia Processor integrated with

Embedded DRAM, MPEG4 Accelerator, and 3D Rendering
Engine for Mobile Applications
9:00 AM
C. Yoon, R. Woo, J. Kook, S. Lee, K. Lee, Y. Bae, I. Park, H. Yoo
KAIST, Taejon, Korea

A 84mm2 160mW programmable processor in 0.18µm EML technology

consists of 32b RISC with MAC, 20MHz motion compensation accelerator
for MPEG-4 at SP, 3D rendering engine with 2.2Mpolygon/s at 20MHz, and
7.125Mb embedded DRAM with single bitline writing scheme.

9.3 One Chip 15frame/s Mega-Pixel Real-time Image Processor

9:30 AM
H. Yamauchi, S. Okada, T. Watanabe, S. Okada, Y. Matsuda, A.
Kobayashi, I. Ogura, Y. Harada
SANYO Electric Co., Ltd., Gifu, Japan

A one-chip 15frame/s mega-pixel real time image processor. for mobile

multimedia applications is presented. It contains mega-pixel CCD signal
processing, a motion-JPEG/MPEG2 image compression/decompression
engine, a RISC-CPU, an NTSC encoder, a SDRAM controller and
peripheral interfaces.

BREAK 10:00 AM

22
 Tuesday, February 6th 8:30 AM

9.4 A 250MHz Single-Chip Multiprocessor for A/V Signal

Processing
10:15 AM
T. Koyama1, E. Iwata1, H. Yoshikawa1, H. Hanaki1, K. Hasegawa1, M.
Aoki1, M. Yasue1, T. Schrobenhauser2, M. Aikawa1, I. Kumata1, H.
Koyanagi1
1
Sony Corporation, Tokyo, Japan
2
Sony US Research Laboratories, San Jose, CA

A 250MHz single-chip multiprocessor integrates four CPUs with multimedia

extended instructions in 0.25µm CMOS and consumes 2.4W at 2.5V. This
chip exploits both coarse- and fine-grained parallelism in A/V signal
processing and implements various codec standards such as multi-channel
MPEG2 (MP at ML) video decoding.

9.5 A 4GOPS 3-Way VLIW Image Recognition Processor-Based

on a Configurable Media-Processor
10:45 AM
Y. Kondo, T. Miyamori, T. Kitazawa, S. Inoue, H. Takano, I. Katayama, K.
Yahagi, A. Ooue, T. Tamai, K. Kohno, Y. Asao, H. Fujimura, H. Uetani, Y.
Inoue, S. Asano, Y. Miyamoto, A. Yamaga, Y. Masubuchi, T. Furuyama
Toshiba Co., Kawasaki, Japan

A 4GOPS 3-way VLIW image-recognition processor for an automobile

system is based on a configurable media-processor which enables design-
time configuration to optimize for a specific application. It uses a 0.25µm
CMOS process with a standard-cell design method.

9.6 A 150MHz Graphics Rendering Processor with 256Mb

Embedded DRAM
11:15 AM
A. Khan1, H. Magoshi2, M. Furuhashi2, J. Fujita3, M. Imai3, Y. Kurose4, T.
Matsumoto4, M. Sato4, K. Sato4, Y. Yamashita4, K. Kwan1, D. Le1, J. Yu1, S.
Yang1, K. Chow1, J. Li1, M. Li1, T. Nguyen1, J. Shen1, A. Tsou1, K.
Yoshida1, H. Zhao1
1
Altius Solutions, Inc., Santa Clara, CA
2
Sony Computer Entertainment Inc., Tokyo, Japan
3
Sony Kihara Research Center Inc., Tokyo, Japan
4
Sony Corporation, Semiconductor Network Company, Inc., Tokyo, Japan

A 150MHz graphics rendering processor with an integrated 256Mb

embedded DRAM, delivers a rendering rate of 75M polygons/s. 287.5 M
transistors are integrated on a 21.3x21.7 sq. mm. die in a 0.18µm 6-level-
metal CMOS process. Several design methodologies are used.

CONCLUSION 11:45 AM

23
 SESSION 10 SALON 9

WIRELESS BUILDING BLOCKS I

Chair: Charles Chien, Rockwell Science Center, Thousand Oaks, CA

Associate Chair: Paul Davis, Bell Labs, Lucent Technologies,
Reading, PA

10.1 A 1.5W Class-F RF Power Amplifier in 0.2µm CMOS

Technology
8:30 AM
T. Kuo1, B. Lusignan2
1
Philips Semiconductors, Milpitas, CA
2
Stanford University, Stanford, CA

Design considerations for deep-sub-micron RF CMOS power amplifier

emphasize high knee voltage design and CMOS breakdown. A square-
wave driver takes advantage of CMOS. In 0.2µm CMOS, the 1x2mm2 PA
delivers 1.5W output at 900MHz with 43% PAE from a 3V supply.

10.2 A CMOS RF Power Amplifier with Parallel Amplification for

Efficient Power Control
9:00 AM

A. Shirvani1, D. Su2, B. Wooley1

1
Stanford University, Stanford, CA
2
Atheros Communications

A 0.25µm CMOS RF power amplifier uses parallel amplification to provide

an output power adjustment range of 7mW to 300mW. The 2.37mm2
amplifier achieves 49% maximum power-added-efficiency (PAE) and
maintains a PAE >43% over 70% of the power range.

10.3 A 1W 0.35µm CMOS Power Amplifier for GSM-1800 with 45%

PAE
9:15 AM
C. Fallesen, P. Asbeck
Nokia Denmark A/S, Copenhagen, Denmark

A highly-integrated power amplifier in 0.35µm CMOS occupies 1.9mm2

and features class AB operation with 31.2dBm output power at 1730MHz,
and 45% maximum power added efficiency.

24
 Tuesday, February 6th 8:30 AM

10.4 A 1.75GHz Highly-Integrated Narrow-Band CMOS

Transmitter with Harmonic-Rejection Mixers
9:30 AM
J. Weldon1, J. Rudell1, L. Lin2, R. Narayanaswami1, M. Otsuka3, S.
Dedieu4, L. Tee1, K. Tsai1, C. Lee1, P. Gray1
1
University of California, Berkeley, CA
2
Broadcom Corporation
3
Hitachi, Ltd., Tokyo, Japan
4
ST Microelectronics

A 1.75GHz transmitter with harmonic and double image reject mixer

integrates the full signal path from the DAC to the RF output with two
frequency synthesizers in a 0.35µm double-poly five-metal CMOS process.
The IC consumes 151mA from a 3V supply and achieves 1.3o rms phase
error. Active area is 3x9.9mm2

BREAK 10:00 AM

10.5 A +18dBm IIP3 LNA in 0.35µm CMOS

10:15 AM
Y. Ding, R. Harjani
University of Minnesota, Minneapolis, MN

A feedforward linearization technique for RF CMOS LNAs makes feasible

up to 40dB output linearity improvement in current CMOS processes. A
high-linearity LNA with +18dBm IIP3 in a 0.35µm CMOS process shows
little impact on power, noise, and gain.

10.6 A Wideband 1.3GHz PLL for Transmit Remodulation

Supression
10:45 AM
F. Martin, R. Alford, J. Marks, G. Raven, J. Rollman
Motorola, Inc., Plantation, FL

A 1.3GHz 0.5µm BiCMOS offset PLL realizes -132dBc/Hz in-band phase

noise while reducing re-radiated transmission by 58dB. The circuit
operates without an offset signal. Elements include digital phase detector
with steering operating to 1.3GHz and digital frequency divider with
programmable modulus from 1 to 1.5 in steps of .03125. current is 10mA
from 2.7V. Die is 1.2mm2

CONCLUSION 11:15 AM

25
 SESSION 11 SALON 10-15

SRAM

Chair: B. P. Wong, Sun Microsystems, Palo Alto, CA

Associate Chair: Junichi Miyamoto, Toshiba Corp., Yokohama, Japan

11.1 Universal-Vdd 0.65-2.0V 32kB Cache using Voltage-Adapted

Timing-Generation Scheme and a Lithographically-
Symmetrical Cell
8:30 AM
K. Osada , J. Shin2, M. Khan2, Y. Liou2, K. Wang2, K. Shoji1, K. Kuroda1, S.
1

Ikeda1, K. Ishibashi1
1
Hitachi, Ltd., Tokyo, Japan
2
Hitachi Semiconductor America Inc., San Jose, CA

This 32kB cache design operates from 120MHz at 1.7mW and 0.65V to
1.04GHz at 530mW and 2.0V with a single internal supply using 0.18µm
CMOS technology. The wide voltage operating range is achieved using a
voltage-adapted timing-generation scheme with plural dummy cells and a
lithographically-symmetric cell (LS-cell).

11.2 An Architecture for Compact Associative Memories with

deca-ns Nearest-Match Capability up to Large Distances
9:00 AM

H. Mattausch1, T. Gyohten1, Y. Soda1, T. Koide2

1
Hiroshima University, Hiroshima, Japan
2
University of Tokyo, Tokyo, Japan

Associative-memory architecture for Hamming-distance search, compact

implementation, and short nearest-matches times up to large distances are
proposed. The main ideas are fast analog word comparison and self-
adaptive winner-line-up amplification. An implementation in a 0.6µm 2-poly
3-metal CMOS technology with 32 rows and 128 columns verifies the key
concepts. Search time is <38ns.

11.3 SRAM Current-Sense Amplifier with Fully-Compensated Bit

Line Multiplexer
9:30 AM
B. Wicht1, D. Schmitt-Landsiedel1, S. Paul2, A. Sanders2
1
Technical University of Munich, Munich, Germany
2
Infineon Technologies

A current-sense amplifier that fully compensates the bit line multiplexer

based on an improved feedback structure is implemented in a 512x24b
1.8V SRAM macro in 0.18µm CMOS. 0.5ns reduction of read access time
is measured with 0.4% additional area.

BREAK 10:00 AM

26
 Tuesday, February 6th 8:30 AM

11.4 Abnormal Leakage Suppression (ALS) Scheme for Low-

Standby-Current SRAMs
10:15 AM
K. Kanda1, D. H. Nguyen2, H. Kawaguchi1, T. Sakurai1
1
University of Tokyo, Tokyo, Japan
2
Toshiba, Kanagawa, Japan

Abnormal leakage suppression (ALS) repairs standby current errors in

SRAMs. By introducing leakage sensors, shift registers and fuses, ALS
senses 1µA abnormal leakage, isolates the memory cell from VDD lines
and thus suppresses abnormal leakage current. A 64kb test SRAM
demonstrates effectiveness. Area overhead is 7%.

11.5 A 900MHz 2.25MB Cache with On-Chip CPU - Now In Cu SOI

10:45 AM
J. Hill, J. Lachman
Hewlett Packard, Fort Collins, CO

The 500MHz 1.5MB cache with 50% increased bit count is ported from a
0.25µm bulk technology to a 0.18µm SOI process with local interconnect.
The SOI technology used presented significant design challenges to match
the 80% frequency increase expected for the CPU.

CONCLUSION 11:15 AM

27
 SESSION 12 SALON 1-6

SIGNAL PROCESSING FOR STORAGE AND CODING

Chair: Narendra Rao, Ikanos Communications, Fremont, CA

Associate Chair: Engel Roza, Philips Research Labs, Eindhoven, The
Netherlands

12.1 Power-Efficient Application-Specific VLIW Processor for

Turbo Decoding
1:30 PM
M. Bekooij, J. Dielissen, F. Harmsze, S. Sawitzki, J. Huisken, A. van der
Werf, J. van Meerbergen
Philips, Eindhoven, Netherlands

A method permits coprocessors to be embedded inside a programmable

VLIW processor. Synchronization of the coprocessors and the VLIW
processor is determined at compile-time by the VLIW scheduler. The
implementation of a power-efficient turbo decoder demonstrates
effectiveness of this method.

12.2 A Mixed-Signal 0.18µm CMOS SOC for DVD Systems with

432MSample/s PRML Read Channel and 16Mb Embedded
DRAM.
2:00 PM
S. Gotoh, T. Takahashi, K. Irie, K. Ohshima, N. Mimura, K. Aida, T. Maeda,
T. Yamamoto, K. Sushihara, Y. Okamoto, Y. Tai, M. Usui, T. Nakajima, T.
Ochi, K. Komichi, A. Matsuzawa
Matsushita Electric Industrial Co., LTD., Osaka, Japan

A single-chip CMOS mixed-signal LSI for DVD systems contains 32b RISC
CPU, formatter, servo DSP, 16Mb DRAM, an ECC, ATA I/F, and digital
read channel with 7b flash ADC. The chip in 0.18µm embedded DRAM
process contains 24M transistors in a 144mm2 die. The data rate is
432MSample/s with 1.2W power consumption.

12.3 A 700Mb/s BiCMOS Read Channel Integrated Circuit

2:30 PM
S. Altekar1, H. Chan1, J. Chern1, L. Fang1, H. Gao1, R. Gee1, P. Ha1, K.
Hsieh , Y. Hsieh , D. Hsu , X. Huang , H. Kim , H. Kimura , P. Lai1, I.
1 1 1 1 1 1

Mohammed1, L. Moser1, S. Shih1, M. Sugawara2, Y. Tamura2, H. Thapar1,

Y. Wang1, D. Xu1, J. Yang1, A. Yeung1
1
LSI Logic, San Jose, CA
2
NEC Electronics, Santa Clara, CA

A read channel IC achieves >1.5dB SNR improvement over a 32/34 rate

EPRML read channel at 2.8 user bit density. The 0.18µm BiCMOS chip
operates up to 700Mb/s with 1.8W read mode power using 3.3V analog
and 1.8V digital power supplies. The die area is 9.64mm2.

BREAK 3:00 PM

28
 Tuesday, February 6th 1:30 PM

12.4 A 300MHz Mixed-Signal FDTS/DFE Disk Read Channel in

0.6µm CMOS
3:15 PM
D. Wei, D. Sun, A. Abidi
UCLA, Los Angeles, CA

A 300MHz mostly-analog DFE detector IC performs clock recovery and

depth-of-two tree-search detection on equalized EPR4 waveforms. With
MTR-coding, the detector is an analog DFE with digital error-correction
logic to boost performance. At user density 3.0, performance exceeds that
of an EPR4/VA channel. It consumes 530mW from 3V, and occupies
3.34mm2 active area.

12.5 A 1Gb/s Read/Write-Preamplifier for Hard-Disk-Drive

Applications
3:45 PM
H. Veenstra1, J. Mulder2, L. Le3, G. Grillo1
1
Philips, Eindhoven, The Netherlands
2
Broadcom, Bunnik, The Netherlands
3
Philips, Coen, France

The 6-channel read/write preamplifier IC supports data rates up to 1Gb/s.

The bandwidth of the reader exceeds 630MHz. The input-referred noise is
< 0.6nV/¥Hz. The rise time of the writer is 0.3ns at 5mA output current.
Impedance matching is employed at all high-frequency in/outputs. This IC
uses 0.6µm CBiCMOS technology and occupies 16 mm2.

12.6 A 2.3GSample/s 10-tap Digital FIR Filter for Magnetic

Recording Read Channels
4:15 PM
S. Rylov1, A. Rylyakov1, J. Tierno1, M. Immediato1, M. Beakes1, M. Kapur1,
2 1
P. Ampadu , D. Pearson
1
IBM, Yorktown Heights, 2Cornell University

A 6b 10tap 2.3GSample/s distributed-arithmetic digital FIR filter uses

footless dynamic logic with delayed reset for precharge. The 0.5mm2 filter,
fabricated in 0.18µm CMOS, is operational from 1V to 2V power supply. At
2.3GSample/s, the power is 680mW, and at 1GSample/s the power is
120mW.

12.7 A 16b Accurate CMOS Laser Driver IC with 500mA Output

Current and 1.5ns Rise Time
4:30 PM
J. van den Homberg1, A. Immink1, J. McCormack2, A. Slenter3, J. Noot2, M.
Tryzna4, H. Verhoeven4
1
Philips Research, Eindhoven, The Netherlands
2
Philips Optical Storage, Eindhoven, The Netherlands
3
Philips Semiconductors, Eindhoven, The Netherlands
4
Philips Consumer Electronics, Eindoven, The Netherlands

A CMOS laser driver IC combines two 500MHz 250mA driver DACs with
on-board digital write strategy generator and PLL to achieve 2ns timing
resolution. An embedded laser power control algorithm with analog monitor
diode pre-processing compensates for laser temperature variations and
aging.

CONCLUSION 4:45 PM

29
 SESSION 13 SALON 7

WIRELESS LAN

Chair: Trudy Stetzler, TI, Stafford, TX

Associate Chair: Thomas Lee, Stanford University, Stanford, CA

13.1 A Fully-Integrated Single-Chip SOC for Bluetooth

1:30 PM
F. Op 't Eynde1, J. Schmit1, V. Charlier1, R. Alexandre1, C. Sturman2, K.
Coffin1, B. Mollekens1, J. Craninckx1, S. Terrijn1, A. Monterastelli1, S.
Beerens1, P. Goetschalckx1, D. Joos1, S. Guncer3, A. Pontioglu3
1
Alcatel Microelectronics, Zaventem, Belgium
2
TTPCom, Melbourne, UK
3
Alcatel Microelectronics Teletas, Istanbul, Turkey

A 0.25µm CMOS IC contains all analog and digital electronics required for
a point-to-multipoint Bluetooth node. The circuit includes RF front-end and
digital baseband processor, microprocessor and flash memory with
software stack. The 41mm2 die has 15dB noise figure and 2dBm maximum
transmitter output, and consumes 125mW at 2.5V during receive.

13.2 A Fully-Integrated CMOS RFIC for Bluetooth Applications

2:00 PM
A. Ajjikuttira1, C. Leung1, E. Khoo1, M. Choke1, R. Singh1, T. Teo2, B.
Cheong2, J. See2, H. Yap2, P. Leong2, C. Law2, H. Nakamura2, A. Yoshida3,
Y. Yoshida3, A. Tamura3, M. Itoh3
1
Institute of Microelectronics, Singapore
2
Oki Techno Centre, Singapore
3
Oki Electric Industry, Tokyo, Japan

A 4.5x4mm2 single-chip Bluetooth RF transceiver in a 0.35µm standard

CMOS technology with minimal external components operates from a 3V
supply. The low-IF receiver achieves -77dBm sensitivity for 0.1%BER and
-17dBm IIP3. The direct up-conversion transmitter has 0dBm nominal
output power.

13.3 A 2.4GHz CMOS Transceiver for Bluetooth

2:30 PM
H. Darabi, S. Khorram, E. Chien, M. Pan, S. Wu, S. Moloudi, J. Leete, J.
Rael, M. Syed, R. Lee, B. Ibrahim, M. Rofougaran, A. Rofougaran
Broadcom Corporation, El Segundo, CA

A fully-integrated CMOS transceiver tuned to 2.4GHz consumes 46mA in

receive mode and 47mA in transmit mode from a 2.7V supply. The receiver
has -80dBm sensitivity at 0.1% BER, and -7dBm IIP3. The transmitter
delivers a GFSK modulated spectrum at 5dBm output power.

BREAK 3:00 PM

30
 Tuesday, February 6th 1:30 PM

13.4 A 22mW Bluetooth Transceiver with Direct RF Modulation

and On-chip IF Filters
3:15 PM
N. Filiol1, N. Birkett1, J. Cherry1, F. Balteanu1, C. Cojocaru1, A. Namdar1, T.
Pamir1, K. Sheikh1, G. Glandon1, D. Payer1, A. Swaminathan1, R. Forbes1,
T. Riley2, S. Alinoor1, E. Macrobbie1, M. Cloutier1, S. Pipilos3, T. Vareles3
1
Conexant Systems Inc., Nepean, ON, Canada
2
University of Oulu, Oulu, Finland
3
Theta Microelectronics, Athens, Greece

A +2dBm Bluetooth transceiver in 0.5µm SiGe BiCMOS consumes 22mW

at 2V. The transmitter uses a ǻȈ synthesizer and on-chip VCO to directly
modulate the carrier and settles to 30ppm within 180µs. The single low-IF
I/Q receiver uses a 7th-order complex IF filter with tuning, distributed AGC
and digital PLL demodulation.

13.5 A Zero-IF Single-Chip Transceiver for up to 22Mb/s QPSK

IEEE802.11b Wireless LAN
3:45 PM
P. Stroet, R. Mohindra, S. Hahn, A. Schuur, E. Riou
Philips Semiconductors, Sunnyvale, CA

A zero-IF 2.4GHz 22Mb/s IEEE802.11b transceiver including LNA, mixers,

on-chip channel filtering, fully-integrated VCO, AGC, RSSI and synthesizer
is realized in a 0.5µm BiCMOS process. The receiver has 5.4dB NF, -
4dBm IIP3, and dissipates <300mW. It delivers either 0 or 5dBm, and
consumes <370mW at 3V.

13.6 A Single-Chip 2.4GHz RF Transceiver LSI with a Wide-Range

FV Conversion Demodulator
4:15 PM
H. Komurasaki1, H. Sato1, M. Ono1, T. Ebana2, H. Takeda2, K. Takahashi2,
Y. Hayashi1, T. Iga1, K. Hasegawa1, T. Miki1
1
Mitsubishi Electric Corp., Itami, Japan
2
Mitsubishi Electric Engineering Company Ltd., Sagamihara, Japan

A single-chip RF transceiver LSI for 2.4GHz-band GFSK applications uses

a 0.5µm BiCMOS which provides 23GHz fT. The transceiver consumes
34.4mA in TX mode (PA, PLL) and 44.0mA in RX mode (LNA, IR mixer,
filters, limiter, RSSI, demodulator, PLL). It has a linear FV conversion
demodulator with wide input-frequency range.

13.7 A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver

4:45 PM
H. Samavati, H. Rategh, T. Lee
Stanford University, Center for Integrated Systems, Stanford, CA

A fully-integrated 5GHz wireless LAN receiver in 0.24µm CMOS consumes

59mW and occupies 4mm2 die space. The overall image rejection is 53dB
and the noise figure is 7.2dB. IIP3 is -7dBm and LO leakage to the RF port
is -87dBm. The synthesized LO phase noise is -134dBc/Hz at 22MHz and
all spurs are below -70dBc.

CONCLUSION 5:15 PM

31
 SESSION 14 SALON 8

GIGABIT OPTICAL COMMUNICATIONS II

Chair: MaryJo Nettles, Mobilian, San Diego, CA

Associate Chair: Tyson Tuttle, Silicon Labs, Austin, TX

14.1 A 0.6 - 2.5GBaud CMOS Tracked 3x Oversampling

Transceiver with Dead-Zone Phase Detection for Robust
Clock/Data Recovery
1:30 PM
Y. Moon , D. Jeong1, G. Ahn2
1
1
Seoul National University, Seoul, Korea
2
Silicon Image Inc., Sunnyvale, CA

Tracked 3x oversampling with dead-zone phase detection is used in a

receiver for robust clock/data recovery in the presence of excessive jitter
and ISI. The transceiver, in 0.25µm CMOS, operates at 2.5GBaud over
10m 150ȍ STP cable and at 1.25GBaud over 25m with <10-13 BER.

14.2 A 2.75Gb/s CMOS Clock-Recovery Circuit with Broad

Capture Range
2:00 PM
S. Anand, B. Razavi
UCLA, Los Angeles, CA

A dual-loop PLL clock-recovery circuit uses a digital search algorithm to

increase capture range with no external reference. A 0.25µm CMOS circuit
has 350MHz capture range around 2.7GHz, and 5.1ps rms jitter consuming
50mW from 2.7V.

14.3 Si Bipolar Laser Driver/Receiver Chip Set for 4-Channel

5Gb/s Parallel Optical Interconnection
2:30 PM
T. Nagahori, K. Miyoshi, Y. Aizawa, Y. Kusachi, Y. Nukada, N. Kami
NEC, Kawasaki, Japan

A chip set of a 4-channel 5Gb/s laser driver and a receiver uses an electo-
optical mixed design with an array of laser diodes. It realizes a parallel
optical transceiver module with 20Gb/s throughput. Optical waveform is not
required. Power consumption is 1.3W.

BREAK 3:00 PM

14.4 A 1V 1mW CMOS Front-End with On-chip Dynamic Gate

Biasing for a 75Mb/s Optical Receiver
3:15 AM
K. Phang, D. Johns
Univ. of Toronto, Toronto, Canada

An optical receiver front-end consisting of a transimpedance amplifier and

two post amplifiers consumes 1mW from a 1V supply and provides 210kȍ
transimpedance gain at 75Mb/s. A test chip in standard 0.35µm CMOS
without low-threshold devices incorporates a charge pump for the biasing
and tuning of MOS resistors.

32
 Tuesday, February 6th 1:30 PM

14.5 A Redundant Multi-Valued Logic for 10Gb/s CMOS

Demultiplexer IC
3:30 PM
A. Tanabe, Y. Nakahara, A. Furukawa, T. Mogami
NEC, Kanagawa, Japan

A redundant multi-valued logic is used in >1Gb/s communication IC

applications. Using this logic, a quadruple data rate demultiplexer (serial-
parallel converter) IC in 0.18µm CMOS achieves 10Gb/s operation with
1.3V supply and 38mW consumption.

14.6 A Chipset for Scalable QoS-Preserving Protocol-

Independent Packet Switch Fabrics
3:45 PM
F. Chiussi, U. Bakhru, A. Brizio, G. Gu, N. Idirene, K. Kazi, T. Li, J.
Leshchuk, P. Moran, D. Quinn, A. Reynolds, M. Syed, S. Shen, D.
Staunton, T. Wasilewski
Bell Labs, Lucent Technologies, Holmdel, NJ

The protocol independent switch fabric 128Gb/s provides per-flow quality

of service (QoS) in the next-generation Internet. The VLSI challenges stem
from the large number of QoS channels to be managed, the sophisticated
scheduling algorithm used, and the need to relax chip synchronization
requirements in systems.

14.7 A 28.5GB/s CMOS Non-Blocking Router for Terabit/s

Connectivity between Multiple Processors and Peripheral
I/O Nodes
4:15 PM
R. Nair, N. Borkar, C. Browning, G. Dermer, V. Erraguntla, V.
Govindarajulu, A. Pangal, J. Prijic, L. Rankin, E. Seligman, S. Vangal, H.
Wilson
Intel Corporation, Hillsboro, OR

A 28.5GB/s data router enables a terabits/s bandwidth network. The 6.6M

transistor 0.18µm 1.3V 15W CMOS LSI has three clocking domains that
synchronize data through four 1.06GB/s links, a 6-port crossbar, and five
point-to-point links of 4.75GB/s data throughput each. Test data rates are
up to 6.4Gb/s per wire.

14.8 40Gb/s ASIC Switch Design Using Low-Jitter Clock

Recovery
4:45 PM
V. Pathak1, M. Veghese2, S. Ching-Hao1, B. Vance 1, A. Bonelli1, J. Ribo1,
O. Bonte1, F. Bauduin1, I. Grant2, C. Kean2, P. Begin2, H. Mah2, S.
Devalapalli1, B. Roderer1, P. Smith1
1
Texas Instruments, Dallas, TX
2
Nortel Networks, Ottawa, Canada

A 32x32 switch ASIC has 40Gb/s aggregate throughput. The switch fabric
is realized in three stages using full-custom clock recovery and transmit
ports at 1.25Gb/s. 18 ASICs fabricated in 0.18µm CMOS technology and
packaged in 352-pin flip-chip BGA dissipate 160W.

CONCLUSION 5:15 PM

33
 SESSION 15 SALON 9

MICROPROCESSORS

Chair: John Maneatis, True Circuits, Inc., Los Altos, CA

Associate Chair: Glen Giacalone, C-Port Corp., North Andover, MA

15.1 A Scalable Performance 32b Microprocessor

1:30 PM
L. Clark, E. Hoffman, M. Schaecher, M. Biyani, D. Roberts, Y. Liao
Intel Corp., Chandler, AZ

A RISC microprocessor core in a six-layer metal 0.18µm CMOS process

implements the ARMTM V.5TE instruction set. The microprocessor core is
16.77mm2 and dissipates 450mW at 1.3V, 600MHz, scaling between
55mW, 0.7V and 200MHz, and 1.55W at 1.65V, 800MHz.

15.2 POWER4 Physical Design

2:00 PM
C. Anderson, J. Petrovich, J. Keaty, G. Nusbaum
IBM, Austin, TX

The 4th-generation POWER processor chip contains 170M transistors and

includes 2 microprocessor cores, shared L2, directory for an off-chip L3,
and all logic needed to interconnect multiple chips to form an SMP. It is
implemented in a 0.18µm SOI technology with 7 layers of Cu interconnect,
functions in systems at 1.1 GHz, and dissipates 115W at 1.5V.

15.3 A Process-Portable 64b Embedded Microprocessor with

Graphics Extension and a 3.6GB/s Interface
2:30 PM
Y. Ho, I. Bhasin, T. Chiu, P. Forssell, V. von Kaenel, J. Jiang, J. Kelley, D.
Matthews, Q. Nasir, K. Patel, V. Peng, V. Rajagopalan, J. Reaves, U.
Saha, G. Tien, K. Townley, M. Ukanwa, J. Werner
Mips Technologies Inc., Mountain View, CA

A custom yet process-portable dual-issue 64b embedded microprocessor

implements the MIPS64TM architecture with 3D graphics geometry
processing extensions and a 3.6GB/s interface. In a 0.18µm 6 layer metal
process, the 34 mm2 processor is expected to function up to 600MHz, and
dissipate 2W at 1.5V and 500MHz.

BREAK 3:00 PM

34
 Tuesday, February 6th 1:30 PM

15.4 First-Generation MAJC Dual Microprocessor

3:15 PM
A. Kowalczyk, V. Adler, C. Amir, F. Chiu, C. Chng, W. De Lange, S.
Dubler, Y. Ge, S. Ghosh, T. Hoang, R. Hu, B. Huang, S. Kant, Y. Kao, C.
Khieu, S. Kumar, C. Lau, L. Lee, A. Liebermensch, X. Liu, et al.
Sun Microsystems, Inc., Sunnyvale, CA

The MAJC 5200 is a dual 32b microprocessor system-on-a-chip, utilizing

0.22µm CMOS with all-Cu interconnect. Two CPUs, delivering 6GFLOPS
and 13GOPS at 500MHz, are tightly coupled through a shared, coherent,
4-way set associative 16kB data cache, and an on-chip 4GB/s switch.
Each CPU is a 4-issue VLIW engine.

15.5 A 1.1GHz First 64b Generation S/390 Microprocessor

3:45 PM
B. Curran
IBM, Poughkeepsie, NY

The first 64b S/390 microprocessor implemented in a 0.18µm, 7-level

copper interconnect bulk CMOS process, runs operating system and
applications at 1.1GHz. The frequency is achieved with interconnect width
and repeater optimization, selective use of low-Vt devices, tapered library
gates, and improved synthesis and circuit tuning algorithms.

15.6 A 1.2GHz Alpha Microprocessor with 44.8GB/s Chip Pin

Bandwidth
4:15 PM
A. Jain, et al.
Compaq Computer Corporation, Shrewsbury, MA

A 4th-generation Alpha microprocessor running at 1.2GHz delivers up to

44.8GB/s chip pin bandwidth and dissipates 125W at 1.5V. It contains a
1.75MB 2nd level write-back-cache, two memory controllers supporting 8
RambusTM channels running at 800Mb/s, four 6.4GB/s inter-processor
communication ports, and a separate IO port capable of 6.4GB/s. The chip
measures 21.1x18.8mm2 and contains 130M transistors.

15.7 Withdrawn
4:45 PM

CONCLUSION 4:45 PM

35
 SESSION 16 SALON 10-15

INTEGRATED MEMS AND DISPLAY DRIVERS

Chair: J. Judy, UCLA, Los Angeles, CA

Associate Chair: A. Akinwande, MIT, Cambridge, MA

16.1 A CMOS Multi-Parameter Biochemical Microsensor with

Temperature Control and Signal Interfacing
1:30 PM
E. Lauwers1, J. Suls1, G. Van der Plas1, E. Peeters1, W. Gumbrecht2, D.
3 3 1 1
Maes , F. Van Steenkiste , G. Gielen , W. Sansen
1
K. U. Leuven, Leuven, Belgium
2
Siemens AG
3
IMEC

A fully-integrated microsensor chip allows continuous monitoring of

concentrations of blood gases (pH, pO2, pCO2), ions, and biomolecules,
and a conductometric measurement. The chip monitors 7 different
chemical properties and includes temperature control and an EPROM. It
occupies 25.7mm2 in a standard 1.2µm CMOS process including chemical
sensor postprocessing.

16.2 A Single-Chip CMOS Resonant Beam Gas Sensor

2:00 PM
C. Hagleitner, D. Lange, O. Brand, A. Hierlemann, H. Baltes
ETH Zurich, Zurich, Switzerland

A micromachined resonant beam gas sensor for detection of organic

volatiles is monolithically integrated with thermal actuators, piezoresistive
read out, and circuitry for self-excitation and fabricated in standard CMOS
technology. Mass load due to analyte absorption in a sensitive coating
changes beam resonance frequency. The limit of detection is 1ppm for
toluene.

16.3 Integrated Hall Sensor Array Microsystem

2:30 PM
J. Frounchi1, M. Demierre1, Z. Randjelovic2, R. Popovic1
1
Swiss Federal Institute of Technology, Lausanne, Switzerland
2
EM Microelectronics-Marin

A CMOS microsystem consists of an array of miniature integrated Hall

sensors and dynamic offset cancellation interface electronics. It has
86V/Tesla magnetic sensitivity, 160µTesla magnetic offset field, and
0.8µTesla/¥Hz noise density while consuming 2.3mA from a single 5V
supply. It measures the earth magnetic field with 5% precision.

BREAK 3:00 PM

36
 Tuesday, February 6th 1:30 PM

16.4 A Capacitive Fingerprint Sensor with Low-Temperature

Poly-Si TFTs
3:15 PM
R. Hashido, A. Suzuki, A. Iwata, T. Ogawa, T. Okamoto, Y. Satoh, M.
Inoue
Mitsubishi Electric Corp., Amagasaki, Hyogo, Japan

A capacitive fingerprint sensor using low-temperature poly-Si TFTs

succeeds in fingerprint certification. The array area is 19.2x15mm2.
Resolution is 423dpi (60µm pitch) using a structure with only one transistor
and one sensor plate.

16.5 A CMOS Photosensor Array for 3D Imaging using Pulsed

Laser
3:45 PM
R. Jeremias1, W. Brockherde1, G. Doemens2, B. Hosticka1, L. Listl2, P.
Mengel2
1
Fraunhofer IMS Duisburg, Duisburg, Germany
2
Siemens AG

A 32x2 pixel optical time-of-flight range sensor in standard 0.5µm CMOS

acquires up to 20k 3D-images/s combines CDS, S&H, multiple double
short time integration, a high-speed synchronous shutter, and a phase
synchronizer enabling exposures <30ns with <5.2W/m2 NEP. The 42 mm2
chip dissipates 330mW.

16.6 A Versatile Micro-Power High-Voltage Flat Panel Display

Driver
4:15 AM
J. Doutreloigne, H. De Smet, A. Van Calster
University of Gent, Gent, Belgium

A 0.7µm CMOS I2Technology display-driver chip with 100V driving

capability and an internal power consumption of 1µW to 2µW per driver
output is presented. These features together with its multi-functionality
make this driver chip suited for a variety of flat-panel displays, especially in
battery-powered applications.

16.7 100frames/s CMOS Range Image Sensor

4:45 PM
V. Brajovic1, K. Mori2, N. Jankovic3
1
Carnegie Mellon University, Pittsburgh, PA
2
Fuji Electric Co., Ltd., Kawasaki, Japan
3
Faculty of Electronic Engineering, Nis, Yugoslavia

A row–parallel CMOS sensor for triangulation–based range imaging

includes embedded winner–take–all circuits for detecting location of the
brightest spot in each row. The brightest spot originates from a planar light
continuously sweeping across a scene. The sensor delivers more than 100
range maps per second.

CONCLUSION 5:15 PM

37
 DISCUSSION SESSIONS

E5 Embedded DRAM: Curiosity or Workhorse?

(Salon 1-6)
Organizer: Jeffrey Dreibelbis, IBM, Essex Junction, VT
Moderator: Don Stark, Rambus, Mountain View, CA

Are there real design advantages to using embedded DRAM? Are the
technology integration problems of DRAM into logic-based processes
solvable? Can embedded DRAM function in the noisy world? Is it possible
to yield small amounts of DRAM on a large ASIC Chip? Are test costs
containable? How?

Panelists:
Tohru Furuyama, Toshiba, Kawasaki, Japan
Dean Klein, Micron Technologies Inc., Boise, ID
Subramanian Iyer, IBM Microelect. Div., Hopewell Junction, NY
Wingyu Leung, Mosys Inc., Sunnyvale, CA
Sadish Soman, Axiowave Networks, Marlborough, MA
Clair Webb, Intel Corp., Hillsboro, OR

E6 Broadband Access - Who Will Win the Race: Copper, Fiber

or Wireless?
(Salon 7)
Organizer: Tyson Tuttle, Silicon Labs, Austin, TX
Moderator: Gitty Nasserbakht, Proxim, Sunnyvale, CA

Can copper-based technologies (xDSL, cable) continue to evolve to deliver

higher and higher data rates? Has the time finally arrived for fiber to be
a cost-effective solution and a major player in the broadband race to
the enterprise (and even to the home)? Does the ease of installation and
use favor wireless?

Panelists:
Henry Samueli, Broadcom Corp., Irvine, CA
John Cioffi, Stanford Univ., Stanford, CA
Mamoru Kitamura, NTT, Kanagawa, Japan
A. Paulraj, Gigabit Wireless, San Jose, CA
Leon Cloetens, Alcatel Microelectronics, Zaventem, Belgium
Gerry Pepenella, Silicon Laboratories, Austin, TX
Derek Schaefer, Freespace Communications, Palo Alto, CA

38
 DISCUSSION SESSIONS

E7 100cubed: Science or Fiction? Is It Possible to Design a

100mm2 System-on-Chip with 100M Transistors in 100
Days?
(Salon 8)
Organizer: Ivo Bolsens, IMEC, Leuven, Belgium
Moderator: Jan Rabaey, UC Berkeley, CA

In the post-PC era, systems-on-chip (SoC) are the engines of cheap,

energy-efficient consumer products. The primary design bottleneck is
diversity of design styles (embedded SW, analog, RF, passives, MEMS,
and packaging). The system-on-chip challenges the IC industry for a
workable design methodology. The latest "platform-based" design and "IP-
reuse" strategies are much easier to describe than execute. Is starting
design 2 years ahead the only key to timely introduction of SoC?

Panelists
Hugo De Man, IMEC , Leuven, Belgium
Andrea Cuomo, ST Microelectronics, Geneva, Switzerland
Harry Veendrick, Philips Semiconductor, Eindhoven, The
Netherlands
Aart De Geus, Synopsys, Mountain View, CA
Alberto Sangiovanni-Vincentelli, Cadence , Milpitas, CA
Mehdi Hatamanian, Broadcom, Irvine, CA

E8 Are Startups Killing Innovation?

Organizer: Venugopal Gopinathan, Broadcom, Irvine, CA

Moderator: David Johns, Univ. Toronto, Toronto, ON, Canada
(Salon 9)
Has there been a fundamental change in innovative research over the last
5 years? Due to large amounts of venture capital available, many
researchers have left large companies and universities to join start-ups.
Are these start-ups doing innovative research, or are they working on
short-term products to satisfy venture capitalists? Where will research be
done in the future if no one is left in universities or R&D labs?

Panelists:
Nav Sooch, Silicon Labs, Austin, TX
Bob Hewes , Texas Instruments, Dallas, TX
Bryan Ackland, Bell Labs, Holmdel, NJ
Masao Hotta, Hitachi, Gunma, Japan
Klaas Bult, Broadcom, Utrect, The Netherlands
Ron Rohrer, Carnegie Mellon Univ., Pittsburgh, PA

39
 TIMETABLE OF ISSCC 2001 SESSIONS

40 41
 SESSION 17 SALON 1-6

TD: 3D TECHNOLOGIES AND MEASUREMENT TECHNIQUES

Chair: K. Najafi, Univ. of Michigan, Ann Arbor, MI

Associate Chair: A. Kanuma, Toshiba Corp., Kawasaki, Japan

17.1 Three-Dimensional Integrated Circuits for Low-Power High-

Bandwidth Systems on a Chip
8:30 AM
J. Burns1, C. Keast1, C. Lewis2, A. Loomis1, L. McIlrath2, K. Warner1, P.
1
Wyatt
1
MIT Lincoln Laboratory, Lexington, MA
2
TREX Enterprises, Sommerville, MA

A 3D integration technology stacks two silicon circuit layers and connects

them through unrestricted placement of 6µm square vias up to 7.5µm
deep. A back-illuminated 64x64 active pixel sensor with fully-parallel A/D
conversion is reported.

17.2 Neuromorphic Vision Chip Fabricated Using Three-

Dimensional Integration Technology
9:00 AM
M. Koyanagi, Y. Nakagawa, Y. Yamada, K. Lee, T. Nakamura, Y. Yamada,
K. Inamura, K. Park, H. Kurino
Tohoku University, Sendai, Japan

A 3D micro-system mimics the human retina and visual cortex. The system
uses 2.5µm square, 30µm deep vias to connect a photodiode array layer to
a CMOS circuit layer below.

17.3 3-D Assembly Interposer Technology for Next-Generation

Integrated Systems
9:30 AM
K. Ohsawa, T. Iijima, S. Pierce, H. Odaira, M. Ohsawa, S. Hirade
North Corporation, Tokyo, Japan

An interposer structure and manufacturing technique provides ultra-thin

packages. The goal is a wiring layer characterized by one-fourth the
thickness and five times the wiring density of conventional methods. It
comprises a low-cost multi-layer copper wiring process, and enhanced
speed through formation of a low dielectric constant material.

BREAK 10:00 AM

42
 Wednesday, February 7th 8:30 AM

17.4 Millimeter-Wave Characteristics of SiGe Heterojunction

Bipolar Transistors and Monolithic Interconnects in Silicon
Technologies
10:15 AM
J. Long1, J. Zhang2, M. Jackson2
1
University of Toronto, Toronto, ON, Canada
2
University of British Columbia, Vancouver, BC, Canada

SiGe HBTs small-signal parameters are characterized to 150GHz using

electro-optic sampling combined with on-wafer test fixtures. 300GHz
measurement bandwidth is demonstrated for coplanar striplines in SiGe
technology, validating 3-D simulations. Performance of coplanar and
microstrip interconnects in SiGe and CMOS are compared up to 94GHz.

17.5 Backside Infrared Probing for Static Voltage Drop and

Dynamic Timing Measurements
10:45 AM
S. Rusu, S. Seidel, G. Woods, D. Grannes, H. Muljono, K. Petrosky
Intel Corp., Santa Clara, CA

Infrared emission intensity and spectra are characterized for n-channel

transistors from several process generations under both static bias and
switching conditions using a HgCdTe detector array in the 0.9-1.45µm
range. The infrared emission exponential dependence of voltage is used
for accurate, non-invasive supply voltage drop and dynamic timing
measurements in a microprocessor in 0.18µm technology.

17.6 Impact of Die-to-Die and Within-Die Parameter Fluctuations

on the Maximum Clock Frequency Distribution
11:15 AM
K. Bowman1, S. Duvall2, J. Meindl1
1
Georgia Institute of Technology, Atlanta, GA
2
Intel Corp., Santa Clara, CA

A model for the maximum clock frequency (FMAX) distribution is derived

and compared with wafer sort data for a microprocessor. Model predictions
agree closely with measured data and reveal that intra-die fluctuations
directly impact the FMAX mean. Inter-die fluctuations impact FMAX
variance.

17.7 Sea of Leads: A Disruptive Paradigm for a System-on-a-

Chip
11:30 AM
A. Naeemi, C. Patel, M. Bakir, P. Zarkesh-Ha, K. Martin, J. Meindl
Georgia Institute of Technology, Atlanta, GA

Sea of leads (SoL) uses wafer-level batch fabrication of ultra-high-density

(>104/cm2) x-y-z compliant input/output leads and packages. Wafer-level
DC/AC testing and burn-in to enhance performance, cost, size, weight, and
reliability are assessed.

CONCLUSION 11:45 AM

43
 SESSION 18 SALON 7

3G WIRELESS

Chair: Bill Camp, Jr., Ericsson Inc., Research Triangle Park, NC

Associate Chair: John Long, University of Toronto, Ontario, Canada

18.1 A 22mA 3.7dB NF Direct Conversion Receiver for 3G

WCDMA
8:30 AM
J. Jussila, J. Ryynänen, K. Kivekäs, L. Sumanen, A. Pärssinen, K. Halonen
Helsinki University of Technology, Espoo, Finland

A single-chip 2GHz direct-conversion receiver including on-chip A/D

converters achieving 3.7dB DSB NF and -16dBm IIP3 is targeted for third-
generation WCDMA applications. The 10.3 mm2 receiver IC is fabricated
with 0.35µm 45GHz fT SiGe BiCMOS technology and draws 22mA from a
2.7V supply.

18.2 A Fully-Integrated CMOS RF Front-End with On-Chip VCO

for WCDMA Applications
9:00 AM
K. Lim, C. Park, H. Ahn, J. Kim, B. Kim
Korea Advance Institute of Science and Technology, Taejon, Korea

A 0.35µm CMOS fully-integrated WCDMA RF front-end includes LNA,

mixer, programmable gain amplifier, and Ȉǻ modulated fractional-N
synthesizer with on-chip VCO. Measured phase noise of the on-chip VCO
is -134dBc/Hz at 1MHz offset. Sensitivity, DSB NF, IIP3, and maximum
gain of the RF receiver are -107.9dBm, 3.5dB, -16dBm, and 80dB,
respectively. Chip core area is 2mm2 and DC power is 52mW at 3V.

18.3 A 1V 12mW 2GHz Receiver with 49dB of Image Rejection in

CMOS/SIMOX
9:30 AM
M. Ugajin, J. Kodate, T. Tsukahara
NTT, Kanagawa, Japan

A 2GHz receiver consisting of LNA, quadrature mixer, and on-chip

polyphase filters achieves 49dB image rejection. The mixer employs an
LC-tuned folded structure with a common RF input for I and Q channels,
and suppresses phase errors in LO signals. The receiver IC is 2.2x3.8mm2
and is fabricated in 0.2µm CMOS/SIMOX technology, dissipates 12mW at
1V, and provides 10dB NF with -15.7dBm IIP3.

BREAK 10:00 AM

44
 Wednesday, February 7th 8:30 AM

18.4 A 930MHz CMOS DC-Offset-Free Direct-Conversion 4-FSK

Receiver
10:15 AM
Z. Zhang, Z. Chen, L. Tsui, J. Lau
Hong Kong University of Science & Technology, Hong Kong, China

A 0.35µm CMOS single-chip direct-conversion 4-FSK receiver including all

necessary blocks eliminates both self-mixing and device mismatch induced
DC offsets. The overall offset at the receiver output is <1mV. It consumes
58mW at 3V, occupies 4.6mm2, has a 14.5dB NF with 10kHz IF, and
-26dBm front-end IIP3.

18.5 A 900MHz Dual Conversion Low-IF GSM Receiver in 0.35µm

CMOS
10:45 AM
S. Tadjpour1, E. Cijvat2, E. Hegazi1, A. Abidi1
1
University of California, Los Angeles, CA
2
Royal Institute of Technology, Sweden

A low-power fully-integrated GSM receiver IC measuring 2.2x4mm2 in

0.35µm CMOS uses a dual-conversion low-IF architecture with on-chip
VCO and full channel selection, image suppression and more than 100dB
of controllable gain. It consumes 24mA from a 2.5V power supply. The
receiver has 5dB noise figure and -16dBm IIP3 .

18.6 A 2GHz CMOS Image-Reject Receiver with Sign-Sign LMS

Calibration
11:15 AM
L. Der, B. Razavi
University of California, Los Angeles, CA

A Weaver image-reject architecture incorporates an LMS algorithm to

simultaneously calibrate gain and phase mismatches. In digital 0.25µm
CMOS technology, the receiver achieves 57dB image-rejection ratio, 5.2dB
noise figure, and -17dBm IIP3. The circuit consumes 50mW from a 2.5V
supply and occupies 1.23x1.84mm2.

CONCLUSION 12:15 PM

45
 SESSION 19 SALON 8

VOICEBAND, XDSL AND GIGABIT ETHERNET CIRCUITS AND

TRANSCEIVERS

Chair: Cormac Conroy, LSI Logic, Datapath Systems, San Jose, CA

Associate Chair: Loke Tan, Broadcom, Irvine, CA

19.1 A 285mW CMOS Single Chip Analog Front End for G.SHDSL
8:30 AM
P. Laaser, T. Eichler, H. Wenske, D. Herbison, H. Eichfeld
Infineon Technologies AG, Munich, Germany

A 0.5µm CMOS single-chip analog front end for G.SHDSL consists of

transmit current-steering DAC, noise shaping filter, on-chip line driver,
receive ADC, multi-bit 3rd-order ǻȈ ADC and active hybrid for analog echo
cancellation. The 12.8mm2 AFE dissipates 285mW from 5V supply and
supports 2.3Mb/s at 12kft.

19.2 A CMOS Direct Access Arrangement using Digital

Capacitive Isolation
9:00 AM
A. Krone, T. Tuttle, J. Scott, J. Hein, T. Dupuis, N. Sooch
Silicon Laboratories, Inc, Austin, TX

0.5µm CMOS direct access arrangement (DAA) uses high-voltage

discretes to interface device to the PSTN with loop current used for power
source.

19.3 A High-Voltage Line Driver for Combind Voice and ADSL

Services
9:30 AM
R. Apfel, B. Webb, R. Benton, J. Wenske, F. Thiel, W. Schofer
Legerity, Inc., Austin, TX

A 170V line driver allows voice and full-rate ADSL through a single line
interface without splitters. Low noise and good THD support data rates up
to 8Mb/s. The device is built in a high-voltage bipolar process and
consumes <2W.

BREAK 10:00 AM

19.4 An ADSL Central Office AFE Integrating an Actively-

Terminated Line Driver, Receiver, and Analog Filters
10:15 AM
M. Corsi, R. Hester, K. Maclean, M. Agah, J. Quarfoot, C. Kozak, N.
Gibson, T. Hagan
Texas Instruments, Dallas, TX

An analog front-end, fabricated in oxide-isolated complementary BiCMOS,

integrates the analog filters, synthesized-impedance line driver, and
receiver amplifier required for FDD ADSL central office applications.
External passives allow flexibility in hybrid design. The device employs a
single 15V supply and dissipates 1.1W.

46
 Wednesday, February 7th 8:30 AM

19.5 SOPA: A Highly-Efficient Line Driver in 0.35µm CMOS using

a Self-Oscillating Power Amplifier
10:45 AM
T. Piessens, M. Steyaert
KU Leuven, Leuven, Belgium

A driver in mainstream digital 0.35µm 3.3V technology drives loads down

to 2.4ȍ with efficiency >61% and 56.4dB spurious-free dynamic range. It
uses a self-oscillating scheme and coupling 2 self-oscillating power
amplifiers with a transformer. The chip occupies 4.6mm2.

19.6 A DSP Based Receiver for 1000BASE-T PHY

11:15 AM
R. He, N. Nazari, S. Sutardja
Marvell Semiconductor, Sunnyvale, CA

The receiver architecture of a CMOS IC that implements 1000BASE-T

PHY achieves 1000Mb/s transmission over 4-pair Cat-5 cabling up to 170m.
The DSP based receiver incorporates echo&NEXT cancellers, decision
feedback sequence estimator, timing recovery, baseline wander and delay
skew compensation. The power consumption is 1.8W.

19.7 A CMOS Transceiver Analog Front-end for Gigabit Ethernet

over CAT-5 Cables
11:45 AM
P. Roo, S. Sutardja, S. Wei, F. Aram, Y. Cheng
Marvell Semiconductor, Inc., Sunnyvale, CA

An integrated transceiver for gigabit Ethernet over UTP CAT-5 cables uses
0.18µm CMOS. The mixed-signal processing circuits use analog echo
cancellation and baseline correction with extensive DSP to achieve a
maximum transmit distance of 170m (BER<10-10). Dissipation is 1.8W on-
chip using a single 3.3V supply. The die is<25mm2.

CONCLUSION 12:15 PM

47
 SESSION 20 SALON 9

MULTI-GIGAHERTZ MICROPROCESSOR TECHNOLOGIES

Chair: Krste Asanovic, MIT, Cambridge, MA

Associate Chair: William Bowhill, Compaq, Shrewsbury, MA

20.1 A 1.8GHz Instruction Window Buffer

8:30 AM
J. Leenstra, J. Pille, A. Mueller, W. Sauer, R. Sautter, D. Wendel
IBM Entwicklung GmbH, Boeblingen, Germany

An instruction window buffer implements the processor parts for renaming,

reservation station and reorder buffer as a 64-entry unified buffer. Using
0.18µm 1.5V CMOS, it supports operation up to 1.8GHz. This frequency is
enabled by port reduction techniques, the instruction issue structure, and
the use of self-resetting circuits.

20.2 A Low-Power SOI Adder Using Reduced-Swing Charge-

Recycling Circuits
9:00 AM
A. Inoue1, W. Walker1, V. Oklobdzija2, M. Kai3, T. Izawa3
1
Fujitsu Laboratories of America, Inc., Sunnyvale, CA
2
Integration Corp., Berkeley, CA
3
Fujitsu Limited., Kanagawa, Japan

A low-power clocked static low-swing charge-recycling circuit technique is

applied to a 32b carry skip adder and fabricated in 0.08µm SOI CMOS.
Power consumption is reduced by 50% with no speed degradation
compared to that of a conventional CMOS adder.

20.3 Sub-500ps 64b ALUs in 0.18µ SOI/Bulk CMOS: Design &

Scaling Trends
9:30 AM
K. Soumyanath, S. Mathew, R. Krishnamurthy, M. Anders, R. Rios, K.
Mistry
Intel Corp., Hillsboro, OR

A 482ps 64b Han-Carlson ALU in 1.5V 0.18µm bulk CMOS directly ported
to 0.18µm SOI offers 14% performance improvement, after a 2% margin is
added for reverse body effect. An SOI-optimal redesign using a
quaternary-tree architecture improves the speedup to 19%. Scaling the
designs to 0.13µm for the two cases results in overall speedup of 9% and
16%, respectively.

BREAK 10:00 AM

48
 Wednesday, February 7th 8:30 AM

20.4 Design and Migration Challenges for an Alpha

Microprocessor in a 0.18µm Copper Process
10:15 AM
R. Hokinson, B. Benschneider, M. Arneborn, D. Clay, J. Clouser, S.
Dumford, V. Kalathur, V. Kalidindi, S. Kovvali, J. Krause, S. Maresh, B.
Munger, N. O’Neill, I. Pragaspathy, W. Qin, R. Sasamori, S. Sayadi, T.
Singh, M. Tracz, J. Tang, S. Watkins
Compaq Computer Corp., Shrewsbury, MA

An Alpha microprocessor with clock frequency >1.3 GHz is achieved by

migrating to a 0.18µm CMOS process with 7 layers of copper interconnect.
The technology challenges of converting an aluminum-based design to
copper are presented. The circuit and design solutions introduced by the
technology are discussed.

20.5 A 1GHz PA-RISC Processor

10:45 AM
L. Tsai
Hewlett-Packard, Fort Collins, CO

The processor is a leveraged design based on a previous generation of

PA-RISC processor. Improvements over the previous design are: a 0.18µm
silicon-on-insulator (SOI) process with 7-layer metal interconnects, 2.25MB
cache with row and column redundancies, 120-entry TLB, 50% frequency
boost, and 45% lower power with the same footprint.

20.6 4GHz Integer Execution Unit for 0.18µm CMOS

Microprocessor
11:15 AM
D. Sager, G. Hinton, M. Upton, T. Chappell, T. Fletcher, S. Samaan, R.
Murray
Intel, Hillsboro, OR

A microprocessor with an integer execution unit capable of fully-dependent

operations at 4GHz is fabricated in 0.18µm CMOS with 6 Al layers. Micro-
architectural and circuit techniques used are described.

CONCLUSION 11:45 AM

49
 SESSION 21 SALON 10-15

SIGNAL PROCESSING FOR COMMUNICATIONS

Chair: Ingrid Verbauwhede, UCLA, Los Angeles, CA

Associate Chair: Lars Thon, Atheros Communications, Palo Alto, CA

21.1 A Universal Cable Set-Top Box System on a Chip

8:30 AM
L. D'Luna, H. Law, J. Laskowski, W. Ngai, T. Kuo, J. Tang, X. Xie, J.
Patterson, Y. Vu, C. Walker, F. Cheung, C. Luu, M. Case, J. Anderson, F.
Gomez, L. Osborne, S. Jantzi, D. Cheung, A. Venes, P. Bushner, J.
Echtenkamp, D. Bogosh, H. Samueli
Broadcom Corporation, Irvine, CA

The device integrates a complete digital cable TV transceiver, MPEG-2

audio and video decoder, 2-D/3-D graphics processor and CPU running at
81MHz to achieve a true set-top box system-on-a-chip. The 14.6M
transistor IC in a 0.22µm CMOS process, consumes 3W, and incorporates
all required A/Ds and D/As for QAM/QPSK, audio, and video.

21.2 An Energy-Efficient IEEE 1363-based Reconfigurable Public-

Key Cryptography Processor
9:00 AM
J. Goodman1, A. Chandrakasan2
1
Chrysalis-ITS, Ottawa, Ontario, Canada
2
Massachusetts Institute of Technology, Cambridge, MA

A reconfigurable public-key cryptography processor has 2 to 3 orders of

magnitude lower energy consumption than existing software and
programmable logic-based implementations. The processor ISA is based
on the IEEE 1363-2000 Public Key Cryptography Standard. At 50MHz the
processor consumes 75mW at 2V VDD in 0.25µm CMOS. At 3MHz it
consumes 525µW at 0.7V.

21.3 A Self-Contained 100µW Multirate FSK Receiver ASIC

9:30 AM
E. Grayver, B. Daneshrad
UCLA, Los Angeles, CA

A self-contained FSK receiver targets deep-space and terrestrial

communications. It supports variable data rates and is robust against
Doppler. Key features are subsampling, 1b quantization, and FFT based
detection. Low-power circuits are designed for FFT, DDFS, and
decimation. The power consumption is below 100µW for data rates below
20kbps. Rates up to 2Mb/s are supported.

BREAK 10:00 AM

50
 Wednesday, February 7th 8:30 AM

21.4 A Single-chip Band-Segmented-Transmission OFDM

Demodulator for Digital Terrestrial Television Broadcasting
10:15 AM
H. Ohwada1, M. Yoshida1, N. Ohtaka1, M. Hamaminato1, K. Hatta2, M.
Tamamura2, Y. Otobe1
1
Fujitsu Laboratories LTD., Kawasaki, Japan
2
Fujitsu Limited, Kawasaki, Japan

A single-chip OFDM demodulator for Japanese Digital Terrestrial TV

integrates all necessary OFDM demodulator functions, such as 10b ADC,
8192-point FFT processor, and error correction. The chip has multi-layer
transport stream capability for a variety of services relevant to future digital
broadcasting.

21.5 A Digital 72Mb/s 64-QAM OFDM Transceiver for 5GHz

Wireless LAN in 0.18µm CMOS
10:45 AM
W. Eberle1, V. Derudder2, L. Van der Perre2, G. Vanwijnsberghe2, M.
Vergara2, L. Deneire2, B. Gyselinckx2, M. Engels2, I. Bolsens2, H. De Man3
1
IMEC and K.U. Leuven, Leuven, Belgium
2
IMEC, Leuven, Belgium

A parameterizable 64-carrier OFDM transceiver for 72Mb/s 5GHz wireless

LAN with a 20MHz bandwidth encompasses (de)framing, (I)FFT, adaptive
interpolating equalization for BPSK, QPSK, 16-QAM and 64-QAM, full
synchronization and tracking. The 20.8mm2 0.18µm 1.8V/3.3V CMOS IC,
based on distributed control and dynamic clock gating, uses a mixed
C++/VHDL flow.

21.6 A Single-Chip PHY COFDM Modem for IEEE 802.11a with

Integrated ADCs and DACs
11:15 AM
N. Weste1, R. Keaney1, P. Ryan1, T. Arivoli1, U. Parker1, G. Smith1, G.
1 1 1 2 2
Foyster , G. Zyner , L. DeSouza , A. Moini , S. Alsawari
1
Radiata Communications, Level 2, North Ryde, Australia
2
University of Adelaide, Adelaide, Australia

A single-chip 64 tone OFDM modem that provides for 6 to 54Mbs WLANs

is implemented in 0.25µm, 5M-1P CMOS, the 3.7M transistor mixed-signal
chip contains a fully compliant 802.11a modem, dual 10b 40MHz ADCs,
dual 10b 80MHz DACs and a 5b RSSI ADC.

CONCLUSION 11:45 AM

51
 SESSION 22 SALON 1-6

TD: SYSTEM-ON-A-CHIP

Chair: B. Athas, Apple Computer, Cupertino, CA

Associate Chair: J. Long, Univ. of Toronto, Toronto, Canada

22.1 Substrate Noise Generation in Complex Digital Systems:

Efficient Modeling and Simulation Methodology and
Experimental Verification
1:30 PM
M. van Heijningen1, M. Badaroglu1, S. Donnay1, H. De Man1, G. Gielen2, M.
Engels1, I. Bolsens1
1
IMEC, Leuven, Belgium
2
K.U. Leuven, Leuven, Belgium

An 86kgate ASIC has on-chip noise sensors for accurate direct substrate
noise measurements. Modeling and simulation methodology accurately
predict substrate noise generation of large digital circuits. The difference
between measured and simulated RMS substrate voltage is <10%.

22.2 ChipOS: Open Power-Management Platform to Overcome

the Power Crisis in Future LSIs
2:00 PM
H. Mizuno, T. Kawahara
Hitachi, Ltd., Central Research Laboratory, Tokyo, Japan

ChipOS, a power-aware operating system in a chip, provides open power-

management platform for system-on-a-chip devices. It enables a large
degree of high-speed operation on a limited power budget in the same way
that operating systems now make personal computers run multiple
applications with a limited computing or memory capacity.

22.3 Elastic Interconnects: Repeater-Inserted Long Wiring

Capable of Compressing and Decompressing Data
2:30 PM
M. Mizuno1, W. Dally2
1
NEC Corporation, Kanagawa, Japan
2
Stanford University, Stanford, CA

A network communication technique, elastic interconnect, is made possible

using on-chip repeater-inserted long wiring. Latency, throughput, and
saturation throughput are improved by approximately 20% to 40% in
simulations by compressing and decompressing data in interconnects.

BREAK 3:00 PM

52
 Wednesday, February 7th 1:30 PM

22.4 An Implementation of Two Multiprocessor DSPs: A Design

Methodology Case Study
3:15 PM
J. Williams, J. O'Neill
Lucent Technologies, Holmdel, NJ

Implementation results of two code-compatible multiprocessor DSPs are

presented. Although process, libraries, and tools where identical, one
design achieved 16x the peak DSP MIPS of the other in the same die area.
Transistor density improved by 10x and clock frequency by 2x. Results
demonstrate the impact of design methodology on IC design.

22.5 A GSM 2+ Conversion Signal Processor for

Continuous Full-Duplex EDGE/GPRS Applications
3:45 PM
R. Walden1, R. Khoini-Poorfard2, H. Fetterman1, T. Hearn1, R. Jeffery1, P.
3 4 1 1 1
Liu , A. Lukoff , M. Mangahas , D. Martin , J. Mena , A. Webb
1
Lucent Technologies, Allentown, PA
2
Silicon Labs
3
Optronx Inc.
4
PMC-Sierra

A 35mm2 0.3µm 3V CMOS IC supports both continuous and full-duplex

classes of EGPRS / GSM 2+ operation with reduced standby power. The
chip includes digital offset correction, actively-tuned baseband filters, an
expanded GSM-optimized programmable timing control unit, and a power-
saving ADC architecture.

22.6 A Fully-Configurable GSM BTS Controller and GMSK-EDGE

Base-Band Transmitter IC
4:15 PM
T. Delmot, E. Marreel, F. Bonjean, B. Verstraeten, S. Taraborrelli, A. Udahl
Alcatel Telecom, Antwerp, Belgium

A GSM base transceiver station controller and base band transmitter in a

CMOS 0.5µm 3.3V technology embeds a fully-configurable GMSK/EDGE
baseband signal generator, a power-ramping controller, and a dual fully-
programmable 10 to 270MHz PLL. One bandgap reference voltage and
four programmable calibration voltage generators are also integrated.

22.7 A Multicarrier GMSK Modulator for Base Stations

4:45 PM
J. Vankka , J. Pyykönen2, J. Sommarek1, M. Honkanen2, K. Halonen1
1
1
Electronic Circuit Design Laboratory, Helsinki University of Technology,
Espoo, Finland
2
Nokia Research Center, Finland

A multicarrier GMSK modulator with 14b on-chip D/A converter occupies

26.8mm2 in 0.35µm CMOS (in BiCMOS) and dissipates 706mW at 3.3V
with 52MHz. Power ramping and dynamic output power level control is
digital. The digital modulator fulfills spectrum and phase error specifications
of GSM 900 and DCS 1800 base stations.

CONCLUSION 5:15 PM

53
 SESSION 23 SALON 7

ANALOG TECHNIQUES

Chair: Venu Gopinathan, Broadcom, Irvine, CA

Associate Chair: Brian Brandt, National Semiconductor, Salem, NH

23.1 A Synchronous Dual-Output Switching dc-dc Converter

Using Multibit Noise-Shaped Switch Control 1:30 PM

Marcus May, Michael May , J. Willis

Sigmatel, Austin, TX

A synchronous dc-dc converter generates two indepedent output voltages

using a single external inductor. The all-digital control logic includes a
multibit Ȉǻ modulator, which reduces quantization artifacts from
synchronous switching of the inductor. The circuit occupies 0.6mm2,
consumes 3.5mW, and reaches efficiencies >80%.

23.2 Dynamically Biased 1MHz Low-pass Filter with 61dB peak

SNR and 112dB Input Range 2:00 PM

N. Krishnapura, Y. Tsividis
Columbia University, New York, NY

In quiescent condition, a dynamically biased filter, occupying 0.52mm2 in a

0.25µm BiCMOS process, draws 575µW from 2.5V, and has 4.4nArms
output noise. S/N is >50dB over 3 decades of input and THD is <1% for
inputs <2.5mA peak. The bias can be varied to minimize noise and power
consumption without disturbing the output.

23.3 A 200nV Offset 6.5nV/¥Hz Noise PSD 5.6kHz Chopper

Instrumentation Amplifier in 1µm Digital CMOS 2:30 PM

Q. Huang, C. Menolfi
Swiss Federal Institute of Technology (ETH), Zurich, Switzerland

Simple clocking substantially reduces residual offset usually found in

chopper amplifiers due to charge injection. Compared to well-established
techniques of using LP or BP amplifiers for residual offset reduction,
improvement is 5-fold over state-of-the-art. Bandwidth is not sacrificed, so
chopper frequency is 350x that used in the nested chopper technique.
Noise psd is as low as 6.5nV/¥Hz and CMRR is 150dB.

23.4 A Filtering Technique to Lower Oscillator Phase Noise

2:45 PM
E. Hegazi, H. Sjoland, A. Abidi
University of California, Los Angeles, CA

A filtering technique reduces phase noise of differential LC oscillators using

passive LC filters. Three fully-integrated LC VCOs serve as proof of
concept. Two 1GHz VCOs achieve -152dBc/Hz and -148.5dBc/Hz at 3MHz
offset, biased at 3.7mA from 2.5V. A 2.1GHz VCO achieves -148dBc/Hz at
15MHz offset, drawing 4mA from 2.7V supply.

BREAK 3:00 PM

54
 Wednesday, February 7th 1:30 PM

23.5 A 12b 500MSample/s Current-Steering CMOS D/A Converter

3:15 PM
A. Van den Bosch, M. Borremans, M. Steyaert, W. Sansen
K.U. Leuven, Heverlee, Belgium

A 12b 500MSample/s current-steering CMOS DAC requires no tuning or

trimming. INL is 0.3LSB. SFDR is 74.3dB at 500kHz and 62dB at 125MHz
for an update rate of 500MSample/s. At this update rate, the DAC
consumes 110mW for a Nyquist output signal. The chip has 1mm2 active
area.

23.6 A 1.9GHz Si Active LC Filter with On-Chip Automatic Tuning

3:45 PM
D. Li , Y. Tsividis2
1
1
Lucent Technologies, Murray Hill, NJ
2
Columbia University, New York, NY

A 1.9GHz 4th-order bandpass active LC filter, which exhibits 49dB SFDR

and a 1dB compression DR of 63dB, is integrated in 0.25µm resonator
BiCMOS. An on-chip tuning system automatically adjusts center frequency
Q. The filter draws 18 mA from a 3V supply, with another 18 mA drawn
periodically while the tuning mechanism is activated.

23.7 A 0.25µm CMOS 17GHz VCO 4:15 PM

C. De Ranter, M. Steyaert
K.U. Leuven, Leuven, Belgium

A 17GHz fully-integrated VCO uses global optimization of all blocks.

Layout is symmetrical. Measurements show a phase noise as low as
-108dBc/Hz at 1MHz for a 10.5mW power consumption. The tuning range
is 8.6%. A 0.25µm, 4-metal standard CMOS technology is used.

23.8 A 50GHz VCO in 0.25µm CMOS 4:30 PM

H. Wang
Bell Labs, Murray Hill, NJ

A fully integrated 50GHz VCO in 0.25µm CMOS works with a 1.3V supply
and consumes 13mW. The measured phase noise is -99 dBc/Hz at 1MHz
offset from the center frequency and the tuning range is 1.1GHz.

23.9 A Wideband BiCMOS VCO for Multi-Mode Mobile Phones

4:45 PM
J. Kucera
Infineon Technologies AG, Munich, Germany

A packaged 1.75-2.51GHz VCO has phase noise of -99dBc/Hz and

-128.5dBc/Hz at 20kHz and 600kHz frequency offset, respectively. The
differential VCO in 25GHz BiCMOS technology dissipates 12mW and uses
the package bond-wire of a standard TSSOP plastic package with an on-
chip pn diode as resonator tank.

CONCLUSION 5:00 PM

55
 SESSION 24 SALON 8

DRAM

Chair: Tae-Sung Jung, Samsung, Yongin-City, Korea

Associate Chair: Roger Norwood, Micron, Richardson, TX

24.1 A 4Gb DDR SDRAM with Gain-Controlled Pre-Sensing and

Reference Bitline Calibration Schemes in the Twisted Open
Bitline Architecture
1:30 PM
H. Yoon, J. Sim, H. Lee, K. Lim, W. Yang, H. Jeong, J. Yoo, D. Seo, K.
Kim, B. Yoo
Samsung Electronics, Kyungki, Korea

A 1.8V 645mm2 4Gb DDR SDRAM provides low-voltage high-speed

operation at full density. Inter-bitline coupling noise is reduced in the
twisted open bitline architecture. The amplifier sensitivity and sensing
margin are improved with gain-controlled pre-sensing and active calibration
of the bitline precharge voltage.

24.2 A Multi-Gigabit DRAM Technology with 6F2 Open Bit-line

Cell Distributed Over-Driven Sensing and Stacked-Flash
Fuse
2:00 PM
T. Takahashi1, T. Sekiguchi2, R. Takemura2, S. Narui1, H. Fujisawa1, S.
Miyatake3, M. Morino3, K. Arai3, S. Yamada1, S. Shukuri4, M. Nakamura1,
Y. Tadaki1, K. Kajigaya1, K. Kimura2, K. Itoh2
1
ELPIDA Memory.Inc., Tokyo, Japan
2
Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan
3
Hitachi ULSI Systems Co., Ltd., Tokyo, Japan
4
Semiconductor & Integrated Circuits Div., Hitachi, Ltd., Tokyo, Japan

A multi-gigabit DRAM technology features a low-impedance array for 6F2

open-bit-line cell, distributed overdriven sensing for operation below 1V,
and stacked-flash fuse leading to a 10-order of magnitude fuse failure rate
reduction. The technology, which can be used to fabricate a 0.13µm,
180mm2 1GbDRAM, is verified using a 57.6 mm2 200MHz array-cycle
256Mb test chip with 0.109µm2 cells.

24.3 A 113mm2 600Mb/sec/pin 512Mb DDR2 SDRAM with

Vertically Folded Bitline Architecture
2:30 PM
T. Kirihata1, S. Loeffler2, M. Clinton1, B. Ji1, H. Terletzki2, D. Hanson1, C.
Hwang1, G. Lehmann2, D. Storaska1, G. Daniel2, L. Hsu1, O. Weinfurtner2,
T. Boehler2, J. Schnell2, G. Frankowsky2, D. Netis1, J. Ross1, A. Reith2, G.
Mueller2, O. Kiehl2, M. Wordeman1
1
IBM Microelectronics, Hopewell Junction, NY
2
Infineon Technologies, Hopewell Junction, NY

A 113mm2 512Mb DDR2 SDRAM employs a 4 quadrant architecture using

a vertically folded bitline sensing and hierarchical row and column
decoders for 6.6F2 cross point vertical access gate cells. The chip supports
4b prefetch, back-to-back RAS, and flexible calibration, resulting in
600Mb/sec/pin.

BREAK 3:00 PM

56
 Wednesday, February 7th 1:30 PM

24.4 A 1.0V 230MHz Column Access Embedded DRAM Macro

with Dual Interface and Triple Test Functions for Portable
MPEG Applications
3:15 PM
S. Tomishima1, T. Tsuji1, T. Kawasaki2, M. Ishikawa1, T. Inokuchi2, H.
Kato , H. Tanizaki , W. Abe , A. Shibayama , Y. Fukushima , M. Niiro1, M.
1 3 2 2 2

Maruta1, T. Uchikoba2, M. Senoh2, S. Sakamoto2, T. Ooishi1, H. Kikukawa2,

H. Hidaka1, K. Takahashi2
1
Mitsubishi Electric Corp., Hyogo, Japan
2
Matsushita Electric Industrial Co., Ltd., Kyoto, Japan
3
Mitsubishi Electric Engineering Co., Ltd., Kanagawa, Japan

A 1.0V 230MHz random column access 32Mb embedded DRAM macro for
portable MPEG codec LSI uses 0.13µm 3-well 4-level Cu embedded
DRAM technology. Peak power consumption is suppressed to 198mW in
burst accesses. With dual interface and triple test functions, the macro die
is 18.9mm2.

24.5 A 1.43GHz Per Data I/O 16Mb DDR Low-Power DRAM Macro
for A 3D Graphics Engine
3:45 PM
K. Hardee1, O. Jones1, M. Parris1, D. Butler1, L. Aldrich1, P. Austin1, K.
Jacobsen1, M. Miyabayashi2, K. Taniguchi2, T. Arakawa2
1
United Memories, Inc., Colorado Springs, CO
2
Sony Corporation Core Technology & Network Company, Tokyo, Japan

A 15.75mm2 16Mb embedded DRAM macro has 256 DDR I/Os and
employs a hidden write function and local read/write data drivers to achieve
1.43GHz data rate with concurrent read/write for use in a 4Tera-b/s 3D
graphics chip. The macro is fabricated in 1.5V 0.18µm CMOS.

24.6 An Embedded DRAM Hybrid Macro with Auto Signal

Management and Enhanced On-Chip Tester
4:15 PM
N. Watanabe1, F. Morishita1, Y. Taito1, A. Yamazaki1, T. Tanizaki1, K.
Dosaka1, Y. Morooka1, F. Igaue2, K. Furue1, Y. Nagura1, T. Komoike1, T.
Morihara1, A. Hachisuka1, K. Arimoto1, H. Ozaki1
1
Mitsubishi Electric Corp., Hyogo, Japan
2
Mitsubishi Electric Engineering Co., Ltd., Hyogo, Japan

An embedded DRAM hybrid (hardware, software) macro generates a

variety of memory specifications. The macro employs auto signal
management providing more than 120k eDRAM macros and a range
operation from 1.2 to 1.8V. An enhanced-on-chip tester realizes
simultaneous 512b I/O repair analysis, and reduces the testing time to 1/64
that of conventional on-chip tester.

CONCLUSION 4:45 PM

57
 SESSION 25 SALON 9

CLOCK GENERATION AND DISTRIBUTION

Chair: Alisa Scherer, Advanced Micro Devices, Sunnyvale, CA

Associate Chair: Stefanos Sidiropoulos, Rambus Inc.,
Mountain View, CA

25.1 A 4GHz 40dB PSRR PLL for SOC Application

1:30 PM
J. Ingino
SiByte Inc., Santa Clara, CA

A 4GHZ PLL employs a voltage regulator to achieve 40dB minimum PSRR

using a gain boosted regulator. Peak cycle-to-cycle jitter is 25ps at
700MHz with a 500mV step on the regulator 3.3V supply. In a 0.15µm 5-
metal digital CMOS process, area is 1.48mm2, and power dissipation is
130mW.

25.2 A Low-Jitter 125-1250MHz Process-Independent 0.18µm

CMOS PLL Based on a Sample-Reset Loop Filter
2:00 PM
A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko, D. Stiurca
Crystal Cirrus Logic, Austin, TX

A low-jitter frequency synthesizer in 0.18µm CMOS uses the sample-reset

loop filter technique to achieve a process-independent damping factor and
low jitter operation with minimum ripple-filtering pole requirements. PLL
specifications include: operating range 125-1250MHz, resolution <500kHz,
jitter <0.3%×Tosc, and power dissipation 75mW from 2.5V supply.

25.3 A Low-Jitter Skew-Calibrated Multi-Phase Clock Generator

for Time-Interleaved Applications
2:30 PM
L. Wu, W. Black
Iowa State University, Ames, IA

An adaptive skew-compensating four-phase clock generator operating from

100MHz-250MHz continuously self-calibrates skew of the output clocks.
Pre-calibration edge timing skews of 50ps or more are automatically
reduced to <10ps in 0.25µm standard bulk CMOS process operating at
2.5V.

BREAK 3:00 PM

58
 Wednesday, February 7th 1:30 PM

25.4 A 2.5GHz 4-phase Clock Generator with Scalable and

No Feedback Loop Architecture
3:15 PM
K. Yamaguchi, M. Fukaishi, T. Sakamoto, N. Akiyama, K. Nakamura
NEC Corporation, Sagamihara, Japan

An accurate simple multi-phase clock generator using delay compensation

based on phase interpolation is applied to 2.5GHz 4-phase clock
distribution of a 5Gb/s x 8-channel receiver in 0.13µm CMOS technology.
The 4-phase generator in the receiver consumes 30mW and occupies
0.009mm2.

25.5 Multi-GHz Low-Power Low-Skew Rotary Clock Scheme

3:45 PM

S. Lipa1, J. Wood2, P. Franzon1, M. Steer1

1
North Carolina State University, Raleigh, NC
2
Multigig Corp. Ltd.

A clock distribution scheme for VLSI circuits uses rings of differential lines
driven by inverter pairs to distribute a low-skew low-jitter clock over an
arbitrarily large die area with low power consumption. Results are shown
for a prototype with 950MHz and 3.42GHz rings.

25.6 The Design and Analysis of the Clock Distribution Network

for a 1.2GHz Alpha Microprocessor
4:15 PM
T. Xanthopoulos, D. Bailey, A. Gangwar, M. Gowan, A. Jain, B. Prewitt
Compaq, Shrewsbury, MA

A 1.2GHz clock system for a 0.18µm CMOS microprocessor employs three

digital DLLs to phase-lock the memory and interface clocks to the core
CPU clock. The fully-digital DLLs use a 64/8 coarse/fine delay line to
extend the locking range.

25.7 A Multi-GHz Clocking Scheme for Pentium® 4

Microprocessor
4:45 PM
N. Kurd, J. Barkatullah, P. Madland, T. Fletchter, R. Dizon
Intel Corp, Hillsboro, OR

Two tightly-synchronized PLLs generate core and I/O clocks on this 4th
generation IA32 microprocessor. Clock distribution to 47 domains is
adjusted for supply, loading, and on-die variations to reduce skew to 20ps.
Pulse and double frequency clocks are locally generated.

CONCLUSION 5:15 PM

59
 SESSION 26 SALON 10-15

WIRELESS BUILDING BLOCKS II

Chair: Michiel Steyaert, KU Leuven, Belgium

Associate Chair: Raf Roovers, Philips Research, Eindhoven, The
Netherlands

26.1 A Triple-Band 900/1800/1900MHz Low-Power Image-Reject

Front-End For GSM
1:30 PM
R. Magoon1, I. Koullias2, L. Steigerwald2, W. Domino1, N. Vakilian1, E.
Ngompe1, M. Damgaard1, K. Lewis2, A. Molnar1
1
Conexant Systems Inc., Newport Beach, CA
2
Wireless Microsystems, Reading, PA

A triple-band RF front-end including on-chip integrated LC image-reject

filters achieves >40dB image rejection over all bands with 15-18mA supply
current. The device uses 28 on-chip spiral inductors on a 2.25x2.75mm2
BiCMOS die. Measured NF is 2.5dB(GSM), 3.6dB(DCS), 3.8dB(PCS) and
measured input 1dB compression is >-21dBm.

26.2 A 0.8dB NF ESD-Protected 9mW CMOS LNA

2:00 PM
P. Leroux, J. Janssens, M. Steyaert
KU Leuven, Heverlee, Belgium

A 0.25µm CMOS LNA for the L2 GPS band at 1.2276GHz features 0.8dB
noise figure and 20dB power gain consuming 9mW. Apart from the input
bonding wire, the 50ȍ input and output matching networks are
implemented on-chip. The ESD-protection at the input withstands HBM-
pulses from -1.4 to 0.6kV.

26.3 A 19GHz 0.5mW 0.35µm CMOS Frequency Divider with

Shunt-Peaking Locking-Range Enhancement
2:30 PM
H. Wu, A. Hajimiri
California Institute of Technology, Pasadena, CA

Shunt-peaking locking-range enhancement used in a 19GHz 0.35µm

CMOS injection-locked frequency divider (ILFD) gives 760MHz locking
range and 0.5mW dissipation at -12dBm injection power level. The locking
range can be further increased with higher injection power. A second 9GHz
ILFD with 880MHz locking range is also reported.

BREAK 3:00 PM

60
 Wednesday, February 7th 1:30 PM

26.4 A 2GHz Down-Converter with 600MHz 3dB Bandwidth using

LO Signal Suppressing Output Buffer
3:15 PM
O. Watanabe, T. Yamaji, T. Itakura, I. Hattori
Toshiba Corporation, Kawasaki, Japan

A 2GHz down-converter with a 3dB bandwidth of 600MHz is fabricated in

BiCMOS process. The conversion gain varies <0.7dB for temperature
range from -34 to 85oC. NF is 9.5dB and IIP3 is -5dBm. The down-
converter consumes 15mA from 2.7V power supply, and occupies
approximately 1mm2.

26.5 3V GSM Base Station RF Receivers using 0.25µm BiCMOS

3:45 PM
J. Lin1, O. Boric-Lubecke1, P. Gould1, C. Zelley2, Y. Chen3, R. Yan1
1
Bell Labs, Lucent Technologies, Murray Hill, NJ
2
DERA, UK
3
WIN Semiconductors

Two integrated RF receivers for GSM900 and DCS1800 base stations use
a 0.25µm BiCMOS process. Noise figure, gain, and output IP3 are 2.1dB,
25.3dB, and 23.6dBm for GSM900, and 3.3dB, 20.7dB, 21.6dBm for
DCS1800, respectively.

26.6 A 2.4GHz 34mW CMOS Transceiver for Frequency-Hopping

and Direct-Sequence Applications
4:15 PM
A. Zolfaghari, A. Chan, B. Razavi
UCLA, Los Angeles, CA

A 2.4GHz heterodyne transceiver consists of a dual-downconversion

receiver with partial channel-selection filtering, a two-step quadrature
upconversion transmitter, and a 1.6GHz frequency synthesizer. Fabricated
in a 0.25µm CMOS technology, the transceiver consumes 34mW.

26.7 SiGe BiCMOS Broadband Phase Aligner from 1 to 11Gb/s

4:45 PM
R. Hofmann, B. Jelonnek, H. Kling, A. Splett. E. Koenig
Siemens AG, Ulm, Germany

An all digital serial-bit-stream phase-aligner for CDMA, GSM and EDGE

applications, operates from 1 to 11Gb/s, in SiGe BICMOS. With peak-to-peak
jitter up to 20ps, bit error rate is <4.8x10-14. The 0.9x0.85mm2 chip, employing
584 bipolar transistors, consumes 485mW at 5V.

CONCLUSION 5:00 PM

61
 TUTORIALS

Front-End Circuits for Optical Communications

An introduction to optical receiver circuits is presented with focus on
integration at >10Gb/s data rate in SiGe technology. Basic system
requirements and design considerations. TZ-, AGC and limiting amplifiers,
clock and data recovery, demultiplexer circuits, linear binary clock recovery
architectures, and SONET jitter characteristics will be discussed.
Instructor: Yuriy M.Greshishchev, Nortel Networks, Ottawa, Canada
received the PhD in Electrical and Computer Engineering from V.M.
Glushkov Institute of Cybernetics, Microelectronics Division, Kiev, Ukraine,
in 1984. He is an advisor on high-speed communications circuit design
developing highly integrated circuits in emerging technologies for 10-
40Gb/s optical communications. His recent work is on a 10Gb/s fully-
integrated SiGe receiver for SONET. He has co-authored 2 books and
numerous technical papers on high-speed communication circuit design
and data converters.

Logical Effort – Designing Fast CMOS Circuits

Designers of high-speed integrated circuits face a bewildering array of
choices and too often spend frustrating days tweaking gates to meet speed
targets. Logical Effort provides a simple method for estimating gate delays
and evaluating tradeoffs of circuit topologies and gate sizes.
Instructor: David Harris is Assistant Professor of Engineering at Harvey
Mudd College. His research interests are in the area of high-speed
integrated circuit design, especially timing, domino circuits, and arithmetic
units. He is coauthor of a book on Logical Effort and author of Skew-
Tolerant Circuit Design. Prof. Harris has consulted for numerous design
teams at Sun Microsystems, Hewlett-Packard, Intel, and elsewhere in the
area of high speed circuits. He received M.Eng. and SB from MIT in 1994
and PhD in EE form Stanford University In 1999 and M.Eng. and S.B. from
MIT in 1994.

Network Processing ICs

Architectural and design issues of the ASIC architectures dedicated to
specific network processing functions, known as packet processors, for key
functions in high-speed switches and routers will be reviewed. Topics
include: (1) Switch architecture and queue management: Ethernet switch
architectures, input queuing vs. output queuing, multicasting, QoS, buffer
management (2) Multi-layer switching: L2 search and learn, VLAN, L3
longest-prefix-match search, IP multicast, L4-7 classification (3) Emerging
standards/interfaces: 10G Ethernet (XGMII), UTOPIA-4, Packet-over-
SONET (POS), Common Switch Interface Specification (CSIX), InfiniBand
Instructor: C. Bernard Shung, Allayer Communications, San Jose, CA
received PhD in EECS from UC Berkeley in 1988. He is Design Manager
responsible for highly-integrated multi-layer products. He led the first
10GbE switching processor with 44Gb/s bandwidth. He has been at IBM
Almaden, CA and Qualcom, San Diego, and was Professor of EE at
National Chiao Tung University, Hsinchu, Taiwan, where his research was
on ATM switching, wireless communications, error-correcting codes, and
cryptography.

Low-Power Design Techniques for Microprocessors

Microprocessors have become prevalent in today’s handheld wireless
electronic era. The design of the microprocessor significantly impacts
power consumption and hence battery life, a crucial metric in any portable
device. This tutorial discusses design techniques and issues for low power
microprocessor design. The presentation covers design, from system
architecture to transistor sizing. Areas covered include static and dynamic

62
 TUTORIALS

power consumption, process issues, leakage control, logic design styles

and transistor sizing.
Instructor: Simon Segars, ARM Inc., Austin, TX holds a BEng in EE from
Univ. of Sussex, England, and a MSc in Low-Power CPU Design from
Univ. of Manchester, England. He is Director of CPU Development at ARM
Austin Design Center. At ARM since early 1991, he has worked on most of
ARMs CPU products since then. He led development of the ARM7 and
ARM9 Thumb families and now oversees architectural specification of future
high-performance processors. He holds a number of patents on embedded
CPU architectures.

Broadband Design for Wireless and Wired Systems

System requirements and IC design techniques for broadband wireless
and wired systems are discussed. Two example systems, high-definition
television and cable modems, are used as real-world examples.
Broadband design issues are contrasted with the narrowband design styles
that are well known to wireless engineers today. In particular, design
techniques for realizing wide bandwidth matching, low noise, and low
distortion including composite beats are described in detail.
Instructor: Bud Taddiken, Microtune, Plano, TX joined Microtune in 1996
as Director of RFIC Development and became Vice President of IC
Engineering in 1998. From 1983 to 1996, he held various positions with
Texas Instruments, most recently RFIC Design Manager for Transmitters
and PLLs and Member, Group Technical Staff. He has authored or
coauthored over 30 conference or journal papers and holds a BSEE from
MIT and six US patents.

Integrated Electronics for Displays

Displays are the primary interface for information technology users,
especially in today's Internet age. Today's displays must compete in a cost-
sensitive market, which drives innovation in display module technology, its
interface and timing control components, and system integration. An
overview of the latest display technology includes coverage of key
electronic components used today and future opportunities for integration.
Instructors: Philip Alvelda, MicroDisplay, San Pablo, CA received BS in
Physics and Computer Science at Cornell University in 1986, and MS and
PhD in Electrical Engineering and Computer Science from MIT in 1993 and
1994. After working at NASA developing high-precision CCD star and
target trackers, he founded and was Chief Technology Officer of the
MicroDisplay Corp. He has been a Principal Investigator and director of
several DARPA research projects in display technology. He is currently
CEO of Idetic, Inc., a member of IEEE and SID, and is an invited industry
speaker. He holds 15 patents and has presented more than 30 technical
papers.
Instructors: Kai Schleupen, IBM, Yorktown Heights, NY Dr. Schleupen
received MS in 1989 and PhD in 1995, at the Laboratory for Flat Panel
Displays of University of Stuttgart, Germany. From 1995 to 1996 he worked
in the Display Research Dept at AT&T Bell Labs, Murray Hill, NJ. In 1996,
he joined the IBM T.J. Watson Research Center in Yorktown Heights, NY,
where he now manages the Display Design and Electronics Dept.
responsible for design of high-resolution direct-view displays for desktop
and portable applications. He holds 12 patents and is author or co-author
of over 20 technical publications. He is member of IEEE and SID.

63
 SHORT COURSE

CMOS RF CIRCUITS

This Short Course is intended to jumpstart engineers in design and

development of CMOS circuits for wireless applications. Course completion
provides an overall perspective of system tradeoffs along with detailed
circuit design strategies for key RF wireless transceiver building blocks.
Topics include overview of mobile wireless systems and key metrics of RF
design, low noise amplifier characteristics, tradeoffs and designs,
fundamentals of mixer design for RF receivers, and CMOS oscillator circuit
analysis and design.

For Registration, please use the ISSCC 2001 Registration Website or the
Form in the Advance Program Centerfold. Sign-in is at the San Francisco
Marriott Hotel, Level B-2, beginning at 8:00 AM, February 8.

The Short Course will be offered three times on Thursday, February 8.

The first session is scheduled for 8:00AM to 4:30PM.
The second session is scheduled for 10:00AM to 6:30PM.
The third session is scheduled for 1:30PM to 9:30PM.

CD of the Short Course & Relevant Papers: Short Course registrants

will receive a CD-ROM of the Short Course with relevant papers and
background material. The CD-ROM includes: (1) PDF version of
presentations for printing hard copy of slides, (2) Bibliographies of relevant
papers for all presentations, (3) PDF copies of relevant background
material and important papers in the field (about 10-20 papers per
presentation).

OUTLINE

MOBILE TRANSCEIVER DESIGN SYSTEM OVERVIEW

(8:00A-9:30A), (10:00A-11:30A), (1:30P-3:00P)

RF designers must consider noise figure, intercept, and compression

points in the context of system requirements such as sensitivity, selectivity,
and resilience to blocking and interference. Significance of power
consumption in modern mobile communications and trade-off among cost,
power, size, and weight of mobile terminals in CMOS implementations are
discussed.
Instructor: Qiuting Huang received PhD from Katholieke Universiteit
Leuven (1987). After five years as lecturer at the University of East Anglia,
Norwich, UK, he joined the Integrated Systems Laboratory, Swiss Federal
Institute of Technology (ETH), Zurich. His research interests are in the
design of radio-frequency and baseband ICs for wireless communications.
He is member of the ISSCC and European Solid-State Circuit Conference
Program Committees. He was awarded the Transactions on Electronics
best paper award (1997) and participated in the ISSCC Best Panel.

LOW-NOISE AMPLIFIERS
(10:00A-11:30A), (12:00P-1:30P), (3:30P-5:00P)
Design issues for RF low-noise amplifiers in fine-line CMOS and basic LNA
performance parameters are reviewed. Gain, frequency, noise, linearity,
power dissipation, supply voltage, and input/output matching tradeoffs are
presented in terms of CMOS scaling trends for active and passive devices
in single-ended and fully-differential implementations. Merged LNA/filter
topologies with design examples illustrating tradeoffs are discussed.
Instructor: David J. Allstot received PhD from UC Berkeley in 1979. He
is currently the Boeing-Egtvedt Chair Professor in EE at the University of

64
 SHORT COURSE

Washington and a Technical Consultant with Mobilian Corp. He has

advised about 60MS and PhD graduates, published more than 150
papers, and received several best paper awards and several outstanding
teaching and advising awards. His current research includes data
converters and RF circuits. He is an IEEE Fellow.

CMOS UP AND DOWN CONVERTERS

(1:00P-2:30P), (3:00P-4:30P), (5:30P-7:00P)

Modern transceivers often use co-designed receiver architectures and

mixer topologies. For these architectures, different up and down converter
CMOS circuits are discussed in detail. The realization of quadrature and
image-rejection mixers in combination with poly-phase filters is presented.
Relevant design examples and limitations of CMOS transceiver are
reviewed.

Instructor: Michiel S.J. Steyaert received PhD from Katholieke

Universiteit Leuven, Heverlee, Belgium in 1987. He joined the K.U.
Leuven Laboratory ESAT in 1983 where he is Professor. His current
research interests are high-performance and high-frequency analog
integrated circuits for telecommunication systems. He received the
European Solid-State Circuits Conference Best Paper Award (1990), the
ISSCC Evening Session Award (1995, 1997), the 1999 IEEE Circuit and
Systems Society Guillemin-Cauer Award and the 1991 NFWO Alcatel-Bell-
Telephone award for innovative work in integrated circuits for
telecommunications.

FUNDAMENTAL ASPECTS OF OSCILLATOR DESIGN

(3:00P-4:30P), (5:00P-6:30P), (8:00P-9:30P)

Oscillators have traditionally lagged amplifiers in terms of well-formed

intuitions that enable the circuit designer to arrive at the optimum solution.
Simple, accurate, yet physical understanding of noise and large-signal
operation enables complete understanding of oscillators, and points the
way to state-of-the-art solutions. These concepts are illustrated on
frequently-used RF-CMOS oscillators.

Instructor: Asad A. Abidi received PhD from U.C. Berkeley in 1981. He

worked at Bell Labs, Murray Hill, NJ until 1985 when he joined UCLA
where he is Professor. He served as Editor of the IEEE Journal of Solid-
State Circuits (1992-1995). He received the TRW Award for Innovative
Teaching (1988) and the IEEE Donald G. Fink Award (1997), and is co-
recipient of the Best Paper Award at the European Solid-State Circuits
Conference (1995), the ISSCC Jack Kilby Best Student Paper Award
(1997), the ISSCC Jack Raper Award for Outstanding Technology
Directions Paper (1997), the Design Automation Conference Design
Contest Award (1998), and an IEEE Millennium Medal. He is an IEEE
Fellow.

65
 WORKSHOP ON MICROPROCESSOR DESIGN

ISSCC Microprocessor Design Workshop

Thursday, Feb 8th, 2001 - San Francisco Marriott, CA
Organizing Committee:
Chair - Vojin G. Oklobdzija , University of California
William Bowhill, Compaq, Samuel Naffziger, Hewlett-Packard,
Ian Young, Intel

This workshop on microprocessor design discusses important technical

issues and directions in design of next-generation microprocessors. It
addresses issues of high performance on a variety of levels: architecture,
circuit, power and chip-to-chip interconnection. The workshop encourages
open interchange in a closed forum. Attendance is limited and pre-
registration is required.
Topics Time
Introduction/Processor Design Challenges 8:00-8:15
Vojin G. Oklobdzija, University of California

SOI Circuits and Logic:

1) SOI Circuit Design for High-Performance CMOS 8:15-9:00
Microprocessors
T.C. Chuang, IBM T.J. Watson Research
2) Transitioning to SOI: Coping with the Challenges 9:00-9:45
and Exploiting the Advantages
Ron Preston, COMPAQ
BREAK 30 min
Chip-to-Chip Interconnect:
3) Design Challenges of High-Performance I/O 10:15-11:00
Ken Young, UCLA
4) I/O Design Styles for High-Performance
Microprocessors 11:00-1145
Hector Sanchez, Motorola
LUNCH 11:45-1:00
Power Management and Delivery:
5) Software and Hardware Schemes for Achieving 1:00-1:45
Low-Power
Takayasu Sakurai, University of Tokyo
6) Power Reducing Microarchitectural Techniques 1:45-2:30
Douglas Carmean, Intel
7) Design and Analysis of High-Performance Power-Ground
2:30-3:15
Delivery Networks
Shen Lin, Norman Chang, Hewlett Packard Labs
BREAK 30min
Future Trends in Chip Architecture:
8) Chip Multi-Processing: Architectural Issues and 3:45-4:30
Trade-Offs
Garry Lauterbach, Sun Microsystems
9) Ideas Behind NUMA Design 4:30-5:15
Pete Bannon, Compaq
10) Workshop Discussion 5:15-5:30
Vojin G. Oklobdzija, University of California

Registration information is available via the website or by using the ISSCC

printed registration form enclosed.

66
 SSCTC WORKSHOP ON RF CIRCUIT DESIGN

Workshop on RF Circuits for 2.5G and 3G Wireless Systems

IEEE Solid-State Circuits and Technology Committee Workshop
Sunday, February 4, 2001, San Francisco Marriott Hotel, San Francisco,
CA

The market demand to send high-speed data over wireless has spawned
several competing modulation standards for 2.5 Generation and 3rd
Generation systems. EDGE, IS-95B, 1XRTT, 3XRTT, WCDMA, and other
standards have been proposed. All of these standards call for envelope
varying signals and will produce significant peak to average ratios. This
will necessitate receiver and transmitter circuits that must operate with
much higher linearity than used in 2nd Generation hardware. This
workshop will address the signal differences between the proposed and
existing wireless standards, and the requirements on the RF electronics to
support them.

Topics tentatively planned for the Workshop are the following. For an
updated agenda, please refer to the SSCTC website at www.ieee.org/ssctc

EDGE Systems
Architectures for 3G
3G IC Design
Power Amp Linearization
I/Q Modulator Impairments
3G Circuit Design
Device Technologies for 3G
3G Circuits and Architectures
RF Power Measurements

Coordinator: Robert Bayruns, TROPIAN 408-579-9261,

Email [email protected]

The format of the workshop is 40-45 minute talks followed by 10 minutes of

discussion. Lunch and breaks are planned to allow participants to interact.
There is no published proceedings, and cameras are not allowed so there
can be a free flow of information. The workshop is held on the day
preceding the ISSCC and will last the entire day. Attendance is limited.
Please register via the ISSCC web registration at www.isscc.org, or
complete the enclosed ISSCC registration form and select the SSCTC
Workshop on RF Circuits.

67
 INFORMATION

CONFERENCE REGISTRATION

This year ISSCC offers a new and improved means of registering online.
This is the fastest, most convenient way to register and will give you
immediate confirmation of whether or not you have a place in the Tutorials
and Short Course sessions of your choice, and the ISSCC Microprocessor
Workshop, and SSCTC Workshop. If you register online using a credit
card, your registration is processed while you are online, and your written
confirmation can be downloaded and printed for your record keeping. To
register online, go to the ISSCC website (www.isscc.org) and click on
the registration link to SeminarSource.com.

If you register by fax or mail, you will receive a confirmation by Email or fax
if you provided that information. Registration forms received without full
payment will not be processed until payment is received at
SeminarSource.com. All payments must be made in U.S. dollars, by
credit card or check. Checks are to be made payable to
“SeminarSource.com/ISSCC.” Payments by credit card will appear on
your monthly statement as a charge from SeminarSource.com.

The deadline for receipt of Early Registration fees is December 29, 2000.
After December 29th and before January 19, 2001, registrations will be
processed only at the Late Registration rates. After January 19th, you
must pay the Onsite/highest Registration fees. Because of limited seating
capacity in the meeting rooms and hotel fire regulations, onsite registration
may be limited. Therefore, you are urged to register early to ensure your
participation in all aspects of ISSCC 2001.

For those who wish to register by fax or mail, the Advance Registration
form can be found at the center of this booklet. Please read the
explanations and instructions on the back of the form very carefully.

Full conference registration includes one copy each of the Digest of

Technical Papers, the Visual Supplement (mailed in March), one
ISSCC/JSSC DVD Archive (mailed in April) and the 2001 Conference CD-
ROM (mailed in June). Students will receive a Digest, DVD Archive and
CD-ROM. All students must present their student ID at the Conference
Registration Desk to receive the student rate. Anyone registering at the
IEEE Member rate must also provide his/her IEEE Membership number.

The Onsite and Advance Registration Desks at ISSCC 2001 will be located
in the Yerba Buena Ballroom Foyer at the San Francisco Marriott. All
participants, except presenting authors, must pick up their registration
materials at these desks as soon as they arrive at the hotel. Presenting
authors must go directly to Golden Gate C to collect their materials.

REGISTRATION HOURS:
Saturday, 2/3: 4:00 PM to 8:00 PM (Tutorial and Workshop
Attendees Only)
Sunday, 2/4: 6:30 AM to 2:00 PM (Tutorial and Workshop
Attendees Only)
2:00 PM to 8:00 PM (General Registration)
Monday, 2/5: 7:00 AM to 4:00 PM (General Registration)
Tuesday, 2/6: 8:00 AM to 4:00 PM (General Registration)
Wednesday, 2/7: 8:00 AM to 2:00 PM (General Registration)
Thursday, 2/8: 7:00 AM to 2:00 PM (Short Course and
Symposium Only)

68
 INFORMATION

NEXT ISSCC DATES AND LOCATION

ISSCC 2002 will be held on February 4-6, 2002 at the San Francisco
Marriott Hotel.

FOR FURTHER INFORMATION

Visit the website at: http://www.isscc.org

To be placed on the Conference Mailing List, please contact the
Conference Office, c/o Courtesy Associates, 2000 L Street, N.W. - Suite
710, Washington, DC 20036; Email: [email protected]; Fax: 202-
973-8722.

HOTEL RESERVATIONS

This year ISSCC participants can also make their hotel reservations
online. To do this go to the website (www.isscc.org) and click on the Hotel
Reservation link to the San Francisco Marriott. In order to receive the
special ISSCC group rates, you must enter the proper “Group Code” for
ISSCC: EEEEEEI = single @ $178; or double @ $198; EEEEEEB = triple
@ $218; EEEEEEC = quad @ $238. The dates of your reservation must
fall within the period of February 1-9, 2000. All online reservations require
the use of a credit card. Once made and confirmed, your online reservation
may only be changed or cancelled by calling (415-442-6755) or faxing
(415-442-0141) the San Francisco Marriott directly. Online reservations are
confirmed immediately, while you are online. You may download and print
your written confirmation as well.

For those who wish to make hotel reservations by fax or mail, the Hotel
Reservation Form can be found in the center of this booklet. Be sure to fill
in your correct email address and fax number if you wish to receive a
confirmation by email or fax.

Reservations must be received at the San Francisco Marriott no later

than Friday, January 5, 2001 to obtain the special ISSCC rates.

CONFERENCE PUBLICATIONS

Additional ISSCC publications can be purchased at the Conference

Registration Desk. Prices are lower for purchases collected onsite that do
not have to be shipped to the purchaser.

TECHNICAL BOOK DISPLAY

A number of technical publishers have a collection of professional books

and textbooks on display. These books are available for sale or to order
onsite. The Book Display is in the Golden Gate Hall, located one level
above the ballroom and technical sessions. The Book Display will be open
on Monday from 9:30 AM to 6:30 PM; on Tuesday from 9:30 AM to 5:30
PM; and on Wednesday from 9:30 AM to 1:00 PM.

69
 INFORMATION

ISSCC AND JSSC DIGITAL ARCHIVE DVD

In early 2001 the Solid-State Circuits Society (SSCS) releases a new

Digital Archive DVD. The Digital Archive DVD includes the complete
collection of the ISSCC Digests and Slide Supplements and the complete
collection of the Journal of Solid-State Circuits (JSSC). Features of the new
Digital Archive DVD include:

• Master Index of the 1956-2000 ISSCC and the 1966-2000

JSSC, including
• Author, title, issue and subject indexes
• Abstracts, references and citations for each article
• PDF’s of all papers of the 1956-2000 ISSCC and PDF’s of
the ISSCC Slide Supplements
• PDF’s of all papers from the 1966-2000 JSSC

Although the DVD Digital Archive will be priced at $120 for members and
$240 for non-members, the SSCS has authorized that the digital archive
DVD will be free with ISSCC registration. The DVD will be ready in the
Spring of 2001 and will be mailed to your ISSCC 2001 registration address.

IEEE AND SOCIETY MEMBERSHIP

If you have never been a member of the IEEE and would like to sample its
subscriptions and advantages, visit the Membership Desk located in the
Yerba Buena Foyer (opposite the Ballroom) at ISSCC. Great bargains are
offered during ISSCC 2001. IEEE current or previous members should
renew or add membership in a Society by telephoning 1-800-678-IEEE.

70
 COMMITTEES

EXECUTIVE COMMITTEE

Chair: John Trnka, IBM Corp., Rochester, MN

Executive Dir.: W. David Pricer, Charlotte, VT
Executive Sec.: Frank Hewlett, Jr., Sandia National Labs.,
Albuquerque, NM
Dir. of Finance: John Kennedy, Howard Hughes Medical Inst., Palo
Alto,CA
Program Chair: Glenn Gulak, Univ. of Toronto, Toronto, Ontario,
Canada
Prog. Vice Chair: Willy Sansen, K. U. Leuven, Belgium
Program Sec.: Timothy Tredwell, Eastman Kodak, Rochester, NY
Far East Chair: Hisatsune Watanabe, NEC Corp., Kawasaki, Japan
Far East Sec.: Tomohisa Arai, NEC Corp., Kawasaki, Japan
Far East Asst. Sec.: Masakazu Yamashina, NEC Corp.,
Sagamihara, Japan
European Chair: Rudy Van de Plassche, Philips Research Labs,
Eindhoven, The Netherlands
European Sec.: Jan Sevenhans, Alcatel, Antwerpen, Belgium
Short Course: Terri Fiez, Oregon State Univ., Corvallis, OR
Tutorials: Enjeti Murthi, Murthi Associates, Sunnyvale, CA
Dir. of Publications/Presentations: Laura Fujino, Univ. of Toronto,
Toronto, Ontario, Canada
Press/Awards: Kenneth Smith, Univ. of Toronto, Toronto, Ontario,
Canada
Dir. of Operations: Diane Suiters, Courtesy Associates,
Washington, DC
Digest Editor: John Wuorinen, Nordcom, Lamoine, ME

Liaison Members and Representatives:

Europe: Jan van der Spiegel, Univ. of Pennsylvania,

Philadelphia, PA
IEEE SSC Society: Gary Baldwin, U. C. Berkeley, Berkeley, CA
IEEE SSC Society: Timothy Tredwell, Eastman Kodak Co.,
Rochester, NY
IEEE Bay Area Council: Robert Tu
IEEE San Francisco Section: Charles Sayle

US PROGRAM COMMITTEE

Chair: Glenn Gulak, Univ. of Toronto, Toronto, Ontario, Canada

Vice Chair: Willy Sansen, K. U. Leuven, Belgium
Secretary: Timothy Tredwell, Eastman Kodak, Rochester, NY

Analog:
Bezhad Razavi (Chair), UCLA, Los Angeles, CA
David Allstot, Univ. of Washington, Seattle, WA
Brian Brandt, National Semiconductor, Salem, NH
Rinaldo Castello, Univ. de Pavia, Pavia, Italy
Venu Gopinathan, Broadcom Corp., Irvine, CA
Paul Hurst, Univ. of California at Davis, Davis, CA
David Johns, Univ. of Toronto, Toronto, Ontario, Canada
Akira Matsuzawa, Matsushita Electric Industrial Co., Ltd., Osaka,
Japan
Ken Poulton, Hewlett-Packard Labs, Palo Alto, CA
David Robertson, Analog Devices, Wilmington, MA
Michiel Steyaert, K. U. Leuven, Belgium

71
 COMMITTEES

Axel Thonsen, Cirrus Logic, Austin, TX

* Scott Willingham, Silicon Labs., Austin, TX

Digital:
Ian Young (Chair), Intel Corporation, Hillsboro, OR
Krste Asanovic, MIT Computer Science Lab, Cambridge, MA
* William Athas, Univ. of Southern California, Marina del Ray, CA
David Bearden, Motorola, Inc., Austin, TX
Kerry Bernstein, IBM Microelectronics, Essex Junction, VT
William Bowhill, Compaq Computer Corp., Shrewsbury, MA
Glenn Giacalone, C-Port Corp., North Andover, MA
David Greenhill, Sun Microsystems, Palo Alto, CA
Michel Harrand, STMicroelectronics, Crolles, France
Paul Landman, Texas Instruments, Dallas, TX
John Maneatis, JGM Enterprises, Redwood City, CA
Samuel Naffziger, Hewlett-Packard, Fort Collins, CO
Vojin Oklobdzjia, Integration Corp., Berkeley, CA
Andre Picco, STMicroelectronics, Grenoble, France
Simon Segars, Arm Ltd., Cambridge, Great Britain
Alisa Scherer, Advanced Micro Devices, Sunnyvale, CA
Stefanos Siridopoulos, Rambus Inc., Mountain View, CA
Masakazu Yamashina, NEC Corp., Sagamihara, Japan

Imagers, Displays, and MEMS:

Dennis Polla (Chair), University of Minnesota, Minneapolis, MN
Alantunde Akinwande, Mass. Instit. of Technology, Cambridge, MA
Philip Alvelda, The Microdisplay Corp., San Pablo, CA
Abbas El Gamal, Stanford Univ., Stanford, CA
Ralph Etienne-Cummings, Johns Hopkins Univ., Baltimore, MD
Yoshiaki Hagiwara, Sony Corp. Semicon. Co., Tokyo, Japan
Michael Judy, Analog Devices, Cambridge, MA
Jack Judy, UCLA, Los Angeles, CA
Fritz Kub, Naval Research Lab, Washington, DC
Daniel McGrath, Atmel Corp., Andover, MA
* Khalil Najafi, Univ. of Michigan, Ann Arbor, MI
Kai Schleupen, IBM, Yorktown Heights, NY
Charles Stancampiano, Eastman Kodak Company, Rochester, NY
Albert Theuwissen, Philips Semiconductor Image Sensors,
Eindhoven, The Netherlands
H.-S. Philip Wong, IBM T. J. Watson Res. Ctr., Yorktown Heights,
NY
Woodward Yang, Harvard Univ., Cambridge, MA

Memory:
Bruce Bateman (Chair), Microunity Systems Eng., Sunnyvale, CA
Mark Bauer, Intel Corp., Folsom, CA
Martin Brox, Infineon Techn., Munchen, Germany
Jeffrey Dreibelbis, IBM, Essex Jct., VT
Tae-Sung Jung, Samsung Electronics, Kyungki, Korea
Takayuki Kawahara, Hitachi Ltd., Tokyo, Japan
* Bill Martino, Motorola, Austin, TX
Junichi Miyamoto, Toshiba Corp., Yokohama, Japan
Roger Norwood, Micron Technology, Richardson, TX
Ashish Pancholy, Cypress Semiconductor, San Jose, CA
Jagdish Pathak, Sub Micron Circuits Inc., San Jose, CA
George Smarandoiu, Atmel Corp., San Jose, CA
Don Stark, Rambus Inc., Mountain View, CA
Ban-Pak Wong, Sun Microsystems, Palo Alto, CA

72
 COMMITTEES

Signal Processing:
Anantha Chandrakasan (Chair), MIT, Cambridge, MA
* Bill Bidermann, S3 Inc., Santa Clara, CA
Ivo Bolsens, IMEC, Leuven, Belgium
Frederic Boutaud, Analog Devices, Wilmington, MA
Stephen Fischer, Intel Corp., Folsom, CA
Wai Lee, Texas Instruments, Dallas, TX
Stephen Molloy, Luxxon Corp., San Jose, CA
Nersi Nazari, Marvell Semiconductor Inc., Sunnyvale, CA
Chris Nicol, Bell Labs, Lucent Technologies, North Ryde, Australia
Narendra Rao, Datapath Systems, Inc., Los Gatos, CA
Engel Roza, Philips Research Labs, Eindhoven, The Netherlands
Bernard Shung, Allayer Technologies Corp., San Jose, CA
Lars Thon, T-Span Systems Corp., Palo Alto, CA
Ingrid Verbauwhede, Univ. of California, Los Angeles, CA
Takao Yamazaki, Sony Electronics, San Jose, CA

Technology Directions Steering Committee:

John Cressler (Chair), Auburn Univ., Auburn, AL
Akira Kanuma, Toshiba Corp., Kawasaki, Japan
Timothy Tredwell, Eastman Kodak, Rochester, NY
Jan Van der Spiegel, Univ. of Pennsylvania, Philadelphia, PA

Wireless & RF Communications:

Robert Bayruns (Chair), Tropian, Cupertino, CA
William Camp, Ericsson Inc., Research Triangle Park, NC
Charles Chien, Rockwell Science Center, Thousand Oaks, CA
Paul Davis, Bell Labs, Lucent Technologies, Reading, PA
Akira Kanuma, Toshiba Corp., Kawasaki, Japan
Thomas Lee, Stanford Univ., Stanford, CA
* John Long, Univ. of Toronto, Toronto, Ontario, Canada
Gitty Nasserbakht, Proxim, Inc., Sunnyvale, CA
Trudy Stetzler, Texas Instruments, Stafford, TX
Bud Taddiken, Nicrotune, Plano, TX
Rudy Van de Plassche, Broadcom Corp., Bunnik, The Netherlands

Wireline Communications:
Russell Apfel (Chair), Consultant, Austin, TX
Cormac Conroy, LSI Logic, San Jose, CA
Roger Minear, Lucent Technologies, Reading, PA
MaryJo Nettles, AMCC, San Diego, CA
Jan Sevenhans, Alcatel, Antwerp, Belgium
* Mehmet Soyuer, IBM Yorktown Heights, NY
Hirotaka Tamura, Fujitsu Labs Ltd., Kawasaki, Japan
Loke Tan, Broadcom Corp., Irvine, CA
Tyson Tuttle, Silicon Labs Inc., Austin, Tx
Rick Walker, Agilent Technologies, Palo Alto, CA

73
 COMMITTEES

EUROPEAN PROGRAM COMMITTEE

Chair: Rudy Van de Plassche, Broadcom Corp., Bunnik,

The Netherlands
Secretary: Jan Sevenhans, Alcatel, Antwerpen, Belgium

Members:
Martin Borx, Infineon Techn. Corp., Munchen, Germany
Rinaldo Castello, University of Pavia, Pavia, Italy
Franz Dielacher, Siemens Entwicklungszentrum, Villach, Austria
Pietro Erratico, STMicroelectronics, Cornaredo, Milano, Italy
Michel Harrand, STMicroelectronics, Crolles, France
* Qiuting Huang, ETH, Zurich, Switzerland
Rudolf Koch, Infineon Technologies, Munchen, Germany
Andre Picco, STMicroelectronics, Grenoble, France
Christian Piguet, CSEM SA, Neuchâtel, Switzerland
Wolfgang Pribyl, Austria Microsysteme International AG,
Unterprenstatten, Austria
William Redman-White, Philips Semiconductors, Southampton, U.K.
Engel Roza, Philips Research Labs, Eindhoven, The Netherlands
Willy Sansen, K. U. Leuven, Belgium
Patrice Senn, CNET, Meylan, France
Ted Smith, XEMICS SA, Neuchâtel, Switzerland
Michel Steyaert, K. U. Leuven, Belgium
Christer Svensson, Linköping Univ, Linköping, Sweden
Hannu Tenhunen, Electrum, Kista, Sweden
Albert Theuwissen, Philips Semiconductors Image Sensors,
Eindhoven, The Netherlands
Michael Tuthill, Analog Devices Inc., Limerick, Ireland
Jan van der Spiegel, Univ. of Pennsylvania, Philadelphia, PA
* Werner Weber, Infineon Technologies, Munich, Germany

74
 COMMITTEES

FAR EAST PROGRAM COMMITTEE

Chair: Hisatsune Watanabe, NEC Corp., Kawasaki, Japan

Secretary: Tomohisa Arai, NEC Corp., Kawasaki, Japan, Japan
Asst. Sec.: Masakazu Yamashina, NEC Corp., Sagamihara, Japan
Members:
Kunihiro Asada, Univ. of Tokyo, Tokyo, Japan
Jinyong Chung, Hundai Electronics Industries Co., Inchon, Korea
Yoshiaki Hagiwara, Sony Corp., Tokyo, Japan
Takahiro Hanyu, Tohoku Univ., Sendai, Japan
Hideto Hidaka, Mitsubishi Electric Corp., Hyogo, Japan
Marwan Jabri, Univ. of Sydney, Sydney, Australia
Tae-Sung Jung, Samsung Electronics, Kyungki, Korea
Yuichi Kado, NTT, Kanagawa, Japan
Akira Kanuma, Toshiba Corp., Kawasaki, Japan
Masayuki Katakura, Sony Corp., Kanagawa, Japan
* Takayuki Kawahara, Hitachi Ltd., Tokyo, Japan
Shigeo Kuninobu, Matsushita Electric, Kyoto, Japan
Bang Won Lee, @Lab Inc., Kyungki, Korea
Nicky Lu, Etron Technology Inc., Hsinchu, TAIWAN, ROC
Akira Matsuzawa, Matsushita Electric Industrial Co. Ltd., Osaka,
Japan
Junichi Miyamoto, Toshiba Corp., Yokohama, Japan
Masayuki Miyamoto, Sharp Corp., Nara, Japan
Tadashi Nakagawa, Electrotechnical Laboratory, Tsukuba, Japan
Kazuyuki Nakamura, NEC Corp., Kanagawa, Japan
Yukihito Oowaki, Toshiba Corp., Yokohama, Japan
Kaoru Saito, OKI Electric Industry Co., Ltd., Tokyo, Japan
* Takayasu Sakurai, Univ. of Tokyo, Tokyo, Japan
Hirotaka Tamura, Fujitsu Labs, Ltd., Kawaski, Japan
Yangyuan Wang, Peking Univ., Bejing, P.R. China

Liaison:
Naohiko Irie, Hitachi America, Ltd., San Jose, CA
Ed Katsuta, NEC Electronics, Inc., Santa Clara, CA
Masaki Kumanoya, Mitsubishi Elec. America, Inc., Sunnyvale, CA
Masanori Kuwahara, Toshiba Corp., Kanagawa, Japan
Junji Ogawa, Fujitsu Labs of America Ltd., Sunnyvale, CA
Tetsuzo Ueda, Panasonic Semiconductor Co., Cupertino, CA
Takao Yamazaki, Sony Electronics, San Jose, CA

* Committee Representative on Technology Directions Subcommittee

75
 CONFERENCE SPACE LAYOUT

The Conference Book Display and Social Hour will be held in

Golden Gate Hall. The layout appears below:

76
 CONFERENCE SPACE LAYOUT

All Conference Technical Paper Sessions are in the Yerba Buena Ballroom
at the San Francisco Marriott Hotel. The layout appears below.

77
 NOTES

78
79
ISSCC 2001 ADVANCE PROGRAM