Cortex-M3

Processor core system

Interrupts Trace

Instruction bus

Data bus

Debug
Optional

FIGURE 2.1

A Simplified View of the Cortex-M3.

In addition, optional components provide debugging features, such as instruction trace, and various
types of debugging interfaces.

REGISTERS

The Cortex-M3 processor has registers R0 through R15 (see Figure 2.2). R13 (the stack pointer) is
banked, with only one copy of the R13 visible at a time.

R0–R12: General-Purpose Registers

R0–R12 are 32-bit general-purpose registers for data operations. Some 16-bit Thumb® instructions
can only access a subset of these registers (low registers, R0–R7).

R13: Stack Pointers

The Cortex-M3 contains two stack pointers (R13). They are banked so that only one is visible at a
time. The two stack pointers are as follows:

Main Stack Pointer (MSP): The default stack pointer, used by the operating system (OS) kernel and
exception handlers

Process Stack Pointer (PSP): Used by user application code

The lowest 2 bits of the stack pointers are always 0, which means they are always word aligned.
Name

Functions (and banked registers) General-purpose register General-purpose register General-

General-purpose register General-purpose register General-purpose register General-purpose

Low registers

High registers
FIGURE 2.2

Registers in the Cortex-M3.

Main Stack Pointer (MSP), Process Stack Pointer (PSP) Link Register (LR)

Program Counter (PC)

R14: The Link Register

When a subroutine is called, the return address is stored in the link register.

R15: The Program Counter

The program counter is the current program address. This register can be written to control the
program flow.

Special Registers

The Cortex-M3 processor also has a number of special registers (see Figure 2.3). They are as follows:

Program Status registers (PSRs)

Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI)

Control register (CONTROL)

These registers have special functions and can be accessed only by special instructions. They cannot

be used for normal data processing (see Table 2.1).

xPSR

PRIMASK

FAULTMASK

BASEPRI

CONTROL

FIGURE 2.3

Special Registers in the Cortex-M3.

Functions

Program status registers

Interrupt mask registers

Control register
Special registers

Table 2.1 Special Registers and Their Functions

Register Function

xPSR Provide arithmetic and logic processing flags (zero flag and carry flag), execution status, and
current executing interrupt number

PRIMASK Disable all interrupts except the nonmaskable interrupt (NMI) and hard fault

FAULTMASK Disable all interrupts except the NMI

BASEPRI Disable all interrupts of specific priority level or lower priority level

CONTROL Define privileged status and stack pointer selection

For more information on these registers, see Chapter 3.

OPERATION MODES

The Cortex-M3 processor has two modes and two privilege levels. The operation modes (thread
mode and handler mode) determine whether the processor is running a normal program or running
an excep- tion handler like an interrupt handler or system exception handler (see Figure 2.4). The
privilege levels (privileged level and user level) provide a mechanism for safeguarding memory
accesses to critical regions as well as providing a basic security model.

When the processor is running a main program (thread mode), it can be either in a privileged state
or a user state, but exception handlers can only be in a privileged state. When the processor exits
reset, it is in thread mode, with privileged access rights. In the privileged state, a program has access
to all memory ranges (except when prohibited by MPU settings) and can use all supported
instructions.
Software in the privileged access level can switch the program into the user access level using the
control register. When an exception takes place, the processor will always switch back to the
privileged state and return to the previous state when exiting the exception handler. A user program
cannot change back to the privileged state by writing to the control register (see Figure 2.5). It has to
go through an exception handler that programs the control register to switch the processor back
into the privileged access level when returning to thread mode.

The separation of privilege and user levels improves system reliability by preventing system config-
uration registers from being accessed or changed by some untrusted programs. If an MPU is
available,

FIGURE 2.4

When running an exception handler

When not running an exception handler (e.g., main program)

Privileged
User

Operation Modes and Privilege Levels in Cortex-M3.

Start (reset)

Exception exit

Exception

Privileged thread

Privileged handler

Exception exit
Exception

Program of CONTROL

register

User thread

FIGURE 2.5

Allowed Operation Mode Transitions.

it can be used in conjunction with privilege levels to protect critical memory locations, such as pro-
grams and data for OSs.

For example, with privileged accesses, usually used by the OS kernel, all memory locations can be
accessed (unless prohibited by MPU setup). When the OS launches a user application, it is likely to
be exe- cuted in the user access level to protect the system from failing due to a crash of untrusted
user programs.

THE BUILT-IN NESTED VECTORED INTERRUPT CONTROLLER

The Cortex-M3 processor includes an interrupt controller called the Nested Vectored Interrupt
Control- ler (NVIC). It is closely coupled to the processor core and provides a number of features as
follows:

Nested interrupt support

Vectored interrupt support

Dynamic priority changes support

Reduction of interrupt latency

Nested Interrupt Support

The NVIC provides nested interrupt support. All the external interrupts and most of the system
excep- tions can be programmed to different priority levels. When an interrupt occurs, the NVIC
compares