RF7411

3V WCDMA BAND 1 LINEAR PA MODULE

Package Style: Module, 10-Pin, 3mm x 3mm x 1.0mm

: NDA REQUIRED

VBAT 1
Features 10 VCC

 HSDPA/HSUPA/HSPA+/ LTE RF IN
2 9 RF OUT
 High Efficiency WCDMA
Operation : 42.5% at POUT = NC
3 8 CPL IN
+28dBm Bias Control &
Low Voltage Positive Bias VMODE PA/V MODE Enable
 4 7 GND
Supply (3.0V to 4.2V)
Internal Voltage Regulator - VEN
 5 6 CPL OUT
No External (VREF) Required
 Two Mode Power/Gain Stages
with Digital Control Interface
 Integrated Power Coupler
Functional Block Diagram
 Integrated Blocking and
Decoupling Capacitors
Product Description
Applications The RF7411 is a high-power, high-efficiency, linear power amplifier
designed for use as the final RF amplifier in 3V, 50 WCDMA mobile cellu-
 WCDMA/HSPA+/LTE Wireless lar equipment and spread-spectrum systems. This PA is developed for
Data Cards
UMTS Band 1 which operates in the 1920MHz to 1980MHz frequency
 WCDMA/HSPA+/LTE band. The RF7411 has a digital control pin which enables a low power
Handsets mode to reduce amplifier gain at lower power levels. The part also has an
integrated directional coupler which eliminates the need for an external
discrete coupler at the output. The RF7411 (Band 1) meets the spectral
linearity requirements of High Speed Downlink Packet Access (HSDPA),
High Speed Uplink Packet Access (HSUPA), and Long Term Evolution (LTE)
data transmission. The RF7411 is assembled in a 10-pin, 3mm x 3mm
module.

Ordering Information
RF7411 3V WCDMA Band 1 Linear PA Module
RF7411PCBA-410 Fully Assembled Evaluation Board

Optimum Technology Matching® Applied

GaAs HBT SiGe BiCMOS GaAs pHEMT GaN HEMT
GaAs MESFET Si BiCMOS Si CMOS BiFET HBT
 InGaP HBT SiGe HBT Si BJT LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.

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RF7411
Absolute Maximum Ratings
Parameter Rating Unit Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
Supply Voltage in Standby Mode 6.0 V cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
Supply Voltage in Idle Mode 6.0 V mance or functional operation of the device under Absolute Maximum Rating condi-
tions is not implied.
Supply Voltage in Operating Mode, 6.0 V The information in this publication is believed to be accurate and reliable. However, no
50 Load responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
Supply Voltage, VBAT 6.0 V license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
Control Voltage, V MODE 3.7 V
Control Voltage, VEN 3.7 V RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
RF - Input Power +10 dBm solder.

RF - Output Power +30 dBm

Operating Ambient Temperature -30 to +110 °C
Storage Temperature -55 to +150 °C

Specification
Parameter Unit Condition
Min. Typ. Max.
Recommended Operating
Conditions
Operating Frequency Range 1920 1980 MHz
VBAT +3.0 +3.2 +4.2 V
VCC +3.01 +3.2 +4.2 V
VCC (used with DC-DC) 0.5 +4.2 V PA used with DC-DC converter to reduce current
drain at back-off and lower output powers
VEN 0 0.5 V PA disabled.
1.35 1.80 3.10 V PA enabled.
VMODE 0 0.5 V Logic “low”.
1.35 1.80 3.10 V Logic “high”.
POUT
Maximum Linear Output (HPM) 28.01,2 dBm High Power Mode (HPM)

Maximum Linear Output (LPM) 161,2 dBm Low Power Mode (LPM)
Ambient Temperature -20 +25 +85 °C
Notes:
1
For operation at VCC = +3.0V, derate POUT by 0.5dB.
2
POUT is specified for 3GPP (Voice) modulation. For HSDPA and HSPA+ operation, derate POUT by 2dB:
HSDPA Configuration: c12, d15, hs24
HSPA+ Configuration: 3GPP Rel7 Subtest 1

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 RF7411
Specification
Parameter Unit Condition
Min. Typ. Max.
T = +25C, VCC = VBAT = +3.2V, VEN = +1.8V, 50
Electrical Specifications system, WCDMA Rel 99 Modulation unless other-
wise specified.
Gain 28 dB HPM, POUT = 28.0dBm
15.5 dB LPM, POUT16.0dBm
ACLR - 5MHz Offset -40 -36 dBc HPM, POUT = 28.0dBm
-44 -38 dBc LPM, POUT = 16.0dBm
ACLR - 10MHz Offset -52 -48 dBc HPM, POUT = 28.0dBm
-60 -48 dBc LPM, POUT = 16.0dBm
PAE 39 42.5 % HPM, POUT = 28.0dBm
10 % LPM, POUT = 16.0dBm
Current Drain 435 mA HPM, POUT = 28.0dBm
116 mA LPM, POUT = 16.0dBm
Quiescent Current 50 mA HPM, DC only
Enable Current 0.03 mA Source or sink current. VEN = 1.8V.
Mode Current (IMODE) 0.01 mA Source or sink current. VMODE = 1.8V.
Leakage Current 2.1 10.0 A DC only. VCC = VBAT = 4.2V, VEN = VMODE = 0.5V.
Noise Power in Receive Band -137 dBm/Hz All power modes, measured at duplex offset fre-
quency (FTX + 190MHz). Rx: 2110MHz to
2170MHz, POUT28.0dBm
Input Impedance 1.8:1 VSWR No ext. matching, POUT28dBm, all modes.
Harmonic, 2FO -20 -7 dBm POUT28.0dBm, all power modes.
Harmonic, 3FO -23 -14 dBm POUT28.0dBm, all power modes.
Spurious Output Level -60 dBc All spurious, POUT28dBm, all conditions, load
VSWR6:1, all phase angles.
Insertion Phase Shift -30 9.8 +30 ° Phase shift at 16dBm when switching from HPM
to LPM.
DC Enable Time 10 S DC only. Time from VEN = high to stable idle cur-
rent (90% of steady state value).
RF Rise/Fall Time 6 S POUT28.0dBm, all modes. 90% of target, DC set-
tled prior to RF.
Ruggedness 10:1 VSWR HPM, POUT = 28.0dBm, all phases.
Coupling Factor -20 dB POUT28.0dBm, all modes.
Daisy Chain Insertion Loss 0.25 dB CPL_IN to CPL_OUT port, VEN = 0.5V
Coupling Directivity 20 dB

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RF7411
Pin Function Description
1 VBAT Supply voltage for bias circuitry.
2 RF IN RF input internally matched to 50 and DC blocked. The RF input matching circuit has a shunt inductor to
ground which would short any DC voltage placed on this pin.
3 NC No connection.
4 VMODE Digital control input for power mode selection (see Operating Modes truth table).
5 VEN Digital control input for PA enable and disable (see Operating Modes truth table).
6 CPL_OUT Coupler output.
7 GND This pin must be grounded.
8 CPL_IN Coupler input used for cascading couplers in series. Terminate this pin with a 50 resistor if not connected to
another coupler.
9 RF OUT RF output internally matched to 50and DC blocked.
10 VCC Supply voltage for the first and second stage amplifiers, which can be connected to battery supply or output of
DC-DC converter.
Pkg GND Ground connection. The package backside should be soldered to a topside ground pad connecting to the PCB
ground plane with multiple ground vias. The pad should have a low thermal resistance and low electrical imped-
Base ance to the ground plane.

Operating Mode Truth Table

VEN VMODE VBAT VCC Conditions/Comments
Low Low 3.0V to 4.2V 3.0V to 4.2V Power down mode
Low X 3.0V to 4.2V 3.0V to 4.2V Standby Mode
High Low 3.0V to 4.2V 3.0V to 4.2V High power mode
High High 3.0V to 4.2V 3.0V to 4.2V Low power mode

Package Drawing

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 RF7411
Application Schematic
VBAT VCC

1 10
AMP
4.7uF 10 nF (3) 4.7uF (2)
RF IN 2 9 RF OUT

VMODE1 3 Bias Control 8

& PA/VMODE
Enable 50 
 
VMODE0 4 7

VEN 5 6
CPL OUT

NOTES:
(1). The 50  resistor should be removed if pin 8 is connected to another coupler for daisy chaining multiple couplers.
(2). This capacitance value can be reduced for multi-PA with DC to DC converter applications where a total maximum
capacitive load is required to be met. Keeping at least a 1uF capacitor close to the PA Vcc pin is recommended.
(3). A capacitor of at least 10 nF should be placed closed to the PA VCC pin (pin10) for optimum decoupling.

Evaluation Board Schematic

VCC1 VCC2

1 10
C5 C7 AMP C8 C6 C4
4.7uF 10nF J1 J2 10nF 4.7uF 22uF
2 9
RF IN RF OUT

VMODE1 3 Bias Control 8

C9 & PA/VMODE R2
10nF VMODE0 4 Enable 7 51 
C10
10nF VEN 5 6
J3
P1_1 C11 CPL OUT
P1_2 VEN 10nF
P1_3 VMODE0
P1_4 VMODE1
P1_5 VCC1
NOTES:
P1_6
P1_7 VCC2 (1). VCC2S is a sense line to be used if the test power supply has voltage sensing
P1_8 VCC2S (1) capability. This compensates for any resistive voltage drop that occurs between
P1_9 the power supply and the PA and thus ensures that the voltage at the PA is set as
expected.

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RF7411
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch
to 8inch gold over 180inch nickel.

PCB Land Pattern Recommendation

PCB land patterns for RFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown
has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate
lead and package tolerances. Since surface mount processes vary from company to company, careful process development is
recommended.

PCB Metal Land Pattern

Figure 1. PCB Metal Land Pattern (Top View)

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PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB
metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The
center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be
provided in the master data or requested from the PCB fabrication supplier.

Figure 2. PCB Solder Mask Pattern (Top View)

Thermal Pad and Via Design

The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device.

Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing
strategies.

The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a
0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the
quantity of vias be increased by a 4:1 ratio to achieve similar results.

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