RFMD2080

RFMD2080
45MHz TO 2700MHz IQ MODULATOR WITH
SYNTHESIZER/VCO AND BASEBAND INTERFACE
Package: QFN, 32-Pin, 5mm x 5mm

Features
 RF Output Frequency Range
45MHz to 2700MHz
 Fractional-N Synthesizer with Phase
Synth
Very Low Spurious Levels det .
 Typical Step Size 1.5Hz
 Fully Integrated Wideband VCOs
and LO Buffers
Ref.
 Integrated Phase Noise divider
<0.2° rms at 1GHz
 Integrated Baseband
Amplification Stage with Variable
Gain and Filtering
Functional Block Diagram
 Tunable Baseband Filters Input
3dB Bandwidth from 1.5MHz to Product Description
10MHz
The RFMD2080 is a low power, highly integrated, IQ modulator with integrated fractional-N syn-
 -45dBc Unadjusted Carrier thesizer and voltage controlled oscillator (VCO). The RFMD2080 can generate output frequen-
Suppression cies of between 45MHz and 2700MHz, making it suitable for a wide range of applications.
 -40dBc Unadjusted Sideband The fractional-N synthesizer takes advantage of an advanced sigma-delta architecture that
Suppression delivers ultra-fine step sizes and low spurious products. The synthesizer/VCO combined with an
external loop filter allows the user to generate an oscillator signal covering 90MHz to 5400MHz.
 Very Low Noise Floor The signal is buffered and routed to a high accuracy quadrature divider (/2) that drives the bal-
-150dBm/Hz Typical anced I and Q mixers. The output of the mixers are summed and applied to a differential RF out-
put stage. The device also features a differential input for an external VCO or LO source.
 Output P1dB +4dBm
 Output IP3 +18dBm The baseband I and Q stages are highly integrated; featuring variable gain and filtering as well
as generation of DC offset voltages. The programmable DC offsets enable improved carrier sup-
 3.0V to 3.3V Power Supply pression. The baseband input 3dB bandwidth can be tuned from 1.5MHz to 10MHz, and the
total gain control range is 38dB with 2dB resolution.
 155mA Typical Current
Consumption Device programming is achieved via a simple 3-wire serial interface. In addition, a unique pro-
gramming mode allows up to four devices to be controlled from a common serial bus. This elim-
 Serial Programming Interface inates the need for separate chip-select control lines between each device and the host
controller. Up to six general purpose outputs are provided, which can be used to access internal
Applications signals (the LOCK signal, for example) or to control front end components. The device is opti-
mized for low power operation, consuming typically only 155mA from a 3V supply.
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RFMD2080
Absolute Maximum Ratings
Parameter Rating Unit Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
Supply Voltage (VDD) -0.5 to +3.6 V cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
Input Voltage (VIN), any pin -0.3 to VDD+0.3 V tions is not implied.
The information in this publication is believed to be accurate and reliable. However, no
LO Input Power +15 dBm responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
Operating Temperature Range -40 to +85 °C license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
Storage Temperature Range -65 to +150 °C cation circuitry and specifications at any time without prior notice.
RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
solder.

Specification
Parameter Unit Condition
Min. Typ. Max.
ESD Requirements
Human Body Model 2000 V DC Pins
1500 V All Pins
Charge Device Model 1000 V All Pins
Operating Conditions
Supply Voltage (VDD) 3.0 3.3 V
Temperature -40 +85 °C
Logic Inputs/Outputs
(VDD = Supply to DIG_VDD pin)
Input Low voltage -0.3 +0.5 V
Input High voltage VDD / 1.5 VDD V
Input Low current -10 +10 A Input = 0V
Input High current -10 +10 A Input = VDD
Output Low voltage 0 0.2*VDD V
Output High voltage 0.8*VDD VDD V
Load Resistance 10 K
Load Capacitance 20 pF
GPO Drive Capability
Sink Current 20 mA At VOL = +0.6V
Source Current 20 mA At VOH = +2.4V
Output Impedance 25 
Static
Supply Current (IDD) 155 mA
Standby 2 mA Reference Oscillator and Bandgap Only
Power Down Current 300 A ENBL = 0 and REF_STBY = 0

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 RFMD2080
Specification
Parameter Unit Condition
Min. Typ. Max.
Modulator (Output driving 4:1 balun)
I and Q Input Max 3dB Bandwidth 10 MHz Filter Setting rctune = 0
I and Q Input Min 3dB Bandwidth 1.5 MHz Filter Setting rctune = 63
I and Q Input Voltage 1 VP-P Differential with 0.5V to 1.5V Input DC Bias
Output Power -3 dBm
Output Noise Floor -150 dBm/Hz At 10MHz Offset
Output IP3 +18 dBm
Output P1dB +4 dBm
Carrier Suppression -45 dBc Unadjusted
Carrier Suppression -55 dBc DC Bias Offset DACs Adjusted
Sideband Suppression -40 dBc Unadjusted
Output Port Center Frequency Range 45 2700 MHz
Reference Oscillator
External Reference Frequency 10 104 MHz
Reference Divider Ratio 1 7
External Reference Input Level 500 800 1500 mVP-P AC-coupled
Synthesizer
(PLL closed loop, 52MHz reference)
Synthesizer Output frequency 90 5400 MHz
Phase Detector Frequency 52 MHz
Phase Noise, LO=1GHz -108 dBc/Hz 10kHz Offset
-108 dBc/Hz 100kHz Offset
-135 dBc/Hz 1MHz Offset
0.19 Deg RMS Integrated from 1KHz to 40MHz
Phase Noise, LO=2GHz -102 dBc/Hz 10kHz Offset
-102 dBc/Hz 100kHz Offset
-130 dBc/Hz 1MHz Offset
0.32 Deg RMS Integrated from 1KHz to 40MHz
Normalized phase noise floor -214 dBc/Hz Measured at 20kHz to 30kHz Offset
Voltage Controlled Oscillator
Open Loop Phase Noise at 1MHz Offset
2.5GHz LO Frequency -134 dBc/Hz VCO3, LO Divide by 2
2.0GHz LO Frequency -135 dBc/Hz VCO2, LO Divide by 2
1.5GHz LO Frequency -136 dBc/Hz VCO1, LO Divide by 2
Open loop phase noise at 10MHz offset
2.5GHz LO Frequency -149 dBc/Hz VCO3, LO Divide by 2
2.0GHz LO Frequency -150 dBc/Hz VCO2, LO Divide by 2
1.5GHz LO Frequency -151 dBc/Hz VCO1, LO Divide by 2
External LO Input
LO Input Frequency Range 90 5400 MHz
External LO Input Level 0 dBm Driven from 50 source via a 1:1 balun

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RFMD2080
Pin Names and Descriptions
Pin Name Description
1 ENBL/GPO5 Device Enable pin (see note 1 and 2).
2 EXT_LO External local oscillator input. Use AC coupling capacitor.
3 EXT_LO_DEC Decoupling pin for external local oscillator. Use AC coupling capacitor.
4 REXT External bandgap bias resistor (see note 3).
5 ANA_VDD1 Analog supply. Use good RF decoupling.
6 LFILT1 Phase detector output. Low-frequency noise-sensitive node.
7 LFILT2 Loop filter op-amp output. Low-frequency noise-sensitive node.
8 LFILT3 VCO control input. Low-frequency noise-sensitive node.
9 MODE/GPO6 Mode select pin (see notes 1 and 2).
10 REF_IN Reference input. Use AC coupling capacitor.
11 NC
12 TM Connect to ground.
13 RF_OUT_N Differential output (see note 5).
14 RF_OUT_P Differential output (see note 5).
15 GPO1/ADD1 General purpose output / MultiSlice address bit.
16 GPO2/ADD2 General purpose output / MultiSlice address bit.
17 DIG_VDD Digital supply. Should be decoupled as close to the pin as possible.
18 MOD_Q_N Modulator Q differential input (see note 4).
19 MOD_Q_P Modulator Q differential input (see note 4).
20 NC
21 NC
22 MOD_I_N Modulator I differential input (see note 4).
23 MOD_I_P Modulator I differential input (see note 4).
24 ANA_VDD2 Analog supply. Use good RF decoupling.
25 GPO3 General purpose output
26 GPO4/LD/DO General purpose output / Lock detect output / serial data out.
27 NC
28 NC
29 RESETX Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.
30 ENX Serial interface select (active low) (See note 1).
31 SCLK Serial interface clock (See note 1).
32 SDATA Serial interface data (See note 1).
Exposed Paddles Ground reference, should be connected to PCB ground through a low impedance path.

Notes:
1. An RC low pass filter may be used on this line to reduce digital noise.
2. If the device is under software control this input can be configured as a general purpose output (GPO).
3. Connect a 51K resistor from this pin to ground. This pin is sensitive to low frequency noise injection.
4. DC bias voltage and modulation should be applied to this pin.
5. This pin must be connected to ANA_VDD2 using an RF choke or center tapped transformer (see application schematic).

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 RFMD2080
Theory of Operation
The RFMD2080 is a wideband IQ modulator with integrated fractional-N synthesizer and a low noise VCO core. It features a
high accuracy LO quadrature divider followed by buffer circuits which drive the I and Q mixers of the modulator with the quadra-
ture LO signals. The RFMD2080 has an integrated voltage reference and low drop out regulators supplying critical circuit
blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control are achieved through a
mixture of hardware and software controls. All on-chip registers are programmed through a simple three-wire serial interface.

VCO
The VCO core in the RFMD2080 consists of three VCOs which, in conjunction with the integrated LO dividers of /1 to /32, cover
the frequency range of 90MHz to 5400MHz. The modulator quadrature divider provides a further fixed divide by two to give the
center frequency range at the modulator output of 45MHz to 2700MHz.

Each VCO has 128 overlapping bands which are used to achieve low VCO gain and optimal phase noise performance across
the whole tuning range. The chip automatically selects the correct VCO (VCO auto-select) and the correct VCO band (VCO
coarse tuning) to generate the desired LO frequency based on the values programmed into the PLL1 and PLL2 registers banks.

The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is
programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the
band selection process fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is
oscillating at approximately the correct frequency. The output of this band selection, CT_CAL, is made available in the read-
back register. If this was unsuccessful it will be indicated by the CT_FAILED flag also available in the read-back register. A value
between 1 and 126 indicates a successful calibration, the actual value being dependent on the desired frequency as well as
process variation for a particular device.

The band select process will center the VCO tuning voltage at about 0.8V, compensating for manufacturing tolerances and pro-
cess variation as well as environmental factors including temperature. In applications where the device is left enabled at the
same LO frequency for some time it is recommended that automatic band selection be performed for every 30°C change in
temperature. This assumes an active loop filter.

The RFMD2080 features a differential LO input to allow the mixer to be driven from an external LO source. The fractional-N PLL
can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in some applications.
This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.

Fractional-N PLL
The RFMD2080 contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL
includes automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable
loop response and phase noise performance. As well as the VCO auto-select and coarse tuning, there is a loop filter calibration
mechanism which can be enabled if required. This operates by adjusting the charge pump current to maintain loop bandwidth.
This can be useful for applications where the LO is tuned over a wide frequency range.

The PLL has been designed to use a reference frequency of between 10MHz and 104MHz from an external source, which is
typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and
should be programmed to limit the frequency at the phase detector to a maximum of 52MHz.

Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. The active register bank is selected by the state of the MODE pin, low for PLL1 and high for PLL2.

The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters
the N divider, which is a fractional divider containing a dual-modulus prescalar and a digitally spur-compensated fractional
sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is shaped and
appears as fractional noise at frequency offsets above 100KHz which will be attenuated by the loop filter. An external loop filter
is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time, for example.

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RFMD2080
The synthesizer step size is typically 1.5Hz when using a 26MHz reference frequency. The exact step size for any reference and
LO frequency can be calculated using the following formula:

(FREF * P) / (R * 224 * LO_DIV*2)

Where FREF is the reference frequency, R is the reference division ratio, P is the prescalar division ratio, and LO_DIV is the LO
divider value.

Pin 26 (GPO4) can be configured as a lock detect pin. The lock status is also available in the read-back register. The lock detect
function is a window detector on the VCO tuning voltage. The lock flag will be high to show PLL lock which corresponds to the
VCO tuning voltage being within the specified range, typically 0.30V to 1.25V.

The lock time of the PLL will depend on a number of factors; including the loop bandwidth and the reference frequency at the
phase detector. This clock frequency determines the speed at which the state machine and internal calibrations run. A 52MHz
phase detector frequency will give fastest lock times, of typically <50secs when using the PLL re-lock bit.

Phase Detector and Charge Pump

The phase detector provides a current output to drive an active loop filter. The charge pump output current is set by the value
contained in the P1_CP_DEF and P2_CP_DEF fields in the loop filter configuration register. The charge pump current is given
by approximately 3A/bit, and the fields are 6 bits long. This gives default value (31) of 93A and maximum value (63) of
189A.

If the automatic loop bandwidth calibration is enabled the charge pump current is set by the calibration algorithm based upon
the VCO gain.

The phase detector will operate with a maximum input frequency of 52MHz.

Loop Filter
The active loop filter is implemented using the on-chip low noise op-amp, with external resistors and capacitors. The op-amp
gives a tuning voltage range of typically +0.1V to +2.4V. The internal configuration of the chip is shown below with the recom-
mended active loop filter. The loop filter shown is designed to give lowest integrated phase noise, for reference frequencies of
between 26MHz and 52MHz. The external loop filter components give the flexibility to optimize the loop response for any par-
ticular application and combination of reference and VCO frequencies.
8p2

LFILT1 22K
180p LFILT2

470R 470R LFILT3

330p 330p
+1.1V

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 RFMD2080
External Reference
The RFMD2080 has been designed to use an external reference such as a TCXO. The typical input will be a 0.8Vp-p clipped
sine wave, which should be AC-coupled into the reference input. When the PLL is not in use, it may be desirable to turn off the
internal reference circuits, by setting the REFSTBY bit low, to minimize current draw while in standby mode.

On cold start, or if REFSTBY is programmed low, the TCXO will need a warm-up period. This is set by the SU_WAIT bits. This will
allow the clock to be stable and immediately available when the ENBL bit is asserted high, allowing the PLL to assume normal
operation.

If the current consumption of the reference circuits in standby mode, typically 2mA, is not critical, then the REFSTBY bit can be
set high. This allows the fastest startup and lock time after ENBL is taken high.

IQ Modulator
The IQ modulator core of the RFMD2080 is wideband covering from 45MHz to 2700MHz. It has been designed to achieve
exceptional linearity for the amount of DC power consumed.

The modulator mixer cores have four coarse gain/current settings. Each setting steps the gain and linearity by 6dB and can be
used to optimize performance or reduce power consumption. The best linearity is achieved using the modulator bias setting
MODDC=4. This setting adjusts bias mixer current and can be used to trade off linearity and current consumption.

The modulator output is differential and requires a balun and simple matching circuit optimized to the specific application fre-
quencies. The modulator output pins are also used to source current for the modulator mixer circuits, about 10mA on each pin.
This is usually via a center-tapped balun or by RF chokes in the external matching circuitry to the supply. The modulator output
is high impedance, consisting of approximately 2K resistance in parallel with some capacitance, approximately 1pF. The
modulator output does not require a conjugate matching network. It is a constant current output which will drive a real differ-
ential load of typically 200. Since the mixer output is a constant current source, a higher resistance load will give higher out-
put power and gain. A shunt inductor can be used to resonate with the mixer output capacitance at the frequency of interest.
This inductor may not be required at lower frequencies where the impedance of the output capacitance is less significant. At
higher output frequencies the inductance of the bond wires (about 0.5nH on each pin) becomes more significant.

The following diagram is a simple model of the modulator output:

0.5nH

1K
RFMD2080
1pF
RF Output
1K 0.5nH

It is recommended to use a 4:1 balun on the modulator output, presenting 200 to the output in a single ended 50 system.
The RFMD2080 evaluation board has an RFXF8553 wideband transmission line transformer.

Baseband Section
The RFMD2080 features a baseband section that consists of an active low pass filter, variable attenuator and DC offset con-
trol circuitry. DC offset calibration is performed using digital-to-analog converters (DACs) that apply an offset voltage to various
parts of the circuit to compensate for DC offsets introduced by the internal buffers and the mixer core. This can be done to opti-
mize LO suppression by setting registers to program the DAC offset voltages.

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RFMD2080

dcdac_ai dcdac_i
rc_tune

DAC DAC

I
I_p

I_n

10K 10K
bb_atten cal_blank

rc_tune

dcdac_aq dcdac_q
rc_tune

DAC DAC

Q
Q_p

Q_n

10K 10K
bb_atten cal_blank

rc_tune

The differential I and Q input impedance is set by 10K pull down resistors on each pin, so presenting 20K differential
impedance. The baseband input signals will be typically 1Vp-p differential. A common mode DC voltage between 0.5V and 1.5V
is required for optimal performance. If required the phase and amplitude of either of the I or Q signal can be adjusted to
reduce the level of the unwanted sideband signal at the modulator output.

The baseband path consists of an active low pass filter with variable capacitors. The variable capacitors provide 64 "rctune"
settings that allow the input 3dB bandwidth to be tuned from 1.5MHz to 10MHz. This is followed by a variable gain attenuator
that delivers 0dB to -20dB gain in 2dB steps. Additionally, the mixers have gain control, ranging from 0dB to -18dB in 6dB
steps giving a maximum range of 38dB. The variable gain attenuator and mixer input have DACs attached to allow DC offsets
within the baseband path to be corrected, thus reducing LO breakthrough. An isolation switch sits between the variable gain
attenuator and the mixer input to allow their offsets to be compensated separately. This may be required since the offset within
the variable gain attenuator will vary with gain and thus its DC compensation may also have to vary for optimum LO cancella-
tion.

Serial Interface
All on-chip registers in the RFMD2080 are programmed using a proprietary 3-wire serial bus which supports both write and
read operations. Synthesizer programming, device configuration and control are achieved through a mixture of hardware and
software controls. Hardware pins can be used to control ENBL, MODE and RESETX or the device can be programmed entirely
via the serial bus.

The serial data interface can be configured for 4-wire operation, by setting the '4WIRE' bit in the SDI_CTRL register high. Then
pin 26 is used as the data out pin, and pin 32 is the serial data in pin.

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 RFMD2080
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETX.

The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO auto-selection and coarse tun-
ing mechanisms. The VCO auto-selection and coarse tuning are initiated when the ENBL pin is taken high. Every time the fre-
quency of the synthesizer is reprogrammed, ENBL has to be asserted high to initiate these mechanisms and then to initiate the
PLL locking. Alternatively following the programming of a new frequency the PLL re-lock self clearing bit could be used.

If the device is left in the enabled state for long periods, it is recommended that VCO auto-selection and coarse tuning (band
selection) is performed for every 30°C change in temperature. The lock detect flag can be used to indicate when to perform
the VCO calibration; it shows that the VCO tuning voltage has drifted significantly with changing temperature.

The RESETX pin is a hardware reset control that will reset all digital circuits to their startup state when asserted low. The device
includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the
positive supply.

The MODE pin controls which PLL programming register bank is active.

Serial Data Interface Control

The normal mode of operation uses the 3-wire serial data interface to program the device registers, and three extra hardware
control lines; MODE, ENBL and RESETX.

When the device is under software control, achieved by setting the SIPIN bit in the SDI_CTRL register high, then the hardware
can be controlled via the SDI_CTRL register. When this is the case, the MODE and ENBL control lines are not required. If the
device is under software control, pins 1 and 9 can be configured as general purpose outputs (GPO).

Multi-Slice Mode
ENX
SDATA
SCLK

Slice 2 Slice2 Slice2 Slice2

(0) (1) (2) (3)
A1 A2 A1 A2 A1 A2 A1 A2

Vdd Vdd Vdd Vdd

The Multi-Slice mode of operation allows up to four chips to be controlled from a common serial bus. The device address pins,
(15 and 16) ADD1 and ADD2, are used to set the address of each part.

On power up, and after a Reset, the devices ignore the address pins ADD1 and ADD2 and any data presented to the serial bus
will be programmed into all the devices. However, once the 'ADDR' bit in the SDI_CTRL register is set each device then adopts
an address according to the state of the address pins on the device.

General Purpose Outputs

The general purpose outputs (GPOs) can be controlled via the GPO register, and will depend on the state of MODE since they
can be set in different states corresponding to either path 1 or 2. The GPOs can be used for example to drive LEDs, or to con-
trol external circuitry such as switches or low power LNAs.

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RFMD2080
Each GPO pin can supply up to and above 20mA load current. The output voltage of the GPO high state will drop with increased
current drive, by approximately 25mV/mA. Similarly the output voltage of the GPO low state will rise with increased current,
again by approximately 25mV/mA.

Programming Information
Please refer to the register map and programming guides which are available for download from http://rfmd.com/prod-
ucts/IntSynthModulator/.

Evaluation Boards
The evaluation board for the RFMD2080 is provided as part of a design kit, along with the necessary cables and programming
software tool to enable full evaluation of the device. The evaluation board has been configured for wideband operation; the
modulator output is connected to a wideband transmission line transformer balun. Design kits can be ordered from
www.rfmd.com or from local RFMD sales offices and authorized sales channels. For ordering codes please see "Ordering Infor-
mation" on the last page of this data sheet. For further details on how to set up the design kits please refer to the user guide
which can be downloaded from http://rfmd.com/products/IntSynthModulator/.

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 RFMD2080
Detailed Functional Block Diagram

Ext LO Biasing
& LDOs

/2n
[n=0..5] I

Mux
Pre-
scaler

Sequence N-
generator divider /2 IQ
Charge gen
pump

Phase
detector

Reference
divider
Q
Control

GPIO

Pin Out
GPO4/LD/DO 26
RESETX 29
SDATA 32

GPO3 25
SCLK 31

ENX 30

NC 28

NC 27

ENBL/GPO5 1 24 ANA_VDD2

EXT_LO 2 23 MOD_I_P

EXT_LO_DEC 3 22 MOD_I_N

REXT 4 21 NC
Exposed
ANA_VDD1 5 paddle 20 NC

LFILT1 6 19 MOD_Q_P

LFILT2 7 18 MOD_Q_N

LFILT3 8 17 DIG_VDD
10 REF_IN

11 NC

12 TM

13 RF_OUT_N

14 RF_OUT_P

15 GPO1/ADD1

16 GPO2/ADD2
9 MODE/GPO6

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 DS140110
C15 C14 C13 C1
R13
33pF 33pF 33pF 33pF
RESETX 220R D1
GPO4
ENX
GREEN
SCLK
SDATA

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ENBL VDDA2
GPO3
C35
33pF C18
C2
32

31

30

29

28

27

26

25
33pF 10nF
RESETX

NC

NC

GPO3/FM
ENX
SCLK
SDATA

GPO4/LD/DO
1 24
ENBL/GP05 ANA_VDD2
Application Schematic

2 23 MOD_I_P
EXT_LO MOD_I_P
3 22 MOD_I_N
EXT_LO_DEC U1 MOD_I_N
R1 4 21
VDDA1
51K
REXT RFMD2080 NC
5 20
ANA_VDD1 NC
LFILT1 6 19 MOD_Q_P
C34 C5 LFILT1 MOD_Q_P

MODE/GP06

GPO1/ADD1
GPO2/ADD2
RF_OUT_N
10nF 33pF LFILT2 7

RF_OUT_P
18 MOD_Q_N
LFILT2 MOD_Q_N

REF_IN
LFILT3 8 17

GND
LFILT3 DIG_VDD
VDDD

TM
NC
LFILT1

10

11

12

13

14

15
16
33
C3 C19
R3 33pF 10nF
22K
C8
Loop Filter
8.2pF
C9 R2 470R R6 470R
180pF LFILT3 C16 GPO2
1nF GPO1
LFILT2 C10 C17 T1 RFXF8553
330pF 330pF 3 C30
Y1 VDDA2 6 RF_OP 1 J4
2
2 3 4 50 OHM (0.5mm) RF_OP
GND OUT L1
1 100pF
RFMD2080

DNI

2
R31
VDDA2 120R
VDDA2 C29
1 4 +2.8V 100pF
VC VCC
470R
R32 VCTCXO
R9 C33
C43 470R C44
100pF
10nF 10nF

12 of 19
 RFMD2080
Typical Performance Characteristics: Synthesizer
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2080 evaluation board

Synthesizer Phase Noise Synthesizer Phase Noise

5200MHz VCO Frequency, 52MHz Crystal Oscillator 5200MHz VCO Frequency, 26MHz Crystal Oscillator
-60.0 -60.0

-70.0 2600MHz -70.0 2600MHz

1300MHz 1300MHz
-80.0 -80.0
650MHz 650MHz

Phase Noise (dBc/Hz)

-90.0 325MHz
Phase Noise (dBc/Hz)

-90.0 325MHz
162.5MHz 162.5MHz
-100.0 -100.0

-110.0 -110.0

-120.0 -120.0

-130.0 -130.0

-140.0 -140.0

-150.0 -150.0

-160.0 -160.0
1.0 10.0 100.0 1000.0 10000.0 100000.0 1.0 10.0 100.0 1000.0 10000.0 100000.0

Offset Frequency (KHz) Offset Frequency (KHz)

Synthesizer Phase Noise Synthesizer Phase Noise

4000MHz VCO Frequency, 52MHz Crystal Oscillator 4000MHz VCO Frequency, 26MHz Crystal Oscillator
-60.0 -60.0

-70.0 2000MHz -70.0 2000MHz

1000MHz 1000MHz
-80.0 -80.0
500MHz 500MHz
Phase Noise (dBc/Hz)

-90.0
Phase Noise (dBc/Hz)

250MHz -90.0 250MHz

125MHz 125MHz
-100.0 -100.0

-110.0 -110.0

-120.0 -120.0

-130.0 -130.0

-140.0 -140.0

-150.0 -150.0

-160.0 -160.0
1.0 10.0 100.0 1000.0 10000.0 100000.0 1.0 10.0 100.0 1000.0 10000.0 100000.0
Offset Frequency (KHz) Offset Frequency (KHz)

Synthesiser RMS Integrated Phase Noise

Integration Bandwidth 1KHz to 40MHz
0.6
RMS Integrated Phase Noise (Degrees)

26MHz TCXO
0.5 52MHz TCXO

0.4

0.3

0.2

0.1 Note:
• 26 MHz Crystal Oscillator: NDK ENA3523A
0.0 • 52 MHz Crystal Oscillator: NDK ENA3560A
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0
LO Frequency (MHz)

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RFMD2080
Typical Performance Characteristics: VCO
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2080 evaluation board

VCO1 Frequency versus CT_CAL VCO1 Frequency versus Kvco

VCO1 with LO Divide by 2 LO Divide by 2
1800 25

1700
-40 Deg C
20
+27 Deg C
VCO1

Kvco (MHz/V)
+85 Deg C
VCO Frequency (MHz)

1600
15

1500

10
1400

5
1300

1200 0
0 20 40 60 80 100 120 1200 1300 1400 1500 1600 1700 1800

CT_CAL Word VCO Frequency /2 (MHz)

VCO2 Frequency versus CT_CAL VCO2 Frequency versus Kvco

VCO2 with LO Divide by 2 LO Divide by 2
2300 30

2200 -40 Deg C

25
+27 Deg C
2100 +85 Deg C VCO2
VCO Frequency (MHz)

Kvco (MHz/V)

20

2000
15
1900

10
1800

1700 5

1600 0
0 20 40 60 80 100 120 1600 1700 1800 1900 2000 2100 2200 2300
CT_CAL Word VCO Frequency /2 (MHz)

VCO3 Frequency versus CT_CAL VCO3 Frequency versus Kvco

VCO3 with LO Divide by 2 LO Divide by 2
2900 30

2800 -40 Deg C

25
+27 Deg C
2700
+85 Deg C
VCO Frequency (MHz)

VCO3
Kvco (MHz/V)

20
2600

2500 15

2400
10
2300

5
2200

2100 0
0 20 40 60 80 100 120 2200 2300 2400 2500 2600 2700 2800 2900
CT_CAL Word VCO Frequency /2 (MHz)

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14 of 19 support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS140110
 RFMD2080
Typical Performance Characteristics: VCO
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2080 evaluation board
VCO1 Frequency versus Tuning Voltage VCO2 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two For the same coarse tune setting, LO divide by two
1505 2020

2015
1500
2010

VCO2 Frequency /2 (MHz)

VCO1 Frequency /2 (MHz)

1495
2005

1490 2000

1995
1485
-40 Deg C 1990 -40 Deg C
+27 Deg C +27 Deg C
1480
+85 Deg C 1985 +85 Deg C

1475 1980
0.0 0.5 1.0 1.5 0.0 0.5 1.0 1.5
Tuning Voltage (Volts) Tuning Voltage (Volts)

VCO3 Frequency versus Tuning Voltage VCO Phase Noise

For the same coarse tune setting, LO divide by two With LO Divide by 2
2515 -60.0

2510 -70.0 2500MHz VCO3

2000MHz VCO2
2505 -80.0
VCO3 Frequency /2 (MHz)

1500MHz VCO1
Phase Noise (dBc/Hz)

2500 -90.0

2495 -100.0

2490 -110.0

2485 -120.0

2480 -130.0
-40 Deg C
2475 -140.0
+27 Deg C
2470 +85 Deg C -150.0

2465 -160.0
0.0 0.5 1.0 1.5 10.0 100.0 1000.0 10000.0 100000.0
Tuning Voltage (Volts) Offset Frequency (KHz)

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RFMD2080
Typical Performance Characteristics: IQ Modulator
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2080 evaluation board. I and Q Input
Level 1VP-P differential with +1.15V DC bias. DC bias current setting in modulator core, moddc = 4.

Modulator Typical Performance Modulator Typical Performance

I & Q Unadjusted, Output Unmatched Linearity, Output Unmatched
20.0
0.0 0.0

15.0
-10.0 -10.0
Wanted Signal Level (dBm)

10.0

Output Level (dBm)

Suppression (dBc)
-20.0 -20.0
Wanted Signal
5.0
Sideband Suppression
-30.0 -30.0
LO Suppression
0.0
IM3 Product
-40.0 -40.0
-5.0

-50.0 -50.0 -10.0

Wanted Signal

-15.0 Output P1dB

-60.0 -60.0
Output IP3
-20.0
-70.0 -70.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0
Output Frequency (MHz) Output Frequency (MHz)

Modulator Output Frequency Response

Versus Shunt Matching Inductor Value +1.3V Input Bias; Moddc=4
Typical Supply Current
0.0 165.0

160.0
-10.0
Wanted Signal Level (dBm)

Supply Current (mA)

155.0
-20.0 Unmatched
27nH Shunt
150.0
15nH Shunt
-30.0 8.2nH Shunt 85DegC, 3.0V
3.9nH Shunt 145.0 85DegC, 3.3V
27DegC, 3.0V
2.7nH Shunt
27DegC, 3.3V
-40.0 -40DegC, 3.0V
140.0
-40DegC, 3.3V

-50.0 135.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 10.0 100.0 1000.0 10000.0
Output Frequency (MHz) Output Frequency (MHz)

Baseband Input Bandwidth Baseband Input Bandwidth

"rctune" Setting; +3.0V; +27C Versus "rctune" Setting, Voltage & Temperature
0.0 0.0

-5.0 -8.0
Output Power (dBm)

Output Power (dBm)

-40DegC, +3.0V, rctune=0

rctune=0 -40DegC, +3.0V, rctune=63
-40DegC, +3.3V, rctune=0
rctune=8 -40DegC, +3.3V, rctune=63
-10.0 -16.0
rctune=16 +27DegC, +3.0V, rctune=0
rctune=24 +27DegC, +3.0V, rctune=63
+27DegC, +3.3V, rctune=0
rctune=32 +27DegC, +3.3V, rctune=63
rctune=40 +85DegC, +3.0V, rctune=0
-15.0 -24.0 +85DegC, +3.0V, rctune=63
rctune=48
+85DegC, +3.3V, rctune=0
rctune=56 +85DegC, +3.3V, rctune=63
rctune=63

-20.0 -32.0
0.1 1.0 10.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
Baseband Frequency (MHz) Baseband Frequency (MHz)

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

16 of 19 support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS140110
 RFMD2080
Typical Performance Characteristics: IQ Modulator
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2080 evaluation board. I and Q Input
Level 1VP-P differential with +1.15V DC bias. DC bias current setting in modulator core, moddc = 4.
Modulator Output Power Modulator Unadjusted LO Suppression
Vs Temperature & Supply Voltage Vs Temperature & Supply Voltage
0.0 -30.0
-40DegC, +3.0V -40DegC, +3.0V
-40DegC, +3.3V -40DegC, +3.3V
-2.0 -35.0
+27DegC, +3.0V +27DegC, +3.0V
+27DegC, +3.3V +27DegC, +3.3V
-4.0

LO Suppression (dBc)
Wanted Signal Level (dBm)

+85DegC, +3.0V -40.0 +85DegC, +3.0V

+85DegC, +3.3V +85DegC, +3.3V
-6.0
-45.0
-8.0

-50.0
-10.0

-55.0
-12.0

-14.0 -60.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0

Output Frequency (MHz) Output Frequency (MHz)

Modulator Unadjusted Sideband Suppression Modulator IM3 Output Tone

Vs Temperature & Supply Voltage Vs Temperature & Supply Voltage
-30.0 -30.0
-40DegC, +3.0V
-40DegC, +3.3V
-35.0 -35.0
+27DegC, +3.0V
+27DegC, +3.3V
IM3 Product (dBc)
Sideband Suppression (dBc)

-40.0 +85DegC, +3.0V -40.0

+85DegC, +3.3V

-45.0 -45.0
-40DegC, +3.0V
-40DegC, +3.3V
-50.0 -50.0
+27DegC, +3.0V
+27DegC, +3.3V
-55.0 -55.0 +85DegC, +3.0V
+85DegC, +3.3V

-60.0 -60.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0

Output Frequency (MHz) Output Frequency (MHz)

Modulator Output Power for 1dB Compression Modulator Output IP3

Vs Temperature & Supply Voltage Vs Temperature & Supply Voltage
8.0 21.0
-40DegC, +3.0V
6.0 19.0 -40DegC, +3.3V
+27DegC, +3.0V
4.0 17.0
+27DegC, +3.3V
Ouput IP3 (dBm)
Output Level (dBm)

+85DegC, +3.0V
2.0 15.0
+85DegC, +3.3V

0.0 13.0

-40DegC, +3.0V
-2.0 11.0
-40DegC, +3.3V
+27DegC, +3.0V 9.0
-4.0
+27DegC, +3.3V
-6.0 +85DegC, +3.0V 7.0
+85DegC, +3.3V
-8.0 5.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0

Output Frequency (MHz) Output Frequency (MHz)

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

DS140110 support, contact RFMD at (+1) 336-678-5570 or [email protected]. 17 of 19
RFMD2080
Typical Performance Characteristics: IQ Modulator
VDD = +3V and TA = +27°C unless stated otherwise, as measured on RFMD2080 evaluation board. I and Q Input
Level 1VP-P differential with +1.15V DC bias. DC bias current setting in modulator core, moddc = 4.

Modulator Output Noise Floor Modulator Output Noise Floor

1MHz Offset 5MHz Offset
-130.0 -130.0
-40DegC, +3.3V -40DegC, +3.0V
-135.0 +27DegC, +3.0V -135.0 -40DegC, +3.3V

Output Noise Floor (dBm/Hz)

+27DegC, +3.3V +27DegC, +3.0V
-140.0 -40DegC, +3.0V -140.0 +27DegC, +3.3V
Output Noise Floor (dBm/Hz)

+85DegC, +3.0V +85DegC, +3.0V

-145.0 -145.0
+85DegC, +3.3V +85DegC, +3.3V

-150.0 -150.0

-155.0 -155.0

-160.0 -160.0

-165.0 -165.0

-170.0 -170.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0
Output Frequency (MHz) Output Frequency (MHz)

Modulator Input Voltage for 1dB Compression Effect of Gain Setting

Vs Temperature & Supply Voltage Wanted and Current at 500MHz Output
1.6 0.0 160.0
-40DegC, +3.0V
Peak to Peak Differential Voltage (Vp-p)

-40DegC, +3.3V -5.0 155.0

1.5 +27DegC, +3.0V
+27DegC, +3.3V
+85DegC, +3.0V -10.0 150.0
1.4
+85DegC, +3.3V
-15.0 145.0
Wanted (dBm)

1.3

Current (mA)
-20.0 140.0
1.2
-25.0 135.0
1.1 Mod=0; Wanted
-30.0 Mod=1; Wanted 130.0
Mod=2; Wanted
1.0 Mod=3; Wanted
-35.0 125.0
Mod=0; Current
Mod=1; Current
0.9 -40.0 Mod=2; Current 120.0
Mod=3; Current
0.8 -45.0 115.0
0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 5 6 7 8 9 10 11 12 13 14 15

Output Frequency (MHz) Baseband Attenuator Setting (bb_atten)

Effect of Gain Setting on Modulator Performance Effect of Gain Setting on Linearity

Sideband and LO Suppression at 500MHz OIP3 and OP1dB at 500 MHz
-20.0 20.0
Mod=0; Sideband
-25.0 Mod=1; Sideband
Mod=2; Sideband 10.0
Mod=3; Sideband
-30.0
Mod=0; LO
Mod=1; LO 0.0
Level (dBc)

-35.0
Level (dBm)

Mod=2; LO
Mod=3; LO
-40.0 -10.0 Mod=0, OIP3
Mod=1; OIP3
-45.0 Mod=2; OIP3
-20.0
Mod=3; OIP3
-50.0 Mod=0; OP1dB
Mod=1; OP1dB
-30.0
-55.0 Mod=2; OP1dB
Mod=3; OP1dB
-60.0 -40.0
-40.0 -30.0 -20.0 -10.0 0.0 -40.0 -30.0 -20.0 -10.0 0.0
Gain (dB) Gain (dB)

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 RFMD2080
Package Drawing
QFN, 32-pin, 5mm x 5mm

Ordering Information
Ordering Code Package Quantity
RFMD2080SB 32-Pin QFN 5-Piece sample bag
RFMD2080SQ 32-Pin QFN 25-Piece sample bag
RFMD2080SR 32-Pin QFN 100-Piece reel
RFMD2080TR7 32-Pin QFN 750-Piece reel
RFMD2080TR13 32-Pin QFN 2500-Piece reel
DKMD2080 Complete Design Kit 1 Box

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