Von Neumann Architecture:
Program must be resident in main memory to be executed. Program consists of a sequence of
instructions which occupy a contiguous block of main memory. Instructions and data are
indistinguishable, each instruction is fetched , decoded and then executed. Instruction fetch and
data operation cannot occur at the same time.
Arithmetic Logic Unit:
It is the part of the processor which processes instructions that require some form of arithmetic
operations, and logical operations.
Control Unit (CU): part of CPU that fetches instructions from memory, decodes them &
synchronizes operations before sending signals to computer’s memory, ALU and I/O devices to
direct how to respond to instructions sent to processor
System Clock: timing device connected to processor that is needed to synchronize all
components.
Immediate Access Store (IAS): memory unit that can be directly accessed by the processor
What is meant by Register?
Registers are small units of storage within the microprocessor. It allows fast data transfer
between other registers.
The processor’s instructions can be put into these groups:
● Input and output
● Data movement
● Arithemetic operations
● Jump instructions
● Compare instructions
● Modes of addression
General Purpose registers
● Used to temporarily store data values which have been read from memory or some
processed result
● Can be used by assembly language instructions
Memory data register (MDR) : it stores the instructions or data when fetched from memory, or
holds data which is being written to memory. The location accessed in the address held in
Memory address register(MAR).
Benefits of using USB port to allow the attachment of devices?
● devices automatically detected and configured when first attached/plug and play
● it is nearly impossible to wrongly connect a device
● USB has become an industrial standard
● supported by many operating systems
● USB 3.0 allows full duplex data transfer
● later versions are backwards compatible with earlier USB systems
● allows power to be drawn to charge portable devices
Program Counter: Stores the address of next instruction to be executed
Memory Data Register : Stores the data in transit between memory and other registers, it
holds the instruction before it is passed to the CIR
Current Instruction Register : Stores the current instruction being executed.
Memory Address Register: Stores the address of the memory location which is about to be
accessed.
Status Register: It is interpreted as independent bits. Each flag is set depending on an event.
Example: addition overflow, division by zero etc.
Performance of Computer System depends on :
1- Clock Speed
The clock sends out a number of pulses in a given time interval (clock speed_. Each
processor instruction takes certain number of clock cycles to execute. The higher the clock
frequence, the shorter the execution time for the instruction. So performance is improved by
increasing Clock speed.
However, there is a limit on clock speed since the heat generated by higher clock speeds
cannot be removed fast enough, which leads to overheating
2- Bus Width
Bus width determines the number of bits that can be simultaneously transferred. It refers
to as number of lines in a nus. Increasing bus width increases number of bits transferred at one
time. Hence increasing processing speed and performance.
3- Cache Memory
Commonly used instructions are stored in cache memory area of the CPU. If cache
memory size is increased, more commonly executed instructions can be stored and the need for
the CPU to wait for instructions to be loaded reduces, hence
4- Number of Cores
Most CPU chips are multi-core — have more than one core (essentially a processor)
Each core simultaneously processes different instructions through multithreading, improving
computer performance
Special Registers:
• Program Counter (PC) – Contains the address of the next instruction to be fetched.
Passes the address to the MAR and the Program Counter is then incremented. If there is jump
instruction, contents of Program Counter are changed (altered) to the next instruction to be
fetched.
• Memory Address Register (MAR) – Stores the memory address of the location to be
used next. The address of the Program Counter is stored into the MAR to show the address of
instruction to be fetched. Contents of the Memory Address Register are changed as the address
of Current Instruction Register (CIR) changes.
• Memory Data Register (MDR) –Instruction copied from the memory address when
contents of Memory Address Register are from Program Counter. Data is copied from the
memory location if the instruction given is LOAD and data is copied from the Accumulator when
the instruction is STORE.
• Index Register (IR) – Modifies the address in the Current Instruction Register by the
addition of the contents of the Index Register. This register is used for Index Addressing.
• Current Instruction Register (CIR) – Holds the current instruction that is being
processed that holds the operation code and the address of the instruction. Holds the instruction
while decoding. Sends the address to the Memory Address Register.
• Accumulator – Holds the data currently being processed. Result of calculation is held in
accumulator before being passed to the memory unit. The contents of accumulator change each
time a new calculation is made (or a new instruction is fetched).
Marco vs Directive:
● A macro is a sequence of instructionss that are given an idnetifier. These instructions
may need to be executed several times.
● A Directive is an instruction that tells the assembler to do something. It is not a program
instruction.
TYPES of BUSES:
Address bus:
● Lines used to transfer address of main memory or input/output location.It is a
unidirectional bus.
Data bus:
● It is used to transfer data between the processor and memory/input and output devices
about to be used, from processor to memory address register (MAR) . It is a
bidirectional bus.
Control bus:
● It is used to transmit control signals, for example: read/write and fetch. It is dedicated
bus since all timing signals are generated according to control signal
Ports:
● Hardware which provides a physical interface between a device with CPU and a
peripheral device
● Peripheral (I/O) devices cannot be directly connected to CPU, hence connected through
ports
1- Universal Serial Bus (USB): Can connect both input and output devices to processor
through a USB port
2- High Definition Multimedia Interface (HDMI)
● Can only connect output devices (e.g. LCD display) to the processor through a HDMI
port
● HDMI cables transmit high-bandwidth and high-resolution video & audio streams through
HDMI ports
3- Video Graphics Array (VGA)
● Can only connect output devices (e.g. second monitor/display) to the processor through
a VGA port
● VGA ports allows only the transmission of video streams, but not audio components
How special purpose registers are used in the fetch stage of the fetch-execute cycle.
● PC holds address of next instruction to be fetched
● Address in PC is copied to MAR
● PC is incremented
● Instruction loaded to MDR from address held in MAR
● Instruction from MDR loaded to CIR
Decode stage: The opcode and operand parts of instruction are identified
Execute stage: Instructions executed by the control unit sending control signals
Fetch Execute cycle notation:
MAR ← [PC]
PC ← PC + 1
MDR ← [ [MAR] ]
CIR ← [MDR]
What is meant by interrupt
An interrupt is a signal from a source or device, telling the processor its attention is needed.
Example of interrupt
Hardware interrupt:
. Printer out of paper
• No CD in drive
Software interrupt :
• A running program needs input
• Runtime error, e.g. division by zero
How the processor handles an interrupt/ how interrupts are handled during fetch-execute
cycles:
At the start and end of each fetch-execute cycle the processor checks for interrupt(s). It checks
if an interrupt flag is set. Processor identifies the source of the interrupt, and checks the priority
of the interrupt. If interrupt priority is high enough, the processor saves current contents of
registers, Processor calls Interrupt Service Routine (ISR). Address of ISR is loaded into the
Program Counter (PC). When servicing of interrupt completes, processor restores registers.
Lower priority interrupts are re-enabled and Processor continues with next Fetch-execute cycle
