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Computer Architecture and Opera2ng System

Prof. Indranil Sengupta

Department of Computer Science and Engineering
IIT Kharagpur

Basic Opera2on of a Computer

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Introduc2on
• The basic mechanism through which an
instruc8on gets executed shall be discussed.
• Fetch-Decode-Execute cycle.

• May be recalled:
• ALU contains a set of registers, some general-
purpose and some special-purpose.
• First we briefly explain the func8ons of the special-
purpose registers before we look into some
examples.

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Special-purpose Registers: For Keeping Track of

Program / Instruc2ons
• Two special-purpose registers are used:
• Program Counter (PC): Holds the memory address of the next instruc8on to
be executed.
• Automa8cally incremented to point to the next instruc8on when an instruc8on is being
executed.
• Instruc2on Register (IR): Temporarily holds an instruc8on that has been
fetched from memory.
• Need to be decoded to find out the instruc8on type.
• Also contains informa8on about the loca8on of the data.

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Special-purpose Registers: For Interfacing with the

Primary Memory Address
• Two special-purpose registers are used: 0
1
• Memory Address Register (MAR): Holds the address of the 2
memory loca8on to be accessed. 3
4
• Memory Data Register (MDR): Holds the data that is being 5
wriNen into memory, or will receive the data being read
out from memory.
• Memory considered as a linear array of storage
loca8ons (bytes or words) each with unique address. 1023
Memory

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Address
0
1
M Address 2
A 3
R 4
PRIMARY 5
PROCESSOR MEMORY
M Data
D
R
1023
Control Signals Memory

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M Address
A
R
PRIMARY
PROCESSOR MEMORY
M Data
D
R

• To read data from memory Control Signals

• Load the memory address into MAR. MAR ß address

• Issue the control signal READ. Read
MDR ß Mem[MAR]

• To write data into memory

• Load the memory address into MAR. MAR ß address
• Load the data to be wriNen into MDR. MDR ß data
• Issue the control signal WRITE. Write
Mem[MAR] ß MDR
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Architecture of an Example Processor

Memory

MAR MDR
Control
R0
PC
R1
Processor
IR .
. ALU

Rn-1
n General Purpose Registers (GPR)

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Example Instruc2ons
• We shall illustrate the process of instruc8on execu8on with the help of the
following two instruc8ons:
a) ADD R1, LOCA
Add the contents of memory loca8on LOCA (i.e. address of the memory loca8on
is LOCA) to the contents of register R1.
R1 ß R1 + Mem[LOCA]
b) ADD R1, R2
Add the contents of register R2 to the contents of register R1.
R1 ß R1 + R2

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Execu2on of ADD R1,LOCA

• Assume that the instruc8on is stored in memory loca8on 1000, the ini8al value of R1 is
50, and LOCA is 5000.
• Before the instruc8on is executed, PC contains 1000.
• Content of PC is transferred to MAR. MAR ß PC
• READ request is issued to memory unit. Read
• The instruc8on is fetched to MDR. MDR ß Mem[MAR]
• Content of MDR is transferred to IR. IR ß MDR
• PC is incremented to point to the next instruc8on. PC ß PC + 4
• The instruc8on is decoded by the control unit.
ADD R1 5000

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• LOCA (i.e. 5000) is transferred (from IR) to MAR. MAR ß IR[Operand]

• READ request is issued to memory unit. Read
• The data is fetched to MDR. MDR ß Mem[MAR]
• The content of MDR is added to R1. R1 ß R1 + MDR
The steps being carried out are called micro-opera8ons:
MAR ß PC
MDR ß Mem[MAR]
IR ß MDR
PC ß PC + 4
MAR ß IR[Operand]
MDR ß Mem[MAR]
R1 ß R1 + MDR

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R1 125
50
1. PC = 1000
Address Content 2. MAR = 1000
1000 ADD R1, LOCA 3. PC = PC + 4 = 1004
1004 … 4. MDR = ADD R1, LOCA
5. IR = ADD R1, LOCA
5000 75 6. MAR = LOCA = 5000
LOCA 7. MDR = 75
8. R1 = R1 + MDR = 50 + 75 = 125

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Execu2on of ADD R1,R2

• Assume that the instruc8on is stored in memory loca8on 1500, the ini8al value of R1 is
50, and R2 is 200.
• Before the instruc8on is executed, PC contains 1500.
• Content of PC is transferred to MAR. MAR ß PC
• READ request is issued to memory unit. Read
• The instruc8on is fetched to MDR. MDR ß Mem[MAR]
• Content of MDR is transferred to IR. ADD R1, R2 IR ß MDR
• PC is incremented to point to the next instruc8on. PC ß PC + 4
• The instruc8on is decoded by the control unit.
• R2 is added to R1. R1 ß R1 + R2

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R1 250
50
R2 200 1. PC = 1500
2. MAR = 1500
Address Instruc8on
3. PC = PC + 4 = 1504
1500 ADD R1, R2 4. MDR = ADD R1, R2
1504 … 5. IR = ADD R1, R2
6. R1 = R1 + R2 = 250

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Bus Architecture

• The different func8onal modules within the processor must be

connected in an organized manner to form an opera8onal system.
• Bus refers to a group of lines that serves as a connec8ng path for
several devices.
• The simplest way to connect the func8onal unit is to use the single
bus architecture.
• Only one data transfer allowed in one clock cycle.
• For mul8-bus architecture, parallelism in data transfer is allowed.

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System-Level Single Bus Architecture

Input Output Memory Processor

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System-Level Two-Bus Architecture

Processor Memory

Output
Device

Input
Device
I/O Processor

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Single-Bus Architecture Inside the Processor

• Suppose there is a single bus inside the processor.
• ALU and the registers are all connected via the single bus.
• An external bus can connect the processor to the memory and I/O devices.
• A typical single-bus processor architecture is shown on the next slide.
• Two temporary registers Y and Z are also included.
• Register Y temporarily holds one of the operands of the ALU.
• Register Z temporarily holds the result of the ALU opera8on.
• The mul8plexer selects a constant operand 4 during execu8on of the micro-
opera8on: PC ß PC + 4.

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Internal Processor Bus

PC Instruc8on
.. Control
MAR
Decoding and . signals
Control Unit
MEMORY
MDR
IR
4 Y R0
Select MUX R1
..
Func8on
.
ALU
select Carry-in Rn-1

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Mul2-Bus Architectures

• Modern processors have mul8ple buses that connect the registers

and other func8onal units.
• Allows mul8ple data transfer micro-opera8ons to be executed in the same
clock cycle.
• Results in overall faster instruc8on execu8on.
• Also advantageous to have mul8ple shorter buses rather than a single
long bus.
• Smaller parasi8c capacitance, and hence smaller delay.

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