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Computer Architecture and Opera2ng System

Prof. Indranil Sengupta

Department of Computer Science and Engineering
IIT Kharagpur

Instruc2on Set Architecture

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Introduc2on

• Instruc/on Set Architecture (ISA)

• Serves as an interface between so=ware and hardware.
• Typically consists of informa/on regarding the programmer’s view of the
architecture (i.e. the registers, address and data buses, etc.).
• Also consists of the instruc/on set.
• Many ISA’s are not specific to a par/cular computer architecture.
• They survive across genera/ons.
• Classic examples: IBM 360 series, Intel x86 series, etc.

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Instruc2on Set Design Issues

• Number of explicit operands:

• 0, 1, 2 or 3.
• Loca/on of the operands:
• Registers, accumulator, memory.
• Specifica/on of operand loca/ons:
• Addressing modes: register, immediate, indirect, rela/ve, etc.
• Sizes of operands supported:
• Byte (8-bits), Half-word (16-bits), Word (32-bits), Double (64-bits), etc.
• Supported opera/ons:
• ADD, SUB, MUL, AND, OR, CMP, MOVE, JMP, etc.

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Evolu2on of Instruc2on Sets

1. Accumulator based: 1960’s (EDSAC, IBM 1130)
2. Stack based: 1960-70 (Burroughs 5000)
3. Memory-Memory based: 1970-80 (IBM 360)
4. Register-Memory based: 1970-present (Intel x86)
5. Register-Register based: 1960-present (MIPS, CDC 6600, SPARC)

1: 1-address instruc/ons: 3: 2- or 3-address instruc/ons:

ADD X à ACC = ACC + Mem[X] ADD A,B à Mem[A] = Mem[A] + Mem[B]
ADD A,B,C à Mem[A] = Mem[B] + Mem[C]
2: 0-address instruc/ons:
ADD à TOS = TOS + NEXT 5: 3-address instruc/ons:
ADD R1,R2,R3 à R1 = R2 + R3
4: 2-address instruc/ons:
LOAD R1,X à R1 = Mem[X]
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Example Code Sequence for Z = X + Y

a) Stack machine: Top Of Stack

PUSH X
PUSH Y
ADD
POP Z
• The ADD instruc/on pops two
elements from stack, adds them, and
ALU
pushes back result.

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b) Accumulator based machine: ACC

LOAD X // ACC = Mem[X]
ADD Y // ACC = ACC + Mem[Y]
STORE Z // Mem[Z] = ACC
ALU
• All instruc/ons assume that one of the
operands (and also the result) is in a special
register called accumulator. From
memory

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Registers
c) Register-Memory machine:
LOAD R2,X // R2 = Mem[X]
ADD R2,Y // R2 = R2 + Mem[Y]
STORE Z,R2 // Mem[Z] = R2
• One of the operands is assumed to be in ALU
register and another in memory.

From
memory

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Registers
d) Register-Register machine:
LOAD R1,X // R1 = Mem[X]
LOAD R2,Y // R2 = Mem[Y]
ADD R3,R1,R2 // R3 = R1 + R2
STORE Z,R3 // Mem[Z] = R3

• Also called load-store architecture, as only LOAD ALU

and STORE instruc/ons can access memory.

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About General Purpose Registers (GPRs)

• Older architectures had a large number of special purpose registers.

• Program counter, stack pointer, index register, flag register, accumulator, etc.
• Newer architectures, in contrast, have a large number of GPRs.
• Why?
• Easy for the compiler to assign some variables to registers.
• Registers are much faster than memory.
• More compact instruc/on encoding as fewer bits are required to specify
registers.
• Many processors have 32 or more GPR’s.

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COMPARISON BETWEEN VARIOUS

ARCHITECTURE TYPES

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
PUSH B
MUL
SUB
SUB
TOS POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
PUSH B
MUL
SUB
TOS SUB
A POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
PUSH B
MUL
TOS
SUB
B SUB
A POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
PUSH B
MUL
SUB
TOS SUB
A/B POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
TOS PUSH C
PUSH B
B
MUL
C
SUB
A SUB
A/B POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
TOS PUSH B
MUL
B*C
SUB
A SUB
A/B POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
PUSH B
TOS MUL
SUB
A-B*C SUB
A/B POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
PUSH B
MUL
SUB
TOS
SUB
A/B-(A-B*C) POP Y

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(a) Stack Architecture

• Example: Y = A / B – (A – C * B)
• Typical instruc/ons: PUSH A
PUSH X, POP X PUSH B
DIV
ADD, SUB, MUL, DIV
PUSH A
PUSH C
PUSH B
MUL
SUB
SUB
TOS Y = RESULT
POP Y

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(b) Accumulator Architecture Example: Y = A / B – (A – C * B)

LOAD C
MUL B
• Typical instruc/ons:
STORE D // D = C * B
LOAD X, STORE X
LOAD A
ADD X, SUB X, MUL X, DIV X
SUB D
STORE D // D = A – C * B
LOAD A
DIV B
SUB D
STORE Y

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(c) Memory-Memory Architecture Example: Y = A / B – (A – C * B)

DIV D,A,B
• Typical instruc/ons (3 operands): MUL E,C,B
ADD X,Y,Z SUB E,A,E
SUB X,Y,Z SUB Y,D,E
MUL X,Y,Z
• Typical instruc/ons (2 operands): MOV D,A
MOV X,Y DIV D,B
ADD X,Y MOV E,C
SUB X,Y MUL E,B
MUL X,Y SUB A,E
SUB D,A

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(d) Load-Store Architecture Example: Y = A / B – (A – C * B)

LOAD R1,A
• Typical instruc/ons: LOAD R2,B
LOAD R1,X LOAD R3,C
STORE Y,R2 DIV R4,R1,R2
ADD R1,R2,R3 MUL R5,R3,R2
SUB R5,R1,R5
SUB R1,R2,R3
SUB R4,R4,R5
STORE Y,R4

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Instruc2on Format

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Instruc2on Format
opcode operand (s)

• An instruc/on consists of two parts:-

• Opera2on Code or Opcode
• Specifies the opera/on to be performed by the instruc/on.
• Various categories of instruc/ons: data transfer, arithme/c and logical, control, I/O and
special machine control.
• Operand(s)
• Specifies the source(s) and des/na/on of the opera/on.
• Source operand can be specified by an immediate data, by naming a register, or
specifying the address of memory.
• Des/na/on can be specified by a register or memory address.

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• Number of operands varies from instruc/on to instruc/on.

• Also for specifying an operand, various addressing modes are
possible:
• Immediate addressing
• Direct addressing
• Indirect addressing
• Rela/ve addressing
• Indexed addressing, and many more.

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Instruc2on Format Examples

opcode Implied addressing: NOP, HALT, ADD

opcode memory address 1-address: ADD X, LOAD M

opcode memory address memory address 2-address: ADD X,Y

opcode register memory address Register-memory: ADD R1,X

opcode register register register Register-register: ADD R1,R2,R3

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ADDRESSING MODES

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What are Addressing Modes?

• They specify the mechanism by which the operand data can be

located.
• Some ISA’s are quite complex and supports many addressing modes.
• ISA’s based on load-store architecture are usually simple and support
very limited number of addressing modes.
• Various addressing modes exist:
• Immediate, Direct, Indirect, Register, Register Indirect, Indexed, Stack,
Rela/ve, Base, etc.
• Not all processors support all addressing modes.

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(a) Immediate Addressing

• The operand is part of the instruc/on itself.
• No memory reference is required to access the operand.
• Fast but limited range (because a limited number of bits are provided to specify the
immediate data).
• Examples:
• ADD #25 // ACC = ACC + 25
• ADD R1,R2,#42 // R1 = R2 + 42

opcode immediate data

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(b) Direct Addressing

• The instruc/on contains a field that holds the memory address of the
operand.
opcode operand address

• Example:
• ADD R1,20A6H // R1 = R1 + Mem[20A6]
• Single memory access is required to access the operand.
• No addi/onal calcula/ons required to determine the operand address.
• Limited address space (as number of bits is limited, say, 16 bits).

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opcode operand address

Memory

operand

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(c) Indirect Addressing

• The instruc/on contains a field that holds the memory address, which in
turn holds the memory address of the operand.
• Two memory accesses are required to get the operand value.
• Slower but can access large address space.
• Not limited by the number of bits in operand address like direct addressing.
• Examples:
• ADD R1,(20A6H) // R1 = R1 + (Mem[20A6])

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opcode operand address

Memory

operand

pointer

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(d) Register Addressing

• The operand is held in a register, and the instruc/on specifies the register
number.
• Very few number of bits needed, as the number of registers is limited.
• Faster execu/on, since no memory access is required for geqng the operand.
• Modern load-store architectures support large number of registers.
• Examples:
• ADD R1,R2,R3 // R1 = R2 + R3
• MOV R2,R5 // R2 = R5

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opcode register no
Register Bank

operand

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(e) Register Indirect Addressing

• The instruc/on specifies a register, and the register holds the memory
address where the operand is stored.
• Can access large address space.
• One fewer memory access as compared to indirect addressing.
• Example:
• ADD R1,(R5) // R1 = R1 + Mem[R5]

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opcode register no

Register Bank Memory

Memory Address
operand

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(f) Rela2ve Addressing (PC Rela2ve)

• The instruc/on specifies an offset or displacement, which is added to the
program counter (PC) to get the effec/ve address of the operand.
• Since the number of bits to specify the offset is limited, the range of rela/ve
addressing is also limited.
• If a 12-bit offset is specified, it can have values ranging from -2048 to +2047.

opcode offset Memory

ADDER
operand
PC

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(g) Indexed Addressing

• Either a special-purpose register, or a general-purpose register, is used as
index register in this addressing mode.
• The instruc/on specifies an offset or displacement, which is added to the
index register to get the effec/ve address of the operand.
• Example:
• LOAD R1,1050(R3) // R1 = Mem[1050+R3]
• Can be used to sequen/ally access the elements of an array.
• Offset gives the star/ng address of the array, and the index register value
specifies the array element to be used.

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opcode index reg offset

Register Bank Memory

ADDER operand

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(h) Stack Addressing

• Operand is implicitly on top of the stack.
• Used in zero-address machines earlier.
• Examples:
• ADD
• PUSH X
• POP X
• Many processors have a special register called the stack pointer (SP) that
keeps track of the stack-top in memory.
• PUSH, POP, CALL, RET instruc/ons automa/cally modify SP.

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Some Other Addressing Modes

• Base addressing
• The processor has a special register called the base register or segment register.
• All operand addresses generated are added to the base register to get the final
memory address.
• Allows easy movement of code and data in memory.
• Autoincrement and Autodecrement
• First introduced in the PDP-11 computer system.
• The register holding the operand address is automa/cally incremented or
decremented a=er accessing the operand (like a++ and a-- in C).

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