Faculty of

Engineering

ECE203
Digital Logic Design

Chapter 2
Boolean Algebra and Logic Gate

Dr. Ahmed Mohamed Abdeltawab

Electronics and Communication Department

ECE 203 Digital Logic Design Ch2-1

Algebras
Faculty of
Engineering

◼ What is an algebra?
Mathematical system consisting of
❑
❑ Set of elements

❑ Set of operators

❑ Axioms or postulates

◼ Why is it important?
❑ Defines rules of “calculations”
◼ Example: arithmetic on natural numbers
❑ Set of elements: N = {1,2,3,4,…}
❑ Operator: +, –, *
❑ Axioms: associativity, distributivity, closure, identity elements, etc.
◼ Note: operators with two inputs are called binary
❑ Does not mean they are restricted to binary numbers!
❑ Operator(s) with one input are called unary

ECE 203 Digital Logic Design Ch2-2

BASIC DEFINITIONS
Faculty of
Engineering

 A set is collection of having the same property.

◆ S: set, x and y: element or event
◆ For example: S = {1, 2, 3, 4}
» If x = 2, then xS.
» If y = 5, then y S.
 A binary operator defines on a set S of elements is a rule that
assigns, to each pair of elements from S, a unique element
from S.
◆ For example: given a set S, consider a*b = c and * is a binary
operator.
◆ If (a, b) through * get c and a, b, cS, then * is a binary operator of S.
◆ On the other hand, if * is not a binary operator of S and a, bS, then c
 S.

ECE 203 Digital Logic Design Ch2-3

BASIC DEFINITIONS
Faculty of
Engineering

 The most common postulates used to formulate various

algebraic structures are as follows:
1. Closure: a set S is closed with respect to a binary operator if, for every pair
of elements of S, the binary operator specifies a rule for obtaining a unique
element of S.
◆ For example, natural numbers N={1,2,3,...} is closed w.r.t. the binary operator
+ by the rule of arithmetic addition, since, for any a, bN, there is a unique
cN such that
» a+b = c
» But operator – is not closed for N, because 2-3 = -1 and 2, 3 N, but (-1)N.
2. Associative law: a binary operator * on a set S is said to be associative
whenever
◆ (x * y) * z = x * (y * z) for all x, y, zS
» (x+y)+z = x+(y+z)
3. Commutative law: a binary operator * on a set S is said to be commutative
whenever
◆ x * y = y * x for all x, yS
» x+y = y+x
ECE 203 Digital Logic Design Ch2-4
BASIC DEFINITIONS
Faculty of
Engineering

4. Identity element: a set S is said to have an identity element with respect

to a binary operation * on S if there exists an element eS with the
property that
◆ e * x = x * e = x for every xS
» 0+x = x+0 =x for every xI . I = {…, -3, -2, -1, 0, 1, 2, 3, …}.
» 1*x = x*1 =x for every xI. I = {…, -3, -2, -1, 0, 1, 2, 3, …}.

5. Inverse: a set having the identity element e with respect to the binary
operator to have an inverse whenever, for every xS, there exists an
element yS such that
◆ x*y=e
» The operator + over I, with e = 0, the inverse of an element a is (-a), since a+(-a)
= 0.
6. Distributive law: if * and ．are two binary operators on a set S, * is said
to be distributive over . whenever
◆ x * (y．z) = (x * y)．(x * z)

ECE 203 Digital Logic Design Ch2-5

George Boole
Faculty of
Engineering

 Father of Boolean algebra

 He came up with a type of linguistic algebra, the three
most basic operations of which were (and still are) AND,
OR and NOT. It was these three functions that formed the
basis of his premise, and were the only operations
necessary to perform comparisons or basic mathematical
functions.
 Boole’s system (detailed in his 'An Investigation of the
Laws of Thought, on Which Are Founded the
Mathematical Theories of Logic and Probabilities', 1854)
was based on a binary approach, processing only two George Boole (1815 - 1864)
objects - the yes-no, true-false, on-off, zero one approach.
 Surprisingly, given his standing in the academic
community, Boole's idea was either criticized or
completely ignored by the majority of his peers.
 Eventually, one bright student, Claude Shannon (1916-
2001), picked up the idea and ran with it

ECE 203 Digital Logic Design Ch2-6

Axiomatic Definition of Boolean Algebra
Faculty of
Engineering

 We need to define algebra for binary values

◆ Developed by George Boole in 1854

 Huntington postulates for Boolean algebra (1904):

 B = {0, 1} and two binary operations, + and．
◆ Closure with respect to operator + and operator ·

◆ Identity element 0 for operator + and 1 for operator ·

◆ Commutativity with respect to + and ·

x+y = y+x, x·y = y·x
◆ Distributivity of · over +, and + over ·
x·(y+z) = (x·y)+(x·z) and x+(y·z) = (x+y)·(x+z)
⚫ Complement for every element x is x’ with x+x’=1, x·x’=0

◆ There are at least two elements x,yB such that xy

ECE 203 Digital Logic Design Ch2-7
Boolean Algebra
Faculty of
Engineering

 Terminology:
◆ Literal: A variable or its complement
◆ Product term: literals connected by •
◆ Sum term: literals connected by +

ECE 203 Digital Logic Design Ch2-8

Postulates of Two-Valued Boolean Faculty of

Algebra
Engineering

 B = {0, 1} and two binary operations, + and．

 The rules of operations: AND、OR and NOT.

AND OR NOT
x y x．y x y x+y x x'
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
1. Closure (+ and‧)
2. The identity elements
(1) +: 0
(2)．: 1

ECE 203 Digital Logic Design Ch2-9

Postulates of Two-Valued Boolean Faculty of

Algebra
Engineering

3. The commutative laws

4. The distributive laws

x y z y+z x．(y+z) x．y x．z (x．y)+(x．z)

0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

ECE 203 Digital Logic Design Ch2-10

Duality
Faculty of
Engineering

 The principle of duality is an important concept. This says

that if an expression is valid in Boolean algebra, the dual of
that expression is also valid.
 To form the dual of an expression, replace all + operators
with . operators, all . operators with + operators, all ones
with zeros, and all zeros with ones.
 Form the dual of the expression
a + (bc) = (a + b)(a + c)
 Following the replacement rules…
a(b + c) = ab + ac
 Take care not to alter the location of the parentheses if they
are present.

ECE 203 Digital Logic Design Ch2-11

Basic Theorems
Faculty of
Engineering

ECE 203 Digital Logic Design Ch2-12

Boolean Theorems
Faculty of
Engineering

 Huntington’s postulates define some rules

Post. 1:
closure
Post. 2:
(a) x+0=x, (b) x·1=x
Post. 3:
(a) x+y=y+x, (b) x·y=y·x
Post. 4:
(a) x(y+z) = xy+xz,
(b) x+yz = (x+y)(x+z)
Post. 5: (a) x+x’=1, (b) x·x’=0

 Need more rules to modify

algebraic expressions
◆ Theorems that are derived from postulates
 What is a theorem?
◆ A formula or statement that is derived from postulates
(or other proven theorems)
 Basic theorems of Boolean algebra
◆ Theorem 1 (a): x + x = x (b): x · x = x
◆ Looks straightforward, but needs to be proven !

ECE 203 Digital Logic Design Ch2-13

Proof of x+x=x
Faculty of
Engineering

 We can only use Huntington postulates:

Huntington postulates: Post. 2: (a) x+0=x, (b) x·1=x
Post. 3: (a) x+y=y+x, (b) x·y=y·x
Post. 4: (a) x(y+z) = xy+xz,
(b) x+yz = (x+y)(x+z)
Post. 5: (a) x+x’=1, (b) x·x’=0

 Show that x+x=x.

x+x = (x+x)·1 by 2(b)
= (x+x)(x+x’) by 5(a)
= x+xx’ by 4(b)
= x+0 by 5(b)
=x by 2(a)
Q.E.D.
 We can now use Theorem 1(a) in future proofs

ECE 203 Digital Logic Design Ch2-14

Proof of x·x=x
Faculty of
Engineering

 Similar to previous Huntington postulates:

proof Post. 2: (a) x+0=x, (b) x·1=x
Post. 3: (a) x+y=y+x, (b) x·y=y·x
Post. 4: (a) x(y+z) = xy+xz,
(b) x+yz = (x+y)(x+z)
Post. 5: (a) x+x’=1, (b) x·x’=0
Th. 1: (a) x+x=x

 Show that x·x = x.

x·x = xx+0 by 2(a)
= xx+xx’by 5(b)
= x(x+x’) by 4(a)
= x·1 by 5(a)
=x by 2(b)
Q.E.D.

ECE 203 Digital Logic Design Ch2-15

Proof of x+1=1
Faculty of
Engineering

Huntington postulates:
 Theorem 2(a): x + 1 = 1
Post. 2: (a) x+0=x, (b) x·1=x
x + 1 = 1．(x + 1) by 2(b) Post. 3: (a) x+y=y+x, (b) x·y=y·x
=(x + x')(x + 1) 5(a) Post. 4: (a) x(y+z) = xy+xz,
(b) x+yz = (x+y)(x+z)
= x + x' 1 4(b) Post. 5: (a) x+x’=1, (b) x·x’=0
Th. 1: (a) x+x=x
= x + x' 2(b)
=1 5(a)
 Theorem 2(b): x．0 = 0 by duality
 Theorem 3: (x')' = x
◆ Postulate 5 defines the complement of x, x + x' = 1 and x x' = 0
◆ The complement of x' is x is also (x')'

ECE 203 Digital Logic Design Ch2-16

 Absorption Property (Covering)
Faculty of
Engineering

 Theorem 6(a): x + xy = x Huntington postulates:

◆ x + xy = x．1 + xy by 2(b) Post. 2: (a) x+0=x, (b) x·1=x

= x (1 + y) 4(a) Post. 3: (a) x+y=y+x, (b) x·y=y·x
Post. 4: (a) x(y+z) = xy+xz,
= x (y + 1) 3(a) (b) x+yz = (x+y)(x+z)
= x．1 Th 2(a) Post. 5: (a) x+x’=1, (b) x·x’=0
Th. 1: (a) x+x=x
=x 2(b)

 Theorem 6(b): x (x + y) = x by duality

 By means of truth table (another way to proof )
x y xy x+xy
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1

ECE 203 Digital Logic Design Ch2-17

 DeMorgan’s Theorem
Faculty of
Engineering

 Theorem 5(a): (x + y)’ = x’y’

 Theorem 5(b): (xy)’ = x’ + y’
 By means of truth table

x y x’ y’ x+y (x+y)’ x’y’ xy x’+y' (xy)’

0 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 0 1 1 0 0 0 1 1
1 1 0 0 1 0 0 1 0 0

ECE 203 Digital Logic Design Ch2-18

 Consensus Theorem Faculty of
Engineering

1. xy + x’z + yz = xy + x’z
2. (x+y)•(x’+z)•(y+z) = (x+y)•(x’+z) -- (dual)
 Proof:
xy + x’z + yz = xy + x’z + (x+x’)yz
= xy + x’z + xyz + x’yz
= (xy + xyz) + (x’z + x’zy)
= xy + x’z
QED (2 true by duality).

ECE 203 Digital Logic Design Ch2-19

Operator Precedence Faculty of
Engineering

 The operator precedence for evaluating Boolean Expression

is
◆ Parentheses
◆ NOT
◆ AND
◆ OR
 Examples
◆ x y' + z
◆ (x y + z)'

ECE 203 Digital Logic Design Ch2-20

Boolean Functions Faculty of
Engineering

 A Boolean function
◆ Binary variables
◆ Binary operators OR and AND
◆ Unary operator NOT
◆ Parentheses
 Examples
◆ F1= x y z'
◆ F2 = x + y'z
◆ F3 = x' y' z + x' y z + x y'
◆ F4 = x y' + x' z

ECE 203 Digital Logic Design Ch2-21

Boolean Functions Faculty of
Engineering

 The truth table of 2n entries

x y z F1 F2 F3 F4
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 0 0 0 0
0 1 1 0 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0
 Two Boolean expressions may specify the same function
◆ F3 = F4

ECE 203 Digital Logic Design Ch2-22

Boolean Functions Faculty of
Engineering

 Implementation with logic gates

◆ F4 is more economical

F2 = x + y'z

F3 = x' y' z + x' y z + x y'

F4 = x y' + x' z

ECE 203 Digital Logic Design Ch2-23

Algebraic Manipulation Faculty of
Engineering

 To minimize Boolean expressions

◆ Literal: a primed or unprimed variable (an input to a gate)
◆ Term: an implementation with a gate
◆ The minimization of the number of literals and the number of terms
→ a circuit with less equipment
◆ It is a hard problem (no specific rules to follow)
 Example 2.1
1. x(x'+y) = xx' + xy = 0+xy = xy
2. x+x'y = (x+x')(x+y) = 1 (x+y) = x+y
3. (x+y)(x+y') = x+xy+xy'+yy' = x(1+y+y') = x
4. xy + x'z + yz = xy + x'z + yz(x+x') = xy + x'z + yzx + yzx' = xy(1+z)
+ x'z(1+y) = xy +x'z
5. (x+y)(x'+z)(y+z) = (x+y)(x'+z), by duality from function 4.
(consensus theorem with duality)

ECE 203 Digital Logic Design Ch2-24

Complement of a Function
Faculty of
Engineering

 An interchange of 0's for 1's and 1's for 0's in the value of F
◆ By DeMorgan's theorem
◆ (A+B+C)' = (A+X)' let B+C = X
= A'X' by theorem 5(a) (DeMorgan's)
= A'(B+C)' substitute B+C = X
= A'(B'C') by theorem 5(a) (DeMorgan's)
= A'B'C' by theorem 4(b) (associative)
 Generalizations: a function is obtained by interchanging AND
and OR operators and complementing each literal.
◆ (A+B+C+D+ ... +F)' = A'B'C'D'... F'
◆ (ABCD ... F)' = A'+ B'+C'+D' ... +F'

ECE 203 Digital Logic Design Ch2-25

Examples Faculty of
Engineering

 Example 2.2
◆ F1' = (x'yz' + x'y'z)' = (x'yz')' (x'y'z)' = (x+y'+z) (x+y+z')
◆ F2' = [x(y'z'+yz)]' = x' + (y'z'+yz)' = x' + (y'z')' (yz)‘
= x' + (y+z) (y'+z')
= x' + yz‘+y'z
 Example 2.3: a simpler procedure
◆ Take the dual of the function and complement each literal
1. F1 = x'yz' + x'y'z.
The dual of F1 is (x'+y+z') (x'+y'+z).
Complement each literal: (x+y'+z)(x+y+z') = F1'
2. F2 = x(y' z' + yz).
The dual of F2 is x+(y'+z') (y+z).
Complement each literal: x'+(y+z)(y' +z') = F2'

ECE 203 Digital Logic Design Ch2-26

2.6 Canonical and Standard Forms
Faculty of
Engineering

Minterms and Maxterms

 A minterm (standard product): an AND term consists of all
literals in their normal form or in their complement form.
◆ For example, two binary variables x and y,
» xy, xy', x'y, x'y'
◆ It is also called a standard product.
◆ n variables con be combined to form 2n minterms.
 A maxterm (standard sums): an OR term
◆ It is also call a standard sum.
◆ 2n maxterms.

ECE 203 Digital Logic Design Ch2-27

Minterms and Maxterms Faculty of
Engineering

 Each maxterm is the complement of its corresponding

minterm, and vice versa.

ECE 203 Digital Logic Design Ch2-28

Minterms and Maxterms Faculty of
Engineering

 An Boolean function can be expressed by

◆ A truth table
◆ Sum of minterms
◆ f1 = x'y'z + xy'z' + xyz = m1 + m4 +m7 (Minterms)
◆ f2 = x'yz+ xy'z + xyz'+xyz = m3 + m5 +m6 + m7 (Minterms)

ECE 203 Digital Logic Design Ch2-29

Minterms and Maxterms Faculty of
Engineering

 The complement of a Boolean function

◆ The minterms that produce a 0
◆ f1' = m0 + m2 +m3 + m5 + m6 = x'y'z'+x'yz'+x'yz+xy'z+xyz'
◆ f1 = (f1')'
= (x+y+z)(x+y'+z) (x+y'+z') (x'+y+z')(x'+y'+z) = M0 M2 M3 M5 M6
◆ f2 = (x+y+z)(x+y+z')(x+y'+z)(x'+y+z)=M0M1M2M4
 Any Boolean function can be expressed as
◆ A sum of minterms (“sum” meaning the ORing of terms).
◆ A product of maxterms (“product” meaning the ANDing of terms).
◆ Both boolean functions are said to be in Canonical form.

ECE 203 Digital Logic Design Ch2-30

Sum of Minterms (SOM) Faculty of
Engineering

 Sum of minterms: there are 2n minterms and 22n combinations

of function with n Boolean variables.
 Example 2.4: express F = A+BC' as a sum of minterms.
◆ F = A+B'C = A (B+B') + B'C = AB +AB' + B'C = AB(C+C') +
AB'(C+C') + (A+A')B'C = ABC+ABC'+AB'C+AB'C'+A'B'C
◆ F = A'B'C +AB'C' +AB'C+ABC'+ ABC = m1 + m4 +m5 + m6 + m7
◆ F(A, B, C) = S(1, 4, 5, 6, 7)
◆ or, built the truth table first

ECE 203 Digital Logic Design Ch2-31

Product of Maxterms (POM) Faculty of
Engineering

 Product of maxterms: using distributive law to expand.

◆ x + yz = (x + y)(x + z) = (x+y+zz')(x+z+yy') =
(x+y+z)(x+y+z')(x+y'+z)
 Example 2.5: express F = xy + x'z as a product of maxterms.
◆ F = xy + x'z = (xy + x')(xy +z) = (x+x')(y+x')(x+z)(y+z) =
(x'+y)(x+z)(y+z)
◆ x'+y = x' + y + zz' = (x'+y+z)(x'+y+z')
◆ F = (x+y+z)(x+y'+z)(x'+y+z)(x'+y+z') = M0M2M4M5
◆ F(x, y, z) = P(0, 2, 4, 5)

ECE 203 Digital Logic Design Ch2-32

Conversion between Canonical Forms
Faculty of
Engineering

 The complement of a function expressed as the sum of

minterms equals the sum of minterms missing from the
original function.
◆ F(A, B, C) = S(1, 4, 5, 6, 7)
◆ Thus, F'(A, B, C) = S(0, 2, 3)
◆ By DeMorgan's theorem
F(A, B, C) = P(0, 2, 3)
F'(A, B, C) =P (1, 4, 5, 6, 7)
◆ mj' = Mj
◆ Sum of minterms = product of maxterms
◆ Interchange the symbols S and P and list those numbers missing from
the original form
» S of 1's
» P of 0's

ECE 203 Digital Logic Design Ch2-33

Example Faculty of
Engineering

 Example
◆ F = xy + xz
◆ F(x, y, z) = S(1, 3, 6, 7)
◆ F(x, y, z) = P (0, 2, 4, 6)

ECE 203 Digital Logic Design Ch2-34

Standard Forms Faculty of
Engineering

 Canonical forms are very seldom the ones with the least
number of literals.
 Standard forms: the terms that form the function may obtain
one, two, or any number of literals.
◆ Sum of products: F1 = y' + xy+ x'yz'
◆ Product of sums: F2 = x(y'+z)(x'+y+z')
◆ F3 = A'B'CD+ABC'D'

ECE 203 Digital Logic Design Ch2-35

Implementation Faculty of
Engineering

 Two-level implementation

 Multi-level implementation

ECE 203 Digital Logic Design Ch2-36

2.7 Other Logic Operations Faculty of
Engineering

 2n rows in the truth table of n binary variables.

n
 22
functions for n binary variables.
 16 functions of two binary variables.

 All the new symbols except for the exclusive-OR symbol are
not in common use by digital designers.

ECE 203 Digital Logic Design Ch2-37

Boolean Expressions Faculty of
Engineering

ECE 203 Digital Logic Design Ch2-38

2.8 Digital Logic Gates Faculty of
Engineering

 Boolean expression: AND, OR and NOT operations

 Constructing gates of other logic operations
◆ The feasibility and economy;
◆ The possibility of extending gate's inputs;
◆ The basic properties of the binary operations (commutative and
associative);
◆ The ability of the gate to implement Boolean functions.

ECE 203 Digital Logic Design Ch2-39

Standard Gates Faculty of
Engineering

 Consider the 16 functions in Table 2.8 (slide 33)

◆ Two are equal to a constant (F0 and F15).
◆ Four are repeated twice (F4, F5, F10 and F11).
◆ Inhibition (F2) and implication (F13) are not commutative or
associative.
◆ The other eight: complement (F12), transfer (F3), AND (F1), OR (F7),
NAND (F14), NOR (F8), XOR (F6), and equivalence (XNOR) (F9) are
used as standard gates.
◆ Complement: inverter.
◆ Transfer: buffer (increasing drive strength).
◆ Equivalence: XNOR.

ECE 203 Digital Logic Design Ch2-40

Summary of Logic Gates Faculty of
Engineering

Figure 2.5 Digital logic gates

ECE 203 Digital Logic Design Ch2-41
Summary of Logic Gates Faculty of
Engineering

Figure 2.5 Digital logic gates

ECE 203 Digital Logic Design Ch2-42
Multiple Inputs Faculty of
Engineering

 Extension to multiple inputs

◆ A gate can be extended to multiple inputs.
» If its binary operation is commutative and associative.
◆ AND and OR are commutative and associative.
» OR
− x+y = y+x
− (x+y)+z = x+(y+z) = x+y+z
» AND
− xy = yx
− (x y)z = x(y z) = x y z

ECE 203 Digital Logic Design Ch2-43

Multiple Inputs Faculty of
Engineering

 NAND and NOR are commutative but not associative → they

are not extendable.

Figure 2.6 Demonstrating the nonassociativity of the NOR operator;

(x ↓ y) ↓ z ≠ x ↓(y ↓ z)
ECE 203 Digital Logic Design Ch2-44
Multiple Inputs Faculty of
Engineering

◆ Multiple NOR = a complement of OR gate, Multiple NAND = a

complement of AND.
◆ The cascaded NAND operations = sum of products.
◆ The cascaded NOR operations = product of sums.

Figure 2.7 Multiple-input and cascaded NOR and NAND gates

ECE 203 Digital Logic Design Ch2-45

Multiple Inputs Faculty of
Engineering

◆ The XOR and XNOR gates are commutative and associative.

◆ Multiple-input XOR gates are uncommon?
◆ XOR is an odd function: it is equal to 1 if the inputs variables have an
odd number of 1's.

Figure 2.8 3-input XOR gate

ECE 203 Digital Logic Design Ch2-46

Positive and Negative Logic
Faculty of
Engineering

 Positive and Negative Logic

◆ Two signal values <=> two logic values
◆ Positive logic: H=1; L=0
◆ Negative logic: H=0; L=1
 Consider a TTL gate
◆ A positive logic AND gate
◆ A negative logic OR gate
◆ The positive logic is used in this book

Figure 2.9 Signal assignment and logic polarity

ECE 203 Digital Logic Design Ch2-47
Positive and Negative Logic
Faculty of
Engineering

ECE 203 Figure 2.10 Demonstration of positive and negative Digital

logic Logic Design Ch2-48
2.9 Integrated Circuits
Faculty of
Engineering

Level of Integration
 An IC (a chip)
 Examples:
◆ Small-scale Integration (SSI): < 10 gates
◆ Medium-scale Integration (MSI): 10 ~ 100 gates
◆ Large-scale Integration (LSI): 100 ~ xk gates
◆ Very Large-scale Integration (VLSI): > xk gates
 VLSI
◆ Small size (compact size)
◆ Low cost
◆ Low power consumption
◆ High reliability
◆ High speed

ECE 203 Digital Logic Design Ch2-49

Digital Logic Families
Faculty of
Engineering

 Digital logic families: circuit technology

◆ TTL: transistor-transistor logic (dying?)
◆ ECL: emitter-coupled logic (high speed, high power consumption)
◆ MOS: metal-oxide semiconductor (NMOS, high density)
◆ CMOS: complementary MOS (low power)
◆ BiCMOS: high speed, high density

ECE 203 Digital Logic Design Ch2-50

Digital Logic Families
Faculty of
Engineering

 The characteristics of digital logic families

◆ Fan-out: the number of standard loads that the output of a typical gate
can drive.
◆ Power dissipation.
◆ Propagation delay: the average transition delay time for the signal to
propagate from input to output.
◆ Noise margin: the minimum of external noise voltage that caused an
undesirable change in the circuit output.

ECE 203 Digital Logic Design Ch2-51

CAD
Faculty of
Engineering

 CAD – Computer-Aided Design

◆ Millions of transistors
◆ Computer-based representation and aid
◆ Automatic the design process
◆ Design entry
» Schematic capture
» HDL – Hardware Description Language
− Verilog, VHDL
◆ Simulation
◆ Physical realization
» ASIC, FPGA, PLD

ECE 203 Digital Logic Design Ch2-52

Chip Design
Faculty of
Engineering

 Why is it better to have more gates on a single chip?

◆ Easier to build systems
◆ Lower power consumption
◆ Higher clock frequencies

 What are the drawbacks of large circuits?

◆ Complex to design
◆ Chips have design constraints
◆ Hard to test

 Need tools to help develop integrated circuits

◆ Computer Aided Design (CAD) tools
◆ Automate tedious steps of design process
◆ Hardware description language (HDL) describe circuits
◆ VHDL (see the lab) is one such system
ECE 203 Digital Logic Design Ch2-53