FMPM Module 2

SYLLABUS:
Introduction to 8085 Assembly Language Programming: The 8085 Programming Model,
Instruction Classification, Instruction, Data and Storage, Writing assembling and Execution of
a simple program, Overview of 8085 Instruction Set, Writing and Assembling Program.
Introduction to 8085 Instructions: Data Transfer Operations, Arithmetic Operations, Logic
Operation, Branch Operation, Writing Assembly Languages Programs, Debugging a Program.

THE 8085 PROGRAMMING MODEL

8085 programming model includes six registers, one accumulator, and one flag register,
as shown in diagram below.
In addition, it has two 16-bit registers: the stack pointer and the program counter. They
are described briefly as follows :

Accumulator A. (8) Flag Register

B (8) C (8)
D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

8 Lines Bidirectional 16 Lines unidirectional

Register Diagram
Registers
The 8085 has six general-purpose registers to store 8-bit data; these are identified as B(8
bit),C(8 bit),D(8 bit),E(8 bit),H(8 bit), and L(8 bit) as shown in the figure. They can be combined
as register pairs – BC, DE, and HL – to perform some 16-bit operations. The programmer can
use these registers to store or copy data into the registers by using data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations. The result
of an operation is stored in the accumulator. The accumulator is also identified as register A.
Flag Register

Format of flag registers of 8085 register

The ALU includes five flip-flops, which are set or reset after an operation according to
data conditions of the result in the accumulator and other registers.
They are called Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
a) Carry Flag (CY)
 If an arithmetic operation is performed in ALU, then it may generate carry from D7 bit
to next stage, then CY flag is set to 1 which act as 9th bit of the result of addition and
borrow flag for the subtraction.
 If there is no carry/borrow out of the most significant bit D 7 of the result, then the CY
flag is reset.
b) Parity Flag (P)
 This bit is used to indicate parity of the result i.e. numbers of one’s. If the result
contains even numbers of one’s this flag is set to 1.
 If the result of operation contains odd numbers of the one’s then this flag is reset to 0.
c) Auxiliary Cary Flag (AC)
 If an arithmetic or logical operation is performed in the ALU then it may generate a
carry from D3 to D4 then AC flag is set to 1 else reset to 0
i.e. carry is generated from lower nibble to higher nibble.
 This is not general purpose flag, it is used only by microprocessor to perform binary
to BCD conversion using DAA(Decimal Adjust Accumulator) instruction.
d) Zero Flag (Z)
 If the result of an arithmetic or logical operation performed by the ALU is 0, then Z flag
is set to 1 else reset 0.
 When flag is set then the result i.e. the content of A(accumulator) register is 0.
e) Sign Flag (S)
 In sign magnitude number, the sign of the number is indicated by most significant bit
D7 of 8 bit number.
 The sign Flag is a exact replica of the D7 bit to indicate that the result of operation
performed by the ALU is negative.
 So, when this flag is negative this flag is set to 1 else reset to 0
Source: https://youtu.be/OzZNIxR1eSg

Program Counter (PC)

 This 16-bit register deals with sequencing the execution of instructions. This register
is a memory pointer.
 Memory locations have 16-bit addresses, and that is why this is a 16-bit register.
 The microprocessor uses this register to sequence the execution of the instructions.
 The function of the program counter is to point to the memory address from which the
next byte is to be fetched.
 When a byte (machine code) is being fetched, the program counter is incremented by
one to point to the next memory location.
Stack Pointer (SP)
 The stack pointer is also a 16-bit register used as a memory pointer.
 It points to a memory location in R/W memory, called the stack.
 The beginning of the stack is defined by loading 16-bit address in the stack pointer.
INSTRUCTION
 An instruction is a command to the microprocessor to perform a given task on a
specified data.
 Each instruction has two parts: one is task to be performed, called the operation
code (op-code), and the second is the data to be operated on, called the operand.
 The operand (or data) can be specified in various ways.
 It may include 8 bit or 16 bit data, an internal register, a memory location, or 8-bit 16
bit address.
 In some instructions, the operand is implicit.
The 8085 instruction set is classified into the following three groups according to length :
1. 1-byte instructions
2. 2-byte instructions
3. 3-byte instructions
 In the 8085, "byte" is synonymous because it is an 8-bit microprocessor.
a) One-Byte Instructions
 A one-byte instruction includes the op-code and operand in the same byte.
 Operand(s) are internal register and are coded into the instruction.
 One byte instructions require only one memory location to store in memory.
Examples
Instruction 1 : MOV B, A
0 1 0 0 0 1 1 1
Operation Code for MOV Code of destination Code of Source operand A
Operand B
 Hence, the op-code of above instruction in binary is 01000111 i.e. 47 H
i.e. one byte only.
 Where first two bits i.e. D7 and D6 indicate operation to be performed is MOVE i.e. 01.
 Next three bits i.e. D5, D4, D3 are the binary code of destination register B i.e. 000.

 Last three bits i.e. D2, D1, D0 are the binary code of source register A
i.e. 111.
Instruction 2 : SUB B
1 0 0 1 0 0 0 0
Operation code for SUB Code of Source Operand B
 Hence, the op-code of above instruction in binary is 10010000 i.e. 90 H i.e. one byte
only.
 Where first five bit i.e. D7 to D3 indicates operation to be performed is subtraction i.e.
10010.
 Last three bits i.e. D2, D1, D0 are the binary code of destination register B i.e. 000.

b) Two-Byte Instructions
 In a two-byte instruction, the first byte specifies the operation code and the second
byte specifies the operand.
 Source operand is a data byte immediately following the op-code.
 Two byte instructions require two consecutive memory locations to store in memory.
Examples
Instruction 1 : MVI A, 40 H
First byte of the instruction 3E H
0 0 1 1 1 1 1 0
Operation code for MVI A

Second byte of the instruction 40H

0 1 0 0 0 0 0 0
8 bit immediate data
 Hence, the op-code of above instruction in binary is 00111110 i.e. 3E H
i.e. first byte.
 Where second byte is nothing but the immediate data 40H.
Instruction 2 : IN 90H
First byte of the instruction DB H
1 1 0 1 1 0 1 1
Operation code for IN
Second byte of the instruction 90H
1 0 0 1 0 0 0 0
8 bit port address
 Hence, the op-code of above instruction in binary is 11011011 i.e. DB H
i.e. first byte.
 Where second byte is 8 bit port address i.e. 90H.
c) Three-Byte Instructions
 In a three-byte instruction, the first byte specifies the op-code, and the following two
bytes specify the 16-bit address or 16-bit data.
 The second byte is the low-order address or data and the third byte is the high-order
address or data.
 Three byte instructions require three consecutive memory locations to store in
memory.
Examples
Instruction 1 : STA D000 H
First byte of the instruction 32H
0 0 1 1 0 0 1 0
Operation code for STA

Second byte of the instruction 00H

0 0 0 0 0 0 0 0
LSB of the 16 bit address

Third byte of the instruction D0H

 1 1 0 1 0 0 0 0
MSB of the 16 bit address
 Hence, the op-code of above instruction in binary is 00110010 i.e. 32 H
i.e. first byte.
 Where second byte is LSB of the memory address 00H and third byte is MSB of the
memory address D0H
Instruction 2 : LXI H, 9000H
First byte of the instruction 21H
0 0 1 0 0 0 0 1
Operation code for LHLD

Second byte of the instruction 00H

0 0 0 0 0 0 0 0
LSB of the 16 bit address

Third byte of the instruction 90H

1 0 0 1 0 0 0 0
MSB of the 16 bit address
 Hence, the op-code of above instruction in binary is 00101001 i.e. 21 H
i.e. first byte.
 Where second byte is LSB of the 16 bit immediate data 00H and third byte is MSB of
the 16 bit immediate data D0H.
ADDRESSING MODES
 Addressing mode is defined as a method of specifying operand registers or address
of operand in memory.
 There are five ways i.e. addressing mode to specify operand in 8085 microprocessor
as given below :
1. Register addressing mode.
2. Immediate addressing mode.
3. Direct addressing mode.
4. Indirect addressing mode.
5. Implied or implicit addressing mode.
REGISTER ADDRESSING MODE
 In this addressing mode, the data is specified in the general purpose registers.
 Op-code of the instruction itself specifies the operation and operand in the term of
general purpose registers.
 Normally the length of instruction in this addressing mode is one byte.
Examples
a) MOV B, A Copy the content of A register to B register where source and destination
both are registers.
b) ORA D OR the contents of D register with A where in instruction only one operand
register D is specified, the other operand is by default A register.
c) INR A Increment A register by one where this instruction has only one Operand A
accumulator.
IMMEDIATE ADDRESSING MODE
 In this addressing mode, the 8 or 16 bit data is the part of instruction means
immediately given in the instruction itself.
 The length of instruction in this addressing mode is either two or three bytes.
 Where first byte is always op-code, second byte is 8 bit data for two byte instruction.
 In three byte instruction, first byte is op-code, second byte is LSB and third byte is
MSB of 16 bit data.
Examples
a) MVI B, 44 H loads B register with immediate data 44H where source is immediate 8
bit number 44H and destination is B register.
b) LXI B, D000H load 16 bit immediate data D000H in register pair BC where source is
immediate 16 bit number D000H and destination is register pair BC.
DIRECT ADDRESSING MODE
 In this addressing mode, the 8 bit or 16 bit direct address of the operand is a specified
in the instruction where data is stored or is to be stored.
 The length of the instruction in this addressing mode is either two or three bytes.
 For two byte instruction, first byte is op-code of the instruction and second byte is
address of the port from/to data is to be read/ write.
 For three byte instruction, first byte is op-code and next two bytes is 16 bit memory
address of the operand from/to data is to read/write.
 While storing three byte instruction, first we must store op-code, lower byte of 16 bit
address and lastly higher byte 16 bit address.
Examples
a) IN 90H Read data from port whose address is 90H and load it in A register where
source is port address 90H and destination is accumulator A.
b) LDA D000H Read number from memory location D000H and load it in Accumulator
where source is the memory location whose address is D000H and destination is
accumulator A.
INDIRECT ADDRESSING MODE
 In this addressing mode, the address of the operand is stored in register pair, not
specified in the instruction.
 The instruction points where address of data is stored, thus address of the data is
indirectly specified.
  The length of instruction in this addressing mode is one byte.
Examples
a) MOV B,M This instruction load data from memory location whose address is specified
in HL register pair to B register.
b) STAX D This instruction load data from memory location whose address is specified
in DE register pair to accumulator A.
IMPLIED OR IMPLICIT ADDRESSING MODE
 In this addressing mode, the operand is not specified in instruction, but it is supposed
to be available in accumulator.
 The length of the instruction in this addressing mode is one byte.
Examples
a) DAA This instruction adjusts result of binary addition to BCD for that result is
supposed to be available in accumulator.
b) RAR This instruction rotate the content of accumulator to right, hence RAR operate
only on accumulator.

Source: https://youtu.be/mHG5z6KGpGg
DATA TRANSFER GROUP
1. MOV Rd, Rs
Rd = destination register
Rs = Source register
Description
 This instruction copies data from source register Rs to destination register Rd without
modifying source register Rs.
 The Rs and Rd can be any general purpose register like A,B,C,D,E,H,L.
Operation performed : Rd  Rs
Flags affected : None
Length in byte : One
Addressing mode : Register
Machine cycle : 1M/C [op-code fetch]
T-state : 4T
Examples
MOV H,A HA
MOV A,L A L
MOV B,C BC
2. MOV Rd, M and MOV M, Rs
Rd = destination register
Rs = Source register
M = Memory pointer [HL]
Description
 MOV Rd, M instruction copies data from memory location pointed by HL register pairs
to destination Rd without modifying source memory location.
 MOV M, Rs instruction copies the data from the source register Rs to memory location
pointed by HL register pair without modifying source register Rs.
 The Rs and Rd can be any general purpose registers like A,B,C,D,E,H,L.
 BEFORE USING THIS INSTRUCTION the register pair HL must be loaded with valid
address of the data byte because M always refers HL register HL register pair for the
memory address.
Operations performed : Rd  M or Rd  [HL] for MOV Rd, M
: M  Rs or [HL]  Rs or [HL]  Rs for MOV M, Rs
Flags affected : None
Length in byte : One
Addressing Mode : Indirect
Machine cycle : 2M/C [op-code fetch + memory read] for MOV Rd, M
: 2M/C [op-code fetch + memory wire] for MOV M, Rs
T – state : 4 + 3 = 7 t for both instructions
Examples
Assume HL contains D000H
MOV B,M : copies the contents of the memory location D000H pointed
by HL to Register pair to destination register B.
MOV M,C : copies the contents of the source register C to memory
location D000H Pointer BY HL register pair seven
instructions for MOV Rd, M.
3. MVI Rd, 8 bit data and MVI M, 8 bit data
Description
 MVI Rd, 8 bit data instruction copies the 8 bit immediate data specified in the
instructions to destination register Rd.
 MVI M, 8 bit data instruction copies the 8 bit immediate data to memory location
pointed by HL register, hence this instruction HL must be located with valid address
of the memory locations.
 The Rd can be any general purpose register like A,B,C,D,E,H,L.
Operation performed : Rd  8 bit immediate data for MVI Rd, 8 bit data
: M  8 bit immediate data or [HL]  8 bit data for MOV M,
8 bit data
Flags affected : None
Length in byte : Two
Addressing Mode : Immediate for MVI Rd, 8 bit data
: Immediate indirect for MVI M, 8 bit data
Machine cycle : 2M/C [op-code fetch + memory read] for MVI Rd,
8 bit data
: 3 M/C [op-code fetch + memory read + memory write] for
MVI M, 8 bit
T–State : 4+3 =7 for MVI Rs, 8 bit data
: 4+3 +3=10 T for MVI M, 8 bit data
4. LXI Rp , 16 bit immediate data Rp= register pair
Description
 This instruction copies the 16 bits immediate data specified in the instruction to
destination register Rp.
 The Rp can be a pair of general purpose register like BC,DE,HL and SP.
Operation performed : Rp  16 bit immediate data
Flags affected : None
Length in byte : Three
Addressing mode : Immediate
Machine cycle : 3 M/C [op-code fetch + memory read + memory read]
T–state : 4 + 3 +3 =10 T
Examples
LXI H, 1234H : copy 16 bit immediate data 1234H to register pair HL where
12 copied to H and 34 to L after execution.
LXI H, 3000H : copy 16 bit immediate data 3000 to stack pointer SP.
5. LDA 16 bit address
Description
 This instruction copies a byte from memory location specified in the instructions to
accumulator i.e. A register.
 The 16 bit address of the memory location is specified along with the instructions.
Operations performed : A[16 bit address ]
Flags affected : None
Length in byte : Three
Addressing mode : Direct
Machine cycle : 4M/C [op-code fetch + memory read + memory read +
memory write]
T-state : 4+3+3+3=13T
Examples
LDA D100H : copies the contents of memory location D100H to accumulator i.e. A register.
6. STA 16 bit address
Description
 This instruction copies a byte from accumulator i.e. A register to memory location
specified in the instructions.
 The 16 bit address of the memory location is specified along with the instructions.
Operations performed : [16 bit address ]  A
Flags affected : None
Length in byte : Three
Addressing mode : Direct
Machine cycle : 4M/C [op-code fetch + memory read + memory read +
memory write]
T–state : 4+3+3+3=13T
Examples
STA D100H : copies the contents of accumulator i.e. A register to memory location D100H
7. LHLD 16 bit address
Description
 This instruction copies contents of two consecutive memory location to H and L
registers without modifying the contents of memory location.
 The 16 bit address of the first memory location is specified along with the instructions.
 The content of the first memory location is copied to L register and contents of next
memory location [address + 1] copied to H register.
Operation performed : L  16 bit address
: H  16 bit address + 1
Flags affected : None
Length in byte : Three
Addressing mode : Direct
Machine cycle : 5M/C [op-code fetch + memory read + memory read +
memory read + memory read]
T-state : 4+3+3+3+3 = 16T
Examples
LHLD D100 H : copies the contents of memory location D100H to L register and D101 H to H
register.
8. SHLD 16 bit address
Description
 This instruction copies contents of H and L registers to two consecutive memory
location without modifying the contents of H and L register.
 The 16 bit address of the first memory location is specified along with the instructions
 The of L register is copied to first memory location specified and content of H register
is copied to next memory location [address + 1 ].
Operation performed : 16 bit address  L
: [16 bit address + 1]  H
Flags affected : None
Length in byte : Three
Addressing mode : Direct
Machine cycle : 5M/C [op-code fetch+ memory read + memory read
+ memory write + memory write]
T-state : 4+3+3+3+3 = 16T
Examples
SHLD D100 H : copies the contents of reg. L to memory location D100H and reg. H to memory
location D101 H.
9. LDAX Rp
Description
 The instruction copies the content of the memory location specified in the register pair
Rp to accumulator i.e. A register without modifying the content of memory location.
 The 16 bit address of the location must be specified in register pair before the
execution of the instruction.
 Register pairs are BC and DE only.
Operation performed : A  Rp
Flags affected : None
Length in byte : One
Addressing mode : Indirect
Machine cycle : 2 M/C [op-code fetch + memory read]
T–state : 4 + 3 = 7T
Examples
Assume BC contains memory address C000H.
LDAX B : Copies the contents of memory location whose address is specified in BC register
pair to A accumulator.
10. STAX Rp
Rp = register pair
Description
 The instructions copies the content of accumulator i.e. A register to the memory
location specified register pair Rp without modifying the content of accumulator.
 The 16 bit address of the memory location must be specified in register pair before
the execution of this instruction.
  Register pairs are BC and DE only.
Operations performed : Rp A
Flags affected : None
Length in byte : One
Addressing mode : Indirect
Machine cycle : 2M/C [op-code fetch + memory write]
T-state : 4+3=7T
Examples
Assume BC contents memory address C000H.
STAX B : Copies the contents of accumulator A to the memory location whose address is
specified in BC register pair.
11. XCHG
Description
 This instructions exchanges the content of HL register pair with DE register pair.
 Hence this instruction exchanges the content of H registers with D register and the
contents of L register with E register.
 This instruction uses w and z register internally to perform exchange between HL and
DE registers pairs.
Operations performed : HD and LE
Flags affected : None
Length in byte : One
Addressing mode : Implicit or Implied
Machine cycle : 1 M/C [op-code]
T-state : 6T
Examples
Suppose
HL = 1234H and DE = 4321H then
After the execution of XCHG
HL = 4321 H and DE = 1234 H
12. IN 8 bit port address
Description
 This instruction copies the 8 bit data from I/O port whose 8 bit address is specified
along with the instruction to accumulator.
 The 8 bit port address is specified along with the instruction.
 In this instruction the address of port is 8 but microprocessor transfer
16 bit address on the address list.
 The 8 bit port address is transferred on lower order address bus A0 – A7 as well as
on higher order addition bus A8 – A15 and port is accessed.
Operation performed : A  8 bit port address
Flags affected : None
Length in byte : Direct
Addressing mode : Direct
Machine cycle : 3M/C [op-code fetch + memory read + I/O read]
T-state : 4 + 3 + 3 = 10 T
Examples
IN 80H : copies 8 bit data from I/O port whose 80H to accumulator.

13. OUT bit port address

Description
 This instruction copies the 8 bit data from accumulator to I/O port whose 8 bit address
is specified along with instruction.
 The 8 bit I/O port address is specified with the instructions.
 In this instruction the address of port is 8 bit but microprocessor transfer 16 bit address
on the address line.
 The 8 bit port address is transferred on the lower order address bus A0–A7 as well
as on higher order address bus A8-A15 and port is accessed.
Operation Performed : [8 bit port address]A
Flags affected : None
Length in byte : Two
Addressing mode : Direct
Machine cycle : 3 M/C[op-code fetch + memory read + I/O write]
T-state : 4 + 3 + 3 = 10T
Examples
OUT 80H : Copies 8 bit data from accumulator to I/O port address is 80H.
Program 1 : Program to load A with 30H, B with 44H, H with 93H.
Now, here three general purpose registers are required to store data bytes. Hence
immediate addressing mode instructions can be used to load registers with proper data.
Here data is 8 bit, so you can use immediate addressing mode instruction MVI Rd, 8-bit
data in a sequence in which you want to load register.
Algorithm
 Step 1 : load A with 30H
 Step 2 : load B with 44H
 Step 3 : load H with 93H
 Step 4 : Stop

Start

Load A register with data byte 30H

Load B register with data byte 44H

Load H register with data byte 93H

Stop
Program
MVI A, 30H ; Load A with 30H
MVI B, 44H ; Load B with 44H
MVI H, 93H ; Load H with 93.H
HLT or RST 1 ; Stop or restart
After the execution of the above
program, the registers A, B and H will get
loaded with 30H, 44H and 93H. At the Start
end of the above program you can use
either HLT or RST 1 instruction. If you
have used HLT instruction, then after the Load A register with data stored in D000H
execution of the program, the
microprocessor will be halted. In this
case we cannot check the result of the Copy data byte from A reg. to B reg.
program in the registers. Hence, your
data and result loaded in the register will
be lost due to the execution of monitor Load A register with data stored in E000H
program.
Hence, instead of using HLT
Copy data byte from A reg. to H reg.
instruction, it is the best way to use RST
n instruction. After the execution of the
RST instruction, the contents of the all
register will be restored depending on the Stop
kit manufacturer so that you can check
the contents of the desired register.
Program 2 : Load B, H with data byte from the memory locations D000H and E000H.
Here, the data bytes are stored in the memory locations D000H and E000H respectively.
Now you can use direct addressing mode instruction like LDA or MOV Rs, M, but in this case,
you have to use LDA not MOV Rd, M because data bytes are not stored at consecutive
memory locations.

Assume memory locations contains byte as given below :

D000H = 35H
E000H = 98H
Algorithm
 Step 1 : Load B with data byte from memory location D000H
 Step 2 : Load H with data byte from memory location E000H
 Step 3 : Stop
Program
LDA D000H ; Load byte from D000H to Accumulator
MOV B, A ; Copy it to B i.e. B = 35H
LDA E000H ; Load byte from E000H to Accumulator
MOV H, A ; Copy it to H i.e. H = 98H
HLT ; Stop
After the execution of the above program, the microprocessor loads the content of two
memory locations D000H and E000H to B and H respectively.
Program 3 : Load B, A with data byte from the consecutive memory locations D000H
and D001H
In this case, the data bytes are
stored in two consecutive memory Start
locations D000H and D001H, hence
you can use LDA or MOV Rd, M. When
we use memory pointer M, the HL Initialize memory pointer using HL register
register pair must be loaded with
proper address.
Assume memory locations Copy data byte from memory to B reg.
contents data given below :
D000H = 64H Increment memory pointer by 1
D001H = 85H
Algorithm :
 Step 1 : Initialize memory Copy data byte from memory to C reg.
pointer.
 Step 2 : Load byte from
memory to B register. Stop
 Step 3 : Increment memory
pointer by 1.
 Step 4 : Load byte from memory to C register.
 Step 5 : Stop.
Program
LXI H, D000H ; Initialize memory pointer using HL reg. pair
MOV B, M ; Load byte from D000H to B reg. i.e. 64H
INX H ; Increment memory pointer by 1
MOV C, M ; Load byte from D001H to C reg. i.e. 85H
HLT ; Stop
After the execution, the contents of the memory locations D000H and D001H will be
loaded in B and C registers.
Program 4 : Load D and E with data bytes from the consecutive memory locations
D000H and D001H
In this case, you can use direct
addressing mode instruction i.e. LHLD to
load register pair directly with the contents Start
of two consecutive memory locations.
Assume memory locations contents
data given below : Load HL register pair with data stored
D000H = 64H at memory locations D000H and D001H
D001H = 85H
Algorithm Exchange the HL register pair with BC
 Step 1 : Load register pair with the
data bytes stored at two memory
locations.
Stop
 Step 2 : Stop
Program
LHLD D000H ; L <- D000H and H <- D001H
 XCHG ; Load DE with HL
HLT ; Stop
After the execution, the DE will get loaded with 8546H from two consecutive memory
locations D000H and D001H.
ARITHMETIC GROUP INSTRUCTIONS
2.1 ADDITION INSTRUCTION
1. ADD Rs/ADC Rs
Rs = Source register
Description
 The ADD Rs instruction adds the content of source register Rs and accumulator and
store result of addition in accumulator, hence accumulator gest modified.
 The ADC Rs instruction adds the content of source register Rs, accumulator and Cy
flag and store result in the accumulator, hence accumulator gets modified.
 The source register Rs can be any general purpose register like A,B,C,D,E,H,L.
Operation performed : A A–Rs for ADD Rs
: A A+Rs+ Cy for ADC Rs
Flags affected : All flags
Length in byte : One
Addressing mode : Register
Machine cycle : 1M/C[op-code fetch]
T-state : 4T
Examples
Assume A =10H and C-20H
ADD C ; Adds the contents of C register and accumulator and store result 30H
in accumulator A
ADC H ; Adds the contents of H register, accumulator and Cy flag and store
result 76H in accumulator.
2. ADD M/ADC M
M = memory pointer
Description
 The ADD M instruction adds the contents of memory location pointed by HL, register
pair and accumulator and store result of addition in accumulator , hence accumulator
gets modifies.
 The ADC M instruction adds the contents of memory location pointed by HL register
pair, accumulator and Cy flag and store in the accumulator, hence accumulator gets
modified.
 The 16 bit address of the memory location must be loaded in register pair HL before
the execution of this instruction.
Operation performed : AA+[HL]or AA+M for ADD M
: AA+[HL]+Cy or A A+M+ Cy for ADC M
Flags affected : All flags
Length in byte : One
Addressing mode : Indirect
Machine cycle : 2 M/C [op-code fetch + memory read]
T-State : 4+3=7T
Examples
Assume A = 10H, HL = D000H and D000H contains 45H
ADD M ; Adds the contents of memory location pointed by HL register pair and
accumulator and; store result 55H in accumulator A
Assume A=30H,HL=D100H,Cy=1 and D100H contains 70H
ADC M ; Adds the contents of memory location pointed by HL register pair,
accumulator and Cy ; flag and store result A0H in accumulator.
3. ADI 8 bit immediate data / ACI 8 bit immediate data
Description
 The ADI 8 bit data instruction adds the contents of accumulator and 8 bit immediate
data specified in the instruction and store result of addition in accumulator, hence
accumulator gets modified.
 The ACI 8 bit data instruction adds the contents of accumulator,8 bit immediate data
specified in instruction and Cy flag and store result in the accumulator, hence
accumulator gets modified.
Operation performed : A A+8 bit immediate data for ADI 8 bit big data
: AA+8 bit immediate data +Cy for ACI 8 bit data
Flags affected : All flags
Length in byte : Two
Addressing mode : Immediate
Machine cycle : 2 M/C [op-code fetch + memory read]
T-State : 4+3=7T
Examples
Assume A = 10H
ADI 90H ; Adds the contents of accumulator and 8 bit data 90H and store result
A0H in accumulator A
Assume A = 30H and Cy = 1
ACI 80H ; Adds the contents of accumulator 8 bit data 80H and CY flag and store
result B 1H in accumulator.
4. DAD Rp
Description
 The DAD Rp instruction adds the contents of specified source register pair Rp with
HL register pair and store result of addition in HL register pair,hence HL register pair
gets modified.
 The source register pair Rp can be any registers pair like BC,DE,HL,SP.
 The register pair HL will acts as a 16 bit accumulator where result of 16 bit addition is
stored after the execution of DAD instruction.
Operation performed : HLHL+Rp
Flags affected : Only Cy flag
Length in byte : One
Addressing mode : Register
Machine cycle : 3 M/C [op-code fetch + idle m/c cycle + idle mc cycle]
T–State : 4 + 3 + 3 = 10 T
Examples
Assume HL = 10H and BC = 0202H
DAD B ; Adds the contents of BC register pair with HL register and store result
1212H in HL; register pair
Assume HL = 3333H and SP = 7777H
DAD Sp ; Adds the contents of Stack pointer Sp with HL register pair and store result
AAAAH in ; HL register pair.
Program 1 : Load B and C with data bytes 65H and 87H. Add B with C, and store result
in B.
All arithmetic operations, two operands Start
are required, in which one operand must be
in accumulator and other may be in register.
In this case, two operands are available in Load B register first number
B and C register. Hence, you have to move
the content of either B or C in accumulator
and then addition can be performed. Load C register with second number
Algorithm
 Step 1 : Load B reg. with 65H Copy first number B from reg. to A reg.
 Step 2 : Load C reg. with 87H
 Step 3 : Load accumulator with B
Add first number with second
reg.
number
 Step 4 : Add A reg. with B reg.
 Step 5 : Store result in B reg. Store result in B register
 Step 6 : Stop

Stop
Program :
MVI B, 65H ; Load B reg.
with 65H
MVI C, 87H ; Load C reg. with 87H
MOV A, B ; Load A reg. with B reg.
ADD C ; A reg. <- A reg. + B reg.
MOV B, A ; Store result in B reg.
HLT ; Stop
After the execution, the result of addition ECH will be stored in B register.
Program 2 : Add the contents of two memory locations D000H and D001H. Store result
in memory location D002H.
Here, load the numbers from both memory locations in internal registers and perform
addition operation. Finally, store result back to new memory location.
Assume memory locations contents data given below :
 Start

Load B register first number stored in

memory location D000H

Copy first number to B register

Load A register with second number

stored in memory location D001H

Add first number with second number

Store result in memory location D002H

Stop

D000H = 64H
D001H = 85H
Algorithm
 Step 1 : Load first number from memory location D000H
 Step 2 : Load second number from memory location D001H
 Step 3 : Add first number with second number
 Step 4 : Store result to memory location D002H
 Step 5 : Stop
Program
LDA D000H ; Load first number from D000H in A reg.
MOV B, A ; Copy it to B reg.
LDA D001H ; Load second number from D001H in A reg.
ADD B ; A reg. <- A reg. + B reg.
STA D002H ; Store result at memory location D002H
HLT ; Stop
After the execution, you can check the result of addition in memory location D002H.
2.2 Subtraction Instructions
1. SUB Rs/SBB Rs
Rs = Source register
Description
 The SUB Rs instruction subtracts the contents of source register Rs from accumulator
and store result of subtraction in accumulator, hence accumulator gest modified.
 The SBB Rs instruction subtracts the content of source register Rs and Cy flag from
accumulator and store result in the accumulator, hence accumulator gets modified.
  The source register Rs can be any general purpose registers like A,B,C,D,E,H,L.
 The Cy flags will acts as barrow flag for the subtraction.
Operation performed : AA–Rs for SUB Rs
: AA–Rs-Cy for SBB Rs
Flags affected : All flags
Length in byte : One
Addressing mode : Register
Machine cycle : 1 M/C [op-code fetch]
T-State : 4T
Examples
Assume A = 40H and C = 20H
SUB C : subtracts the contents of C register from accumulator and store result
20H in accumulator A.
Assume A = 20H and C = 40H
SUB C ; subtracts the contents of C register from accumulator and store result
E0H set 1.
Assume A = 12H,H = 04H and Cy = 1
SBB H ; Subtract the contents of H register and Cy flag from accumulator and
store result 0DH in ; accumulator.
2. SUB M/SBB M
M = Memory pointer
Description
 The SUB M instruction subtracts the contents of memory location pointer by HL
register pair from accumulated and store result of addition in accumulator,hence
accumulator gets modified.
 The SBB M instruction subtracts the content of memory location pointed by HL
register pair and Cy flag from accumulator and store result of addition in
accumulator,hence accumulator gets modified.
 The 16 bit address of the memory location must be loaded in register pair HL before
the execution of this instruction.
Operation performed : AA-[HL] or AA-M for SUB M
: AA-[HL]-Cy or AA-M-Cy for SBB M
Flags affected : All flags
Length in byte : One
Addressing mode : Indirect
Machine cycle : 2 M/C [op-code fetch + memory read]
T-State : 4+3=7T
Examples
Assume A = 40H, HL = D000H and D000H contains 35H
SUB M ; Subtracts the contents of memory location pointed by HL register pair
and Cy flag fromaccumulator and store result EFH in accumulator which
is 2ndcomplement of 11H i.e. 11H[-17 in BCD].
3. SUI 8 bit immediate data/SBI 8 bit immediate data
Description
  The SUI 8 bit instruction subtracts the 8 bit immediate data specified in the instruction
from the contents of accumulator and store result of subtraction in accumulator,hence
accumulator gets modified.
 The SBI 8 bit data instruction subtracts the 8 bit immediate data specified in instruction
and Cy flag from the contents of accumulator and store in the accumulator, hence
accumulator gets modified.
Operation performed : A  A–8 bit immediate data for SUI 8 bit data
: A  A-8 bit immediate data – Cy for ACI 8 bit data
Flags affected : All flags
Length in byte : Two
Addressing mode : Immediate
Machine cycle : 2 M/C [op-code fetch + memory read]
T-State : 4+3=7T
Examples
Assume A = 10H
SUI 05H ; Subtracts 8 bit data 05H from the content of accumulator and store
result 0BH in accumulator A
Assume A = 90H and Cy = 1
SBI 80H ; Subtracts the 8 bit data 80H and Cy flag from the content of
accumulator and store result 0FH in accumulator.
Program 1 : Load B and C with data bytes 65H and 87H.Subtract B from C, and store
result in B.
In this case, two operands are available in B and C register. Hence, you have to move
the contents of C in accumulator and then subtract the contents of B register from it.
Algorithm
Step 1 : Load B reg. with 65H
Step 2 : Load C reg. with 87H
Step 3 : Load accumulator with C reg.
Step 4 : Subtract B reg. with A reg.
Step 5 : Store result in B register.
Step 6 : Stop
 Start

Load B register with first number

Load C register with second number

Copy first number from C reg. to A reg.

Subtract second number from first number

Store Result in B register

Stop

Program
MVI B, 65H ; Load B reg. with 65H
MVI C, 87H ; Load C reg. with 87H
MOV A, C ; Load A reg. with C. reg.
SUB B ; A reg.  A reg. - B reg.
MOV B, A ; Store result in B reg.
HLT ; Stop
After the execution, the result of addition 22H will be stored in B register.
Program 2 : Subtract the content of memory locations D001H from D00H. Store result
in memory location D002H.
Here, load the numbers from both the memory locations in internal registers and perform
subtraction operation. Finally, store result back to new memory location.
Assume memory locations contents data given below.
D000H = 85H and D001H = 20H
Algorithm
Step 1 : Load first number from memory location D000H
Step 2 : Load second number from memory location D001H
Step 3 : Subtract second number from first numbers.
Step 4 : Store result to memory location D002H.
Step 5 : Stop
Program
LDA D001H ; Load second number from D000H in A reg.
MOV B, A ; Copy it to B reg.
LDA D000H ; Load first number from D001H in A reg.
ADD B ; A reg. ←A reg. - B reg.
STA D002H ; Store result at memory location D002H
HLT ; Stop

Start

Load HL register pair

with first number
Load BC register pair with
second number
Subtract second number from first
number
Store result in HL
register pair

Stop

Before the execution of the above program, store both numbers in memory locations as
given above.
After the execution, you can check the result of subtraction in memory location D002H.
OTHER ARITHMETAIC INSTRUCTION
1. INR R/INR M
R = Register
M–Memory pointer [HL]
Description
 The INR instruction increments the contents of specified register R by 1 means it adds
1 to register R, hence R gets modified.
 The INR M instruction increments the contents of memory location pointed by HL
register pair by 1 means it adds the contents of memory location, hence memory
location gets modified.
 The register R can be any general purpose registers like A, B, C, D, E, H, L.
 Before the execution of the INR M instruction, the HL register pair must be loaded
with valid addition of the memory location where data is stored.
Operation performed : RR+1 forINR R
: MM+1 or [HL][HL]+1 for INR M
Flags affected : All flags except Cy flag
Length in byte : One
Addressing mode : Register for INR R
: Indirect for INR M
Machine cycle : 1 M/C [op-code fetch] for INR R
: 3 M/C [op-code fetch + memory read + memory write] for
INR M
T–State : 4T for INR R
: 4 + 3 + 3 = 10 T for INR M
Examples
Assume C = 10H
INR C ; Increment the contents of C register by 1;after the execution the
contents of C will be 11H
Assume HL = D200H and at memory location D200H contains 06H
INR M ; Increment the content of the memory location pointed by HL register
pair by 1 and memory location is updated with the result 07H after the
execution.
2. DCR R/DCR M
R = Register
M = Memory pointer[HL]

Description
 The DCR R instruction decrements the content of specified register R by 1 means it
subtracts 1 from register R, hence R gets modified.
 The INR M instruction decrements the content of memory location pointed by HL
register pair by 1 means it subtracts 1 to the contents of memory location, hence
memory location gets modified.
 The register R can be any general purpose register like A, B, C, D, E, H, L.
 Before the execution of the DCR R instruction, the HL register pair must be loaded
with valid address of the memory location where data is stored.

Operation performed : RR–1 for DCR R

: MM-1 or[HL][HL]-1 for DCR M
Flags affected : All flags except Cy flag
Length in byte : One
Addressing mode : Register for DCR R
: Indirect for DCR M
Machine cycle : 1 M/C [op-code fetch] for DCR R
: 3 M/C [op-code fetch + memory read + memory write] for
DCR M
T-State : 4T for DCR R
: 4 + 3 + 3 = 10 T for DCR M

Examples
Assume C = 10H
DCR C ; Decrement the contents of C register by 1,hence after the execution
the contents of C will be 0FH
Assume HL = D200H and at memory location D200H contains 06H
DCR M ; Decrement the contents of the location pointed by HL register pair by
1 and memory ; location is updated with the result 05H after the
execution.

10. INX Rp
Rp = Register pair
Description
 This instruction increments the contents of specified register Rp by 1 means it adds 1
to register pair Rp, hence Rp gets modified.
  The register pair Rp can be any register pairs like BC, DE, HL, Sp.
Operation performed : RpRp+1
Flags affected : None
Length in byte : One
Addressing mode : Register
Machine cycle : 1 M/C [op-code fetch]
T-State : 6T
Examples
Assume BC = 0010H
INX B ; Increment the contents of BC pair by 1,hence after the execution the
contents of BC will be 0011H
11. DCX Rp
Description
 This instruction decrements the content of specified register pair Rp by 1 means it
subtracts 1 from Register pair Rp, hence Rp gets modified.
 The register pair Rp can be any register pairs like BC, DE, HL, Sp.
Operation performed : RpRp-1
Flags affected : None
Length in byte : One
Addressing mode : Register
Machine cycle : 1 M/C [op-code fetch]
T-State : 6T
Examples
Assume BC = 0010H
DCX B ; Decrement the content of the BC register pair by 1, hence after the
execution the contents of BC will be 00FH
12. DAA (Decimal adjust Accumulator)
Description
 This instruction is used to convert the result of two addition of two packed BCD
numbers to a valid BCD number.
 DAA only works on accumulator A register.
 So, DAA instruction must be used immediately after the ADD/ADC/ADI/ACI
 Instructions.
 This is only the instruction that uses auxiliary carry AC flags to perform operation of
conversion of binary To BCD.
 The ADD/ADC/ADI/ACI instruction adds the two BCD number in hexadecimal format
and DAA instruction adds 6 to the higher nibble of A accumulator.

Operation performed : Binary Result in A BCD result in A

: If lower nibble of A>9 or AC=1 then A = A + 06
: If the higher nibble of A>9 or Cy =1 then A = A + 60
: If both above condition are satisfied then A = A + 66
Flags affected : All
Length in byte : One
Addressing mode : Implied or Implicit
Machine cycle : 1 M/C [op-code fetch]
T – State : 4T

Examples
If A = 99 BCD and B = 99 BCD
Then Add B 1001 1001 A = 99 BCD
+ 1001 1001 B = 99 BCD
0011 0010 A = 32H and Cy = 1, AC = 1

As per the working of microprocessor the above result is correct ,however for us its is not.
This is because the microprocessor has treated both the number during addition as
hexadecimal number.
Hence in above example after addition Carry and Auxiliary carry flags are set, therefore
DAA instruction adds 6 to higher as well as lower nibble of reg.A to get correct BCD result i.e
198 BCD of which 98 is in reg.A and Cy = 1 as given below :
0011 0010 A = 32H and Cy = 1, AC = 1
+ 0110 0110
1001 1000 = 98 in BCD form

Program 1 : Addition of two 2 digit BCD numbers

Assume two BCD numbers are 45 and
45. Now, these two number are BCD for us, Start
but the microprocessor treats these
numbers as binary numbers
i.e. hexadecimal numbers. When the Load A register first number
microprocessor adds these numbers, then
you will get result 8AH in A register which is
wrong. Practically, the result should be 90. Load B register with second number
Hence, the DAA instruction can be used to
correct or convert this result to proper BCD Add first number with second number
result. The function of DAA instruction is
discusses above.
Algorithm : Adjust result to BCD using DAA
Step 1 : Load A reg. with 45H
Step 2 : Load B reg. with 45H
Store result in memory location
Step 3 : Add A reg. with B reg.
Step 4 : Adjust result to proper BCD
Step 5 : Store result in B register. Stop
Step 6 : Stop
Program
MVI A, 65H ; Load A reg. with 45H
MVI B, 87H ; Load B reg. with 45H
ADD B ; A reg. <- A reg. + B reg.
DAA ; Adjust result to BCD
MOV B,A ; Store result in B reg.
HLT ; Stop
After the execution, the result of addition 90 will be stored in B register.
Program 2 : Addition of two BCD numbers stored at memory locations D00H and
D001H.Store result in memory location D002H.
Here, load the numbers from both the
memory locations in internal registers and Start
perform addition operation because any
arithmetic operation cannot perform on
memory directly. At least on operand must
Load A register with first number stored in
be in register. Finally, store back to new
memory location D00H
memory location.
Assume memory locations contents
data given below.
D005H = 45H and D001H = 45H Load B register with second number stored
Algorithm in memory location D001H
Step 1 : Load first BCD number from
memory location D00H
Add first number with second number
Step 2 : Load second BCD number from
memory location D001H
Step 3 : Add first number with second Adjust first number with second number
number
Step 4 : Adjust result to BCD
Step 5 : Store result to memory location Store Result in memory location D002H
D002H
Step 6 : Stop
Stop
Program
LDA D000H ; Load first number stored from D000H in A reg.
M0V B, A ; copy it B reg.
LDA D001H ; load second number from D001H in A reg.
ADD B ; A reg.  A reg. + B reg.
DAA ; Adjust result to BCD
STA D002H ; Store result at memory location D002H
HLT ; Stop
After the execution, you can check the result of addition in memory location D002H i.e.
90.
LOGIC GROUP INSTRUCTIONS
1. ANA Rs / ANA M
Rs = Source Register
M = Memory pointer
Description
 The ANA Rs instruction logically AND’s the content of source register Rs with
accumulator bit by bit i.e. D0 of source with D0 of A register and so on till D7 bit of
both operands.
 The result of ANDing is stored in accumulator, hence accumulator gets modified.
  The ANA M instruction logically AND’s the content of memory location pointed by HL
register pair with accumulator i.e. bit by bit and store result in the accumulator, hence
accumulator gets modified.
 The source register Rs can be any general purpose registers like A, B, C, D, E, F, L.
 Before the execution of ANA M instruction, the register pair HL must be loaded with
valid address of the memory location where source data is stored .
Operation Performed : A  A AND Rs
Flags Affected : S, Z, P are affected and Cy = 0 and AC = 1
Length on Byte : One
Addressing Mode : Register for ANA Rs
: Indirect for ANA M
Machine cycle : 1 M/C [op-code fetch] for ANA Rs
: 2 M/C [op-code fetch + memory read] for ANA M
T-State : 4T for ANA Rs
: 4+3=7T for ANA M
Examples
Assume A = 89H and C = 98 H
ANA C : AND’s the contents of C register with accumulator and store result 88H in accumulator
A ; Cy = 0 and Ac = 1
Assume A = 30H, HL = D200H and at memory location D200H = 40 H
ANA M : AND’s the contents of memory location pointed by HL register pair with accumulator;
and store result 00H in accumulator ; Cy = 0 and Ac = 1.
2. ANI 8bit immediate data
Description
 This instruction logically AND’s the 8 bit immediate data specified in the instruction
with accumulator bit by bit i.e. D0 of A register and so on till D7 bit of both operands.
 The result ANDing is stored in accumulator, hence accumulator gets modified.
Operation Performed : A  A AND 8 bit immediate data
Flags Affected : S, Z, P are affected and Cy = 0 and AC = 1
Length on Byte : Two
Addressing Mode : Immediate
Machine cycle : 2 M/C [op-code fetch + memory read]
T-State : 4+3=7T
Examples
Assume A = 89H
ANI 98H : AND’s the 8 bit immediate data with accumulator and store the result 88H in the
accumulator A ; Cy = 0 and AC = 1
3. ORA Rs / ORA M
Rs = Source Register
M = Memory pointer
Description
 The ORA Rs instruction logically OR’s the content of source register Rs with
Accumulator bit by bit i.e. D0 of source with D0 of A register and so on till D7 bit of
both operands.
 The result of ORing is stored in accumulator, hence accumulator gets modified.
  The ORA M instruction logically OR’s the content of memory location pointed by HL
register pair with accumulator i.e. bit by bit and store result in the accumulator, hence
accumulator gets modified.
 The source register Rs can be any general purpose registers like A, B, C, D, E, F, L.
 Before the execution of ORA M instruction, the register pair HL must be loaded with
valid address of the memory location where source data is stored.
Operation Performed : A  A OR Rs for ORA Rs
: A  A OR M or A  A OR [HL] for ORA M
Flags Affected : S, Z, P are affected and Cy = 0 and AC = 0
Length on Byte : One
Addressing Mode : Register for ORA Rs
: Indirect for ORA M
Machine cycle : 1 M/C [op-code fetch] for ORA Rs
: 2 M/C [op-code fetch + memory read] for ORA M
T-State : 4T for ORA Rs
: 4+3=7T for ORA M
Examples
Assume A = 89H and C = 98 H
ORA C : OR’s the contents of C register with accumulator and store result 99H in accumulator
A.
; Cy = 0 and Ac = 0
Assume A = 30H, HL = D200H and at memory location D200H = 40 H
ORA M : OR’s the contents of memory location pointed by HL register pair with accumulator
and store result 70H in accumulator.
; Cy = 0 and Ac = 0

4. ORI 8bit immediate data

Description
 This instruction logically OR’s the 8 bit immediate data specified in the instruction with
accumulator bit by bit i.e. D0 of A register and so on till D7 bit of both operands.
 The result ORing is stored in accumulator, hence accumulator gets modified.
Operation Performed : A  A OR 8 bit immediate data
Flags Affected : S, Z, P are affected and Cy = 0 and AC = 0
Length on Byte : Two
Addressing Mode : Immediate
Machine cycle : 2 M/C [op-code fetch + memory read]
T-State : 4+3=7T
Examples
Assume A = 89H
ORI 98H : OR’s the 8 bit immediate data with accumulator and store the result 99H in the
accumulator A. Cy = 0 and AC = 1
5. XRA Rs / XRA M
Rs = Source Register
 M = Memory pointer
Description
 The XRA Rs instruction logically Ex-OR’s the content of source register Rs with
Accumulator bit by bit i.e. D0 of source with D0 of A register and so on till D7 bit of
both operands.
 The result of Ex-ORing is stored in accumulator, hence accumulator gets modified.
 The XRA M instruction logically Ex-OR’s the content of memory location pointed by
HL register pair with accumulator i.e. bit by bit and store result in the accumulator,
hence accumulator gets modified.
 The source register Rs can be any general purpose registers like A, B, C, D, E, F, L.
 Before the execution of XRA M instruction, the register pair HL must be loaded with
valid address of the memory location where source data is stored.
Operation Performed : A  A Ex-OR Rs for XRA Rs
: A  A Ex-OR M or A  A Ex-OR [HL] for XRA M
Flags Affected : S, Z, P are affected and Cy = 0 and AC = 0
Length on Byte : One
Addressing Mode : Register for XRA Rs
: Indirect for XRA M
Machine cycle : 1 M/C [op-code fetch] for XRA Rs
: 2 M/C [op-code fetch + memory read] for XRA M
T-State : 4T for XRA Rs
: 4+3=7T for XRA M

Examples
Assume A = 89H and C = 98 H
XRA C : Ex-OR’s the contents of C register with accumulator and store result 59H in
accumulator A. Cy = 0 and Ac = 0
Assume A = 30H, HL = D200H and at memory location D200H = 40 H
XRA M : Ex-OR’s the contents of memory location pointed by HL register pair with accumulator
and store result 54H in accumulator. Cy = 0 and Ac = 0
6. XRI 8bit immediate data
Description
 This instruction logically Ex-OR’s the 8 bit immediate data specified in the instruction
with accumulator bit by bit i.e. D0 of A register and so on till D7 bit of both operands.
 The result Ex-ORing is stored in accumulator, hence accumulator gets modified.
Operation Performed : A  A Ex-OR 8 bit immediate data
Flags Affected : S, Z, P are affected and Cy = 0 and AC = 0
Length on Byte : Two
Addressing Mode : Immediate
Machine cycle : 2 M/C [op-code fetch + memory read]
T–State : 4+3=7T
Examples
Assume A = 89H
XRI 98H : Ex-OR’s the 8 bit immediate data with accumulator and store the result 99H in the
accumulator A. Cy = 0 and AC = 1
7. CMA [Complement Accumulator]
Description
 This instruction complements the contents of accumulator A.
 CMA only works on accumulator A register.
 The complement is performing a NOT operation bit by bit where all 0’s are replace
with 1’s and all 1’s with 0’s.
Operation Performed : AA
Flags Affected : None
Length on Byte : One
Addressing Mode : Implied or Implicit
Machine cycle : 1 M/C [op-code fetch]
T-State : 4T
Examples
Assume A = 55H
CMA 0101 0101 = 55H before the execution of CMA
1010 1010 = AA after the execution of CMA
Program 1 : Find one's complement of 8 bit number stored in B register and store result
Back to B register.
To find complement of the content of B register, the number must be transferred to A
register because CMA instruction works only with accumulator.

Algorithm
Step 1 : Load B register with number Start
Step 2 : Move the content to B reg. to A reg.
Step 3 : Complement A reg. Load number in B register
Step 4 : Store result back to B reg.
Step 5 : Stop Copy it to A register
Program
MVI B FFH ; Load number FFH in B reg. Complement number
MOV A, B ; Copy it to A reg.
CMA ; Complement number FFH. Store result in B register
MOV B, A ; Copy Result to B reg.
HLT ; Stop
Stop
After the execution, the result of complement
i.e. 00H will be stored in B register.
Program 2 : Find One's complement of 8 bit number stored in memory location D000H
And store result in memory location D001H.
The number must be loaded in accumulator from the memory location D000H. Then find
complement.
Algorithm
Step 1 : Load number in A reg. from memory location
Step 2 : Find complement of number
Step 3 : Store result in memory location.
Step 4 : Stop
Program
LDA D000H ; Load number to A reg. from memory location
CMA ; Complement the number
STA D001H ; Store result to memory location.
HLT ; Stop

Start

Load number in A register from memory location D000H

Complement number

Store result in memory location D001H

Stop

Before the execution, the number must be stored in memory location D000H.
After the execution, the complement of the number will stored in memory location D001H.
Program 3 : Find two's complement of 8 bit number stored in B register and store resul
t back to B register.
To find complement of the content of B register, the
Start number must be transferred to A register because CMA
instruction works only with accumulator.
Load number in B register Now CMA gives you One's complement of number and
then by adding 01 to the result one's complement, you will
get two'2 complement of the number.
Copy it to A register Algorithm
Step 1 : Load B register with number
Complement the number Step 2 : Move the contents of B reg. to A reg.
Step 3 : 2's Complement A reg.
Add 1 to get 2nd complement Step 4 : Store result back to B reg.
Step 5 : Stop
Store results in B register

Program
Stop
MVI B, FFH : Load number FFH in B reg.
MOV A,B : copy it to A reg.
CMA : Complement number FFH
ADI 01H : 2's complement of number
MOV B, A : Store result to B reg.
HLT : Stop
After the execution, the result of two's complement i.e. 01H will be stored in
B register.
Program 4 : Find two's complement of 8 bit number stored in memory location D000H
and store result in memory location D001H.
The number must be loaded in accumulator from the memory location D000H. Then find
two's complement.
Algorithm
Step 1 : Load number in A reg. from memory location
Step 2 : Find two's complement of number
Step 3 : Store result in memory location.
Step 4 : Stop
Program
LDA D000H ; Load number to A reg. from memory location
CMA ; Complement the number
ADI 01H ; Two's complement of number
STA D001H ; Store result to memory location
HLT ; Stop

Start

Load number in A register from memory location D000H

Complement the number

Add 1 to get 2nd complement

Store result in memory locationD001H

Stop

Before the execution, the number must be stored in memory location D000H.
After the execution, the two's complement of number will stored in memory location
D001H.
OTHER LOGICAL INSTRUCTION
1. CMC [Complement Carry]
Description
 This instruction complements the carry flag Cy.
 The complement is performing a NOT operation on Cy flag i.e. if Cy is the set then
instruction will reset it and vice versa.
Operation Performed : Cy  Cy Complement
Flags Affected : Only Carry Cy
Length on Byte : One
Addressing Mode : Implied or Implicit
Machine cycle : 1 M/C [op-code fetch]
T-State : 4T
Examples
Assume Cy = 1
After execution of CMC instruction Cy will be reset i.e. 0
2. STC [Set Carry]
Description
 This instruction sets carry flag to 1 if Cy is reset else it does not effect on Cy flag.
Operation Performed : Set 1  Cy
Flags Affected : Only Carry Cy
Length on Byte : One
Addressing Mode : Implied or Implicit
Machine cycle : 1 M/C [op-code fetch]
T-State : 4T
Examples
If Cy = 0, after the execution of CMC instruction Cy will be reset i.e. 0.
If Cy = 1, then execution of the instruction do not affect Cy flag.
3. CMP Rs / CMP M
Rs = Source Register
M = Memory pointer
Description
 The CMP Rs instruction compares the content of accumulator with the content source
register Rs.
 The CMP M instruction compares the content of accumulator with the content of
memory location pointed by HL register pair.
 The result of comparison is reflected in flag register by setting CY or Z flags.
 The comparison is actually done by non- destructive subtraction of the content of
source register or memory location from the accumulator i.e. the source and the
destination will not change, but the flags set to indicate the results of the comparison.
Operation Performed : flags  A compare Rs/M
Flags Affected : Only CY , P and Z and Cy flags are used to indicate the
result of comparison
Length on Byte : One
Addressing Mode : Register for CMP Rs
: Indirect for CMP M
Machine cycle : 1 M/C [op-code fetch] for CMP Rs
: 2 M/C [op-code fetch + memory read] for CMP M
T-State : 4T for CMP Rs
: 4+3=7T for CMP M
Examples
Case 1 : Assume A = 20H and B = 10H
CMP B Compares content of register B with accumulator
A = 0010 0000
– B = 0001 0000
 0001 0000 Cy = 0 and Z = 0 indicate A > B
Case 2 : Assume A = 10H and B = 20H
CMP B Compares content of register B with accumulator
A = 0001 0000
– B = 0010 0000
1111 0000 Cy = 1 and Z = 0 indicate A < B
Case 3 : Assume A = 20H and B = 10H
CMP B Compares content of register B with accumulator
A = 0010 0000
– B = 0010 0000
0000 0000 Cy = 0 and Z = 1 indicate A = B

4. CPI 8 bit immediate data :

Description
 This instruction compares the content of accumulator with 8 bit immediate data
specified in the instruction.
 The result of comparison is reflected in flag register by setting CY or Z flags.
Operation Performed : flag  A compare 8 bit immediate data
Flags Affected : Only CY , P and Z and Cy flags are used to indicate the
result of Comparison
Length on Byte : Two
Addressing Mode : Immediate
Machine cycle : 2 M/C [op-code fetch + memory read]
T-State : 4+3=7T
Examples
Assume A = 20H
CPI 10H : Compares the content of accumulator with 8 bit immediate data 10H
5. RLC
Description
 This instruction rotates the content of accumulator towards the left by one bit position
i.e. D0 is shifted D1, D1 to D2 so on till D7 to Cy of flag register as well as D0
accumulator .
 This instruction operates only on accumulator i.e. A register.
Operation performed

Cy

D7 D6 D5 D4 D3 D2 D1 D0

Flags Affected : Only CY will be modified as D7 bit is shifted to Cy flag.

Length on Byte : One
Addressing Mode : Implied or Implicit
Machine cycle : 1 M/C [op-code fetch]
T-State : 4T
Examples
Assume A = 89H and Cy = 0
Before the execution of RLC bit position of A are
1000 1001 Cy = 0
After the execution of RLC bit position of A are
0001 0011 Cy = 1
6. RAL
Description
 This instruction rotates the content of accumulator towards left by one bit position i.e.
D0 is shifted D1, D1 to D2 so on till D7 to Cy and Cy to D0 bit position of accumulator
.
 This instruction operates only on accumulator i.e. A register.
Operation performed

Cy

D7 D6 D5 D4 D3 D2 D1 D0

Flags Affected : Only CY will be modified as D7 bit is shifted to Cy flag.

Length on Byte : One
Addressing Mode : Implied or Implicit
Machine cycle : 1 M/C [op-code fetch]
T-State : 4T
Examples
Assume A = 89H and Cy = 0
Before the execution of RLC bit position of A are
1000 1001 Cy = 0
After the execution of RLC bit position of A are
0001 0010 Cy = 1
7. RRC
Description
 This instruction rotates the content of accumulator towards right by one bit position
i.e. D7 is shifted D6, D6 to D5 so on till D0 to D7 as well as Cy flag.
 This instruction operates only on accumulator i.e. A register.
Operation Performed
Cy

D7 D6 D5 D4 D3 D2 D1 D0

Flags Affected : Only CY will be modified as D7 bit is shifted to Cy flag.

Length on Byte : One
Addressing Mode : Implied or Implicit
Machine cycle : 1 M/C [op-code fetch]
T-State : 4T
Examples
Assume A = 89 H and Cy = 0
Before the execution of RLC bit position of A are
1000 1001 Cy = 0
After the execution of RLC bit position of A are
0001 0010 Cy = 1

8. RAR
Description
 This instruction rotate the content of accumulator toward right by one bit position i.e
D7 is shifted D6 to D5 so on till D0 to Cy to D7 bit position of accumulator.
 This instruction operates only on accumulator i.e. A register.
Operation performed
Cy

D7 D6 D5 D4 D3 D2 D1 D0

Flags affected : Only CY will be modified as D7 bit is shifted to Cy flag.

Length in byte : One
Addressing mode : Implicit or Implied
Machine cycle : 1 M/C [op-code fetch]
T- State : 4T
Examples
Assume A = 89H and Cy = 0
Before the execution of RLC bit position of A are
10001001 Cy = 0
After the execution of RLC bit position of A are
01000100 Cy = 1
Program 1. WAP To Exchange Lower And Higher Nibble Of A Byte
Here the nibble of a byte can be swapped or exchanged by using RAR or RAL instruction
rotates bits towards right or left by 1 bit position .hence to rotate 4 bit of either lower or higher
nibble ,a byte Must be rotated 4 times towards left or right.
For example, suppose B register contains AFH, then after swapping you will get FA in B
register. But all rotate instructions operates only on accumulator, hence data must be
transferred to the accumulator.
Algorithm
Step 1 : Load number in a register
Step 2 : Rotate number right by 4 bit position
Step 3 : Store result
Step 4 : Stop
Program
MVI B, AFH ; Load Number In B Reg
MOV A, B ; Copy It To A Reg. For Rotation
RAR ; Rotate Number 4 Times Towards Right
RAR
RAR
RAR
MOV B,A ; Store Result
HLT ; Stop

Start

Load number in B reg.

Copy it to A.reg

Rotate A register toward right by 4 bit.

Store result in B register

Stop

After the execution, the result of byte exchange i.e. FAH will be available in
B register.

BRANCHING GROUP INSTRUCTIONS

 The Microprocessor executes the program in a sequential manner
i.e. second instruction after first, third after second and so on till last instruction of the
program.
 Program counter keeps track of program execution.
 Normally in programming, many times it is required to jump to a different part of the
program.
 The address of the new instruction where we want to jump or transfer program
executor control is either specified in the instruction or by the microprocessor.
The branching instruction can be classified in two categories as given below :
 Conditional branching
 Unconditional branching
Conditional
 These instruction transfer program control to another part or same program normally
called as subroutine if particular condition is satisfied else microprocessor will execute
next instruction.
  Normally the status of flags is checked to satisfy the conditions.
Examples
 JNC C100H jump if Cy=0 to memory location
C100H
 CNZ D000H call subroutine stored at D000H if Z=0
 Unconditional
 These instructions do not check any flag condition and the program control are
transferred directly to specified address directly.

Examples
 JMP D100H : transfer program control to D100H memory location directly.
 CALL E000H : transfer program control to subroutine stored at memory
unconditionally.
 RET : transfer program control back to the calling program
1. JMP 16 bit address
Description
 This is an unconditional jump instruction which transfer program control to the target
memory location whose 16 bit address is specified in the instruction.
 Now the instructions from the target memory location and onward will be executed in
the sequence by the microprocessor.
Operation performed : PC  16 bit address
Flags affected : None
Length in byte : Three
Addressing mode : Immediate
Machine cycle : 3 M/C [op-code fetch + memory read + memory read]
T-State : 4 + 3 + 3 = 10T
Examples
JMP D000H : This instruction transfer program control to D000H and start execution from that
location and onwards.
2. Conditional jump Instructions
Description
 Conditional jump instructions checks the condition, if condition is satisfied then and
only then program control is transferred to target memory location whose address is
specified in the instruction.
 If the condition is not satisfied, then execute next instruction after Jump instruction.
 Different conditional jump instructions are given below :
 JNC 16 bit address Jump if Cy = 0 [Reset]
 JC 16 bit address Jump if Cy = 1 [Set]
 JNC 16 bit address Jump if Z = 0 [Reset]
 JZ 16 bit address Jump if Z = 1 [Set]
 JP 16 bit address Jump if S = 0 [Reset]
 JM 16 bit address Jump if S = 1 [Set]
 JPE 16 bit address Jump if P = 1 [Set]
 JPO 16 bit address Jump if P = 0 [Reset]
Operation performed : PC  16 bit address if condition Is satisfied else
PC  PC+3
Flags affected : None but flags are checked
Length in byte : Three
Addressing Mode : Immediate
Machine Cycle : 3 M/C [op-code fetch + memory read + memory read] if
Condition is true
: 2 M/C if condition is false
T–State : 4+3+3=10T if condition is true
: 4+3=7T if condition is false
Examples
JNC D100H : Jump to the memory location if Cy = 0
JNC D2000H : Jump to memory location if Z =1
3. CALL 16 bit address
Description
 The CALL instruction is used to transfer the program control to the sub-program
control or subroutine.
 When the 8085executes the CALL instruction, the stack pointer is decremented by
one and copies the content of PC on the stack i.e. return address of the next
instruction after the CALL instruction.
 Now the instructions from the target memory location specified in the CALL instruction
and onward will be executed in the sequence by the microprocessor.
 Then, the 8085 loads the 16 bit address specified in the CALL instruction i.e. address
of the first instruction at the end of the subroutine, in to the PC and RET instruction at
the end of the subroutine will transfer program control back to the instruction after the
CALL instruction in the calling program by copying the return address from the stack,
back to PC.
Operation performed : SP  SP – 1
: [SP]  PCH,
: SP  SP – 1
: [SP]  PCL
: PC  16 bit address
OR
: [SP – 1]  PCH
: [SP – 2]  PCL
: PC  16 bit address
Flags affected : None
Length in byte : Three
Addressing Mode : Immediate register indirect
Machine Cycle : 5 M/C [op-code fetch + memory read + memory write]
: 2 M/C if condition if false
T-State : 6+3+3+3+3=18 T if condition is True.
: 6+3=9T if condition is false
Examples
CALL D100H : Transfer program control to subroutine which is stored from the address D100H
and start execution.

4. Conditional CALL instructions

Description
 Conditional CALL instructions checks the condition, if condition is satisfied then and
only then program control is transferred to subroutine whose address is specified in
the instruction.
 If condition is not satisfied, then execute next instruction after CALL instruction.
Different conditional CALL instructions are given below.
CNC 16 bit address Call if Cy=0 [Reset ]
CC 16 bit address Call if Cy=1 [Set]
CNZ Call if Z=0 [Reset]
CZ Call if Z=1 [Set]
CP Call if S=0 [Reset]
CM Call if S=1[Set]
CPE Call if P=1[Set]
CPO Call if P=0[Reset]
Operation performed : if condition is satisfied then
: [SP – 1]  PCH
: [SP – 2]  PCL
: PC  16 bit address
: Else PC  PC + 3
Flags affected : None but flags are checked
Length in byte : Three
Addressing mode : Immediate register indirect
Machine cycle : If condition is true
: 5 M/C [op-code fetch + Memory read + memory write +
memory write]
: 2 M/C if condition is false
T–State : 6 + 3 + 3 + 3 + 3=18T if condition is true.
: 6 + 3=9T if condition is false
Examples
CNC D100H : call subroutine stored at D100H if Cy=0
CNZ D2000H : call subroutine stored at D200H if Z=1
5. RET
Description
 This instruction is used to transfer the program control from the sub-program or sub-
routine to the calling i.e. main where subroutine is called using CALL instruction.
 When the 8085 executes the RET instruction, the contents of stack i.e. return address
is copied to the PC and execution of the calling program will continue from next
instruction after the CALL instruction.
  Now the instructions after the CALL instruction in calling program and onward will be
executed in the sequence by the microprocessor.
 The return address is used to transfer the program control back to the calling program
after execution of subroutine.
Operation Performed : PCL  [SP]
: SP  SP+1
: PCH  [SP]
: SP  SP+1
OR
: PCL  [SP]
: PCH  SP+2
Flags affected : None
Length in byte : One
Addressing Mode : Register Indirect
Machine cycle : 3 M/C [op-code fetch + memory read + memory read]
T-State : 4+3+3=10T
Examples
Main Program
C000H MVI A, 34H
C002H MVI, 40H
C004H CALL D100H ; Store C008 i.e. returns address on to stack
C008H ADD C ; Transfer program control to D100H where subroutine is
stored
C0009H :
Subroutine
D100H MOV A, B
:
:
RET ; Transfer program control from subroutine to return C008H in the calling
program.
6. Conditional RET Instructions
Description
 Conditional RET instructions checks the condition, if condition is satisfied, then
execute next instruction after RET instruction.
 If condition is not satisfied, then execute next instruction after RET instruction.
Different conditional RET instructions are given below :
RNC 16 bit address Return if Cy=0 [Reset]
RC 16 bit address Return if Cy=1 [Set]
RNZ 16 bit address Return if Z = 0 [Reset]
RZ 16 bit address Return if Z = 1 [Set]
RP 16 bit address Return if S = 1 [Set]
RM 16 bit address Return if S = 1 [Set]
RPE 16 bit address Return if P = 1 [Set]
RPO 16 bit address Return if P = 0 [Set]
Operation performed : if condition is satisfied then
: PCL  [SP]
: PCH  [SP + 1]
: SP  SP + 2
: Else PC  PC + 1
Flags affected : None but flags are checked
Length in byte : One
Addressing Mode : Register Indirect
Machine cycle : if condition is true
: 3 M/C [op-code fetch + memory read + memory Read]
: 2 M/C if condition if false
T–State : 4 + 3 + 3 = 10T if condition is true
: 4 + 3 =7 T if condition is false
Examples
RZ : RETURN from subroutine if C = 0
RZ : RETURN from subroutine if Z = 1
7. RST n [Restart Instruction]
Description
 This is one byte CALL information and also called as Software interrupt instructions.
 The program control can be transferred by executing this instruction to one out of right
vectored locations of the corresponding RST instruction.
 The n of the RST instruction ranges from 0 to 7.
 The vector addresses for all RST instructions are provided by the microprocessor it
self.
Operation performed : SP  SP – 1
: [SP]  PCH
: SP  SP – 1
: PC  16 bit address
OR
: [SP – 1]  PCH
: [SP – 2]  PCL
: PC  16 bit address
Flags affected : None
Length in bytes : One
Addressing mode : Register indirect
Machine cycle : 3 M/C [op code fetch + memory read + memory write]
T – State : 6 + 3 + 3 = 12 T
Examples
RST 1 : Restarts from the memory location 0008
8. PCHL
Description
 This instruction copies the content of H and L register pair to program counter PC.
 This instruction can be used to transfer program control to the memory location
specified in the HL register pair.
  Hence, PCHL is called a one byte unconditional jump instruction.
 After the execution of this instruction, the program execution will start from the
address specified in the HL register pair.

Operation Performed : PC  HL
Flags affected : None
Length in bytes : One
Addressing mode : Register
Machine cycle : 1 M/C [op code fetch]
T – State : 6T

Example
LXI H, D200 H
PCHL ;Program control is transferred to memory location D200H and
microprocessor starts execution from this address.

WRITING ASSEMBLY LANGUAGES PROGRAMS, DEBUGGING A PROGRAM

1. Addition of two numbers stored in B and C registers. Assume result is greater than
8 bit. Store the LSB of result in L register and the MSB in H register.
When we add numbers like FFH and FFH, then the result of the addition gives result
greater than 8 bit. The LSB of the result will be available in Accumulator, then what about
MSB? So, initialize on register with 0 i.e. you can say this register as a MSB result register
and then check carry flag after addition. If Cy is set, then increment MSB result register by 1
to get MSB of the result.

Algorithm
Step 1 : Load MSB result register with 00H
Step 2 : Load first number in B register
Step 3 : Load second number in C register
Step 4 : Copy first number to A register for addition
Step 5 : Add first number with second number
Step 6 : Check result < 8 bit, if yes then jump to Step 8
Step 7 : Increment MSB result register by 1
Step 8 : Store result
Step 9 : Stop
 Start

Initialize MSB result counter in D reg.

with 00H

Load B register with first number

Load C register with second number

Copy second number from C reg. to A.reg.

Add first number with second number

N Is
Cy = 1?

Increment MSB result counter by 1

Store result in memory

Stop

Program
MVI D, 00H ; Initialize MSB result register
MVI B, FFH ; Load first number in B reg.
MVI C, FFH ; Load second number in C reg.
MOV A, B ; Copy first number to A reg.
ADD C ; Add second number with first number
JNC DN ; Check result > 8 bit, if no go to label DN
INR D ; Increment MSB result register by 1
DN : MOV L, A ; Store LSB of result
MOV H, D ; Store LSB of result
HLT ; Stop
After the execution, the result will be 01FEH which is available in HL register pair.
2. Addition of two 8 bit numbers stored in memory locations D000H and D001H
respectively. Assume result is greater than 8 bit. Store the LSB of result in memory
location D002H and MSB in D003H.
In this case, the numbers must be loaded in general purpose registers and then perform
operation of addition on them. After the addition, store result to memory locations. Before the
execution of the program, store numbers in memory locations D000H and D001H.
Algorithm
Step 1 : Load first number in reg. from memory location
Step 2 : Load second number in another reg. from memory location
Step 3 : Initialize MSB result register with 00H
Step 4 : Add first number to second number

Start

Initialize MSB result counter in D reg.

with 00H

Load A register with first number stored at D000H

Copy first number in B register

Load A reg. with second number stored at D001H

Add first number with second number

N Is
Cy = 1?

Increment MSB result counter by 1

Store result in memory

Stop

Step 5 : Check result <8 bit, if yes then go to Step 7

Step 6 : Increment MSB result register by 1
Step 7 : Store result to memory locations
Step 8 : Stop
Program
LDA D000H ; Load first number in A register
MOV B, A ; Copy it to B reg.
LDA D001H ; Load second number in A register
MVI C, 00H ; Initialize MSB results register with 0
ADD B ; Add first number to second number
JNC DN ; Check result < 8 bit, if yes then go to DN
INC C ; Increment MSB result register
DN: STA D002H ; Store LSB of result
MOV A, C ; Copy it to A reg.
STA D003H ; Store MSB of result
HLT ; Stop
After the execution of the above program, you can check the result in memory locations
D002H and D003H.

3. Addition of two 2 digits BCD numbers stored in memory locations D000H and
D001H respectively. Assume result is greater than 2 digits. Store the LSB of result
in memory location D002H and MSB in D003H.
In this case, the numbers must be loaded in general purpose registers and then perform
operation of addition on them. After the addition, store result to memory location.
Assume memory location D001H contains 55 and D001 contains 55.

Algorithm
Step 1 : Load first BCD number in another register from memory location
Step 2 : Load second BCD number in another register from memory location.
Step 3 : Initialize MSB counter with 00H
Step 4 : Add first result to second number.
Step 5 : Adjust result to BCD
Step 6 : Check result <8 bit, if yes then go to step 8
Step 7 : Increment MSB counter by 1
Step 8 : Store result to memory locations.
Step 9 : Stop
 Start

Initialize MSB result counter in C reg. with 00H

Load A register with first number stored at D000H

Copy first number in B register

Load A register with second number stored at D001H

Add first number with second number

Adjust result to BCD using DAA instruction

N Is

Cy=1?

Y
Increment MSB result counter by 1

Store result in memory

Stop

Before the execution of the above program, store numbers in memory locations D000H
and D001H.
Program
LDA D00H ; Load first number in A register
MOV B, A ; Copy it to B reg.
LDA D100H ; Load second number in A register
MVI C, 00H ; Initialize MSB results register with 0
ADD B ; Add first number to second number
DAA ; Adjust result to BCD
JNC DN ; Check result < 8 bit, if yes then go to DN
INC C ; Increment MSB result integer
DN: STA D002H ; Store LSB of result
MOV A, C
STA D003H ; Store MSB of result
HLT ; Stop
After the execution of the above program, you can check the result in memory locations
D002H and D003H i.e. LSB of result 10 in D002H and MSB of result 01 in D003H.
4. Program for multiplication Of Two 8 Bit Numbers Using Successive Addition
Method And Shift And Add Method
Method 1 : Multiplication using successive addition method
In this method, the multiplication can be added multiplier times. for example, if you want
to multiply 4 by 5, then you can add 4 five times or 5 four times to get result 20. Hence, in this
program we will take 5 as addition counter and adds 4 five times.

Algorithm
Step 1 : Load multiplier in B reg.
Step 2 : Load multiplicand C reg.
Step 3 : Initialize result register with OOH
Step 4 : Add multiplicand with result register
Step 5 : Decrement multiplier
Step 6 : Check multiplier > 0, if no, then go to step 4
Step 7 : Store result
Step 8 : Stop

Program
MVI B, 05H ; Load B reg. with multiplier
MVI C, 04H ; Load C reg. with multiplicand
MVI A, 00H ; Initialize A reg. as a result register
UP: ADD C ; Add multiplicand with result register
DCR B ; Decrement multiplier
JNZ UP ; Check multiplier > 0, if no, then go to UP
MOV D, A ; Store result in D reg.
HLT ; Stop
 Start

Load multiplier in B register

Load multiplicand in C register

Initialize result register A with 0

Result register = Result register + multiplicand

Multiplier = multiplier - 1

N Is Multiplier
= 0?

Y
Store result in D register

Stop

After the execution, the result of multiplication will be available in D register. But when we
take larger 8 bit number, then result will be greater than 8 bit. In such case, above program
can not be used. Hence following program will solve this problem :

MVI B, 05H ; Load B reg. with multiplier

MVI E, 04H ; Load E reg. with multiplicand
MVI D, OOH ; Initialize D reg. with 00 to get MSB of result
LXI H, 0000H ; Initialize HL reg. pair as a result register
UP: DAD D ; Add multiplicand with result register
DCR B ; Decrement multiplier
JNZ UP ; Check multiplier > 0, if no, then go to UP
LT ; Stop
After the execution, the result of multiplication will be available in HL register pair.

Method 2 : Multiplication using shift and add method

 In this method, we can use multiplier for rotation to check each bit is either I or 0. If bit is
0, then content of result register is shifted toward left and if bit is 1, then result is added with
multiplicand and then shifted toward left by 1 bit position. As the numbers are 8 bit, this process
must be repeated 8 times.

1 0 1 0 1 0 1 0 AA H Multiplier
1 0 1 0 1 0 1 0 AA H Multiplicand
00000000
10101010
00000000
10101010
00000000
10101010
00000000
10101010
0111000011100100 70E4 H Result

7 0 E 4

Algorithm
Step 1 : Load multiplicand in BC reg. pair
Step 2 : Load multiplier in A reg.
Step 3 : Initialize result register HL with 0
Step 4 : Initialize shift counter in D reg. with 8
Step 5 : Result register = result register + result register [Shift result left by 1 bit]
Step 6 : Rotate multiplier to left by 1 bit
Step 7 : Check carry = 0, if yes, the go to step 9
Step 8 : Result register = result register + multiplicand
Step 9 : Decrement shift counter by
Step 10 : Check shift counter = 0, if no, go to step 5
Step 11 : Stop
 Start

Load multiplier in A register

Load multiplicand in BC register pair

Initialize shift counter with 8 in D register

Result register = Result register + Result Register

[Shift Result Register by 1 bit towards left]

Rotate Multiplier by left by 1 bit

Y
Is Cy=0?

N
Result Register = Result register + multiplicand

Shift Counter = shift counter - 1

N Is shift
counter = 0?

Stop

Program
LXI B, 00AAH ; Load multiplicand in BC reg. pair
MVI A, AAH ; Load multiplier in A register
LXI H, 0000H ; Initialize result register HL with 0000H
MVI D, 08H ; Initialize shift counter in D reg. with 8
UP: DAD H ; Shift result Left by 1 bit
RLC ; Rotate multiplier to left by 1 bit
JNC DN ; Check carry = 0, if yes, the go to DN
DAD B ; Result register = result register + multiplicand
DN: DCR D ; Decrement shift counter
JNZ UP ; Check shift counter
HLT ; Stop
After execution, the result of multiplication i.e. 70E4H will be available in HL register pair.

5. Program for division of two 8 bit Number using Successive Subtraction Method
In this method, we subtracts divisor from dividend until divisor is equal or greater than
dividend. So, one counter is required to count successive subtraction which gives you quotient
of the division operation and the end of the successive subtraction, we will get remainder. For
example, suppose we want to divide 0B by 2 then it can be perform as given below.

Step 1 : Initialize Quotient Counter in C register with 0, load dividend in A register and divisor
in B register
Step 2 : A=A-13=0B— 02 = 09
Increment C = C + 1 = 1
Compare Divisor with A, A > Divisor perform next subtraction
Step 3 : A = A - B = 09 — 02 = 07
Increment C = C + 1 = 1
Compare Divisor with A, A > Divisor perform next subtraction
Step 4 : A = A — B = 07 — 02 =05
Increment C = C +1 =3
Compare Divisor with A, A > Divisor perform next subtraction
Step 5 : A = A — B = 05 — 02 = 03
Increment C = C +1 = 4, Compare Divisor with A, A > Divisor perform next subtraction
Step 6 : A = A — B = 03 — 02 = 01
Increment C = C +1 = 5, Compare Divisor with A, A < Divisor stop subtraction
 Start

Load Dividend in A register

Load Divisor in B register

Initialize quotient counter with 0 in C register

Dividend = Dividend - Divisor

Quotient counter = quotient counter + 1

Y Is divided >=
Divisor?

Stop

Algorithm
Step 1 : Load dividend in A register
Step 2 : Load divisor in B register
Step 3 : Initialize Quotient Counter in C register with 0
Step 4 : Dividend = dividend — divisor
Step 5 : Increment quotient counter by 1
Step 6 : Compare result of subtraction with divisor
Step 7 : Check result > divisor, if yes go to Step 4
Step 8 : Stop
Program
MVI A, 0BH; Load dividend in A register
MVI B, 02H ; Load divisor in B register
MVI C, 00H ; Initialize Quotient Counter in C register with 0
UP: SUB B ; Dividend = dividend — divisor
INR C ; Increment quotient counter by 1
CMP B ; Compare result of subtraction with divisor
JNC UP ; Check result > divisor, if yes go to UP
HLT ; Stop
After execution, the remainder will be available in A register and the quotient in C register.
6. Program To Transfer Block Transfer
In block transfer, we transfer the data bytes from one part of memory to another part of
memory. Assume 10 bytes are stored in the memory from address D000H and the starting
address of the destination block where we want to transfer these 10 bytes is D1000H.

Source Block Destination Block

D000H D100H

D009H D109H

Now, to read bytes from the source block and then copy it to destination block, we need
two memory pointers. Hence, we can use HL and BC register pair as a memory pointers for
source and destination block. Again, we need a byte counter to tell microprocessor, how many
bytes stored in the block or to indicate length of block.
Algorithm :
Step 1 : Initialize bytes counter with length of block
Step 2 : Initialize memory pointer for source block
Step 3 : Initialize memory pointer for destination block.
Step 4 : Read byte or number from source block
Step 5 : Copy it to destination block.
Step 6 : Increment source and destination memory pointers by 1
Step 7 : Decrement byte counter by 1
Step 8 : Check byte counter > 0, if yes, then go to step 4
Step 9 : Stop
Program :
MVI D, 0AH ; Initialize bytes counter with length of block
LXI H, D000H ; Initialize memory pointer for source block
LXI B, D100H ; Initialize memory pointer for destination block
NEXT: MOV A, M ; Read number from source block AE ->[HL]
STAX B ; Copy it to destination block. [BC] <- A
INX H ; Increment source memory pointer HL<-HL+1
INX B ; Increment destination memory pointer BC<-BC+1
DCR D ; Decrement byte counter by 1 D<-D-1
JNZ NEXT ; Check byte counter > 0, if yes, then go to NEXT
HLT ; Stop
Before the execution, the ten data bytes must stored from memory location D000H.
After the execution, the contents of source block will be transferred to destination block
starting from D100H.
 Start

Initialize memory pointer for source array in HL

Initialize memory pointer for destination array in BC
Initialize byte counter in D register with nos. of bytes

Read number from source array using memory pointer

HL
Copy number to destination array using memory pointer BC

Increment source memory pointer HL by 1

Increment destination memory pointer BC by 1
Decrement byte counter by 1

N Is byte
counter =
0?

Stop

7. Program To Arrange Numbers In Array Or Block Of Data In Descending Order

To arrange numbers in descending order, check two numbers. If num < num2, then
interchange these two numbers. Then check num2 < num3. restart same process for
remaining numbers in the array.
We have to repeat the process until we get arranged data in descending order and for
the two counters are required where counter1 i.e. byte counter is needed to access numbers
from the block are required where counter2 i.e. pass counter is needed to repeat this
comparison process
Assume the array contains 10 data bytes and the starting address of the array is D100H.
Algorithm :
Step 1 : Initialize comparison or pass counter
Step 2 : Initialize memory pointer to read number from array
Step 3 : Initialize byte counter
Step 4 : Read numbers from an array
Step 5 : Compare 2 numbers
Step 6 : If numbers greater or equal to next number then go to step8
Step 7 : Interchange or swap numbers
Step 8 : Increment memory pointer to read next number from array
Step 9 : Decrement byte counter by one
Step 10 : If word counter not equal to 0 then go to step 4
Step 11 : Decrement comparison counter by one
Step 12 : If comparison counter not equal to zero then go to step 2
Step 13 : Stop

Program :
MVI C, OAH ; Initialize comparison or pass counter
UP1: LXI H, D100H ; Initialize memory pointer to read number from array
MVI B, 09H ; Initialize byte counter with length – 1 = 9
UP: MOV A, M ; Load number from the memory
INX H ; Increment memory pointer by 1 to read next number
CMP M ; Compare number with next number
JNC DN ; If number is > than next number then to DN
MOV D, M ; Exchange number and next number D to [HL]
MOV M,A ; [HL] <- A
DCX H ; HL <- HL – 1
MOV M, D ; HL <- D
INX H ; HL <- HL + 1
DN: DCR B ; Decrement byte counter by 1
JNZ UP ; If not zero then go to UP
DCR C ; Decrement comparison counter by 1
JNZ UP1 ; If not zero , then go to UP1
HLT ; Stop
Before the execution of the program the ten data bytes must be sorted from the memory
location D100H.
After the execution the all 10 bytes of the array will be arranged in the descending order
at same memory location.
8. Program to arrange numbers in array or block of data in ascending order
To arrange numbers in array in ascending order the above both i.e. for byte and word
program for descending order can be executed by replacing JNC instructions with JC
instruction.
Assume the array contains 10 data bytes and the starting address of the array is D100H.
Algorithm :
Step 1 : Initialize comparison or pass counter
Step 2 : Initialize memory pointer to read number from array
Step 3 : Initialize byte counter
Step 4 : Read numbers from an array
Step 5 : Compare 2 numbers
Step 6 : If numbers less or equal to next number then go to step8
Step 7 : Interchange or swap numbers
Step 8 : Increment memory pointer to read next number from array
Step 9 : Decrement byte counter by one
Step 10 : If word counter not equal to 0 then go to step 4
Step 11 : Decrement comparison counter by one
Step 12 : If comparison counter not equal to zero then go to step 2
Step 13 : Stop
Program :
MVI C, OAH ; Initialize comparison or pass counter
UP1: LXI H, D100H ; Initialize memory pointer to read number from array
MVI B, 09H ; Initialize byte counter with length -1 = 9
UP: MOV A, M ; Load number from the memory
INX H ; Increment memory pointer by 1 to read next number
CMP M ; Compare number with next number
JNC DN ; If number < next number then to DN
MOV D, M ; Exchange number and next number D to [HL]
MOV M,A ; [HL] <- A
DCX H ; HL <- HL – 1
MOV M, D ; HL <- D
INX H ; HL <- HL + 1
DN: DCR B ; Decrement byte counter by 1
JNZ UP ; If not zero then go to UP
DCR C ; Decrement comparison counter by 1
JNZ UP1 ; If not zero , then go to UP1
HLT ; Stop
Before the execution of the program the ten data bytes must be stored from memory
location D100H.
After the execution the all 10 bytes of the array will be arranged in ascending order at
same memory locations.
9. Program to find smallest number from the array
To find smallest number from the array the numbers in the array must be compared.

12
12

02
31
02
02
Smallest number from
45 02 the array of 5 number

65

Hence we need a memory pointer to read number from the array and also need byte
counter to read desired numbers only.
Assume the array contains 10 data bytes starting address of the array is D100H.
Algorithm :
Step 1 : Initialize comparison or pass counter
Step 2 : Initialize memory pointer to read number from array
Step 3 : Initialize byte counter
Step 4 : Read numbers from an array
Step 5 : Compare 2 numbers
Step 6 : If numbers < next number then go to step8
Step 7 : Replace number with next number which is smallest
Step 8 : Increment memory pointer to read next number in the array
Step 9 : Decrement byte counter by 1
Step 10 : If byte counter is not equal to zero then go to step 5
Step 11 : Store results
Step 12 : Stop
Program :
MVI C, OAH ; Initialize byte counter with OAH
LXI H, D100H ; Initialize memory pointer to read numbers
MOV A, M ; Read number from array
INX H ; Increment memory pointer by 1 to read next number
DCR C ; Decrement byte counter by 1
UP: CMP M ; Compare number with next number
JNC DN ; If number < next number then to DN
MOV A, M ; Replace number with next number which is smallest
DN: INX H ; Increment memory pointer by 1
DCR C ; Decrement byte counter by 1
JNZ UP ; If byte counter is not equal to zero then go to up
STA D10AH ; Store smallest number in memory
HLT ; Stop
Before the execution of the program the ten data bytes must be stored from memory
location D100H.
After the execution smallest number will be available in memory at location D10AH.

1. Which of the following instructions will complement content of accumulator?

a. CMA
b. CMP
c. CPI
d. CMC
2. Which of the following instructions will complement content of Carry flag?
a. CMC
b. CMA
c. CM
d. CMP
3. All jump instructions belong to ______ addressing mode
a. Immediate
b. Direct
c. Implied
d. Indirect
4. Which of the following instructions does not belong to direct addressing mode?
a. JC 2020H
b. STA 2050H
c. LDA 2020H
d. IN 10H
5. In _________ addressing mode operand is not written in the instruction
a. Implied
b. Immediate
c. Register
d. Direct
6. In _________ addressing mode operand is 8 or 16 bit data written in the instruction
a. Immediate
b. Implied
c. Direct
d. Indirect
7. In ________ addressing mode operand is a memory location whose address is pointed by a
register pair
a. Indirect
b. Register
c. Direct
d. Immediate
8. All register addressing mode instructions are ________
a. 1 byte
b. 2 byte
c. 3 byte
d. 1 or 2 byte
9. Which type of instructions are always of 1 byte?
a. Implied addressing mode
b. Direct Addresdding Mode
c. Immediate addressing mode
d. Data Transfer group
10. Instruction "ADI 44H" belongs to ____________
a. Arithmetic group
b. Logic group
c. Data transfer group
d. Branching group