Chap

Q9) 2 : Instruction set & Programming of 8085

H.S.C. Topic weightage : 43 Marks
1 Mark M.C.Q. = 1 = 1x1 = 01
3 Mark que = 4 = 3 x4 =12
5 Mark Assembly
Language Program = 6 = 6x5 =30

Q1) What is instruction? 4) Some instruction specify one or two register. The
An instruction is a command given to contents of registers are the required data.
microprocessor to perform a specified operation on e.g.1) MOV A,B; 2) INR B
given data. 5) In some instruction data is not specified i.e.
Q2) What is instruction set? implied. The most instruction of this type operate on
The entire group of instructions is called as the content of accumulator.
instruction set of microprocessor. e.g. CMA ;
Q3) Why instruction set? Instruction Format OR Types :
The programmer can write the program in Q6) How instruction of 8085 are classified?
assembly language using these instructions. Depending upon the size of machine codes or
Q4) Explain two parts of instruction? the instruction occupied in memory the 8085
Each instruction of 8085 microprocessor microprocessor instructions are classified into three
consists of two parts i.e. opcode ( operation code ) types as like below:
and operand. 1) One Byte Instruction :
Opcode : A 1byte instruction includes the opcode and
The first part of instruction which specifies the operand in the 8bits only i.e. one byte. It is also
the operation to be performed by the microprocessor called as one word instruction.
is called as opcode. Example MOV A,B
Operand: 2) Two Byte Instruction :
The second part of the instruction is the data In 2byte instruction the first byte is opcode
to be operated on and it is called as operand. and second byte is operand i.e. either 8-bit data or 8-
Mnemonic: Are the meaningful words which bit address.
defines operation performed by instruction Example MVI A, 08H;
during execution. 3) Three Byte Instruction :
In 3byte instruction the first by te is opecode
Q5) What are various techniques to specify and second and third byte bytes are operands i.e. 16-
operand? bit data or 16-bit address.
There are various ways to specify data or Example 1) LXI H, 3400H; 2) STA 3200H;
operand for an instruction given below:
1) 8-bit or 16 bit data may be directly given in
instruction itself.
e.g.1) MVI A, 02H; 2) LXI H, 2500H;
2) The address of memory location (16-bit) or I/O
port address (8-bit) may be given in instruction itself.
e.g.1) STA 3500H; 2) IN 02H; 3) OUT 30H;
3) In some instruction only one register is specified.
The content of the specified register is one of the
operand. It is understood that the other operand is in
the accumulator.
e.g. ADD B;
Q7) What is addressing mode? How they are ii) Arithmetic Group
classified? The instructions of this group perform
Addressing Mode : arithmetic operation such as addition, subtraction,
The various ways of specifying data or increment, decrement etc of the content of register or
operands for instructions are called as addressing memory. Almost all the instructions in this group
modes. affect the zero, sign, parity, carry and auxillary carry
Classification of Addressing Mode: flag according to the flag definattion.
The 8085 addressing modes are classified into All subtraction operations are performed
following types: using 2‟s compilement and set if borrow or not.
1) Register Addressing Mode : iii) Logical Group
In register addressing mode the source and The instructions of this group perform logical
destination operands are in the general purpose operation such as AND, OR, Ex-OR, Compare,
registers. The opcode specifies the operation and rotate, compliment etc of data in register or memory.
registers to be used to perform the operation. iv) Branch Control Group
Example: MOV A, B; The instructions of this group change the
2) Direct Addressing Mode : normal sequence of the program. These are two types
In direct addressing mode the address i.e. 8- of branch instructions:
bit or 16bit of the operand or data is given in the a) Unconditional Branch Instruction:
instruction itself. The unconditional branch instructions
Example: STA 6500H; transfer the program to the specified label or
3) Indirect Addressing Mode: address unconditionally i.e. without satisfying
In indirect addressing mode the address(16- any condition.
bit) of operand(data) is specified by a register pair. b) Conditional Branch Instruction:
The address stored in register pair points to memory The conditional branch instruction
location. transfer the program to the specified label or
Example: 1) LXI H, 7500H; 2) MOV A,M address when certain condition is satisfied. The
4) Immediate Addressing Mode: condition is tested depending upon the status of
In immediate addressing mode the data zero, parity, sign and carry flags. The program
(8-bit/16bit) or operand is specified within the counter contains the address of next instruction to
instruction itself or it is aa part of instruction. be executed. The branch control group instruction
Example: 1) MVI A, 35H; 2) LXI D, 3211H; loads the new address in PC to execute the
5) Implicit or Implied Addressing Mode: program from new address.
In implied or implicit addressing mode the v) Stack, I/O and Machine control Group:
operand is not specified in the instruction i.e. operand The instruction of this group perform I/O data
is absent in instruction. The operand is specified transfer, manipulates the stack and perform machine
within the opcode itself. The data(operand) is related operations.
supposed to be present generally in accumulator. vi) Interrupt Control Group:
Example: 1) RAL ; 2) RLC ; 3) CMA ; The instructions of this group performs
Classification of Instruction of 8085 interrupt related operations.
microprocessor
Q8) How instructions of 8085 microprocessor are
classified?
The 8085 instructions are classified according
to its operations as like six different groups such as
follows:
i) Data Transfer Group
The instructions of this group transfers data
from source to destination without altering the
contents of source. The contents of flags are not
affected by any instruction in this group.
Data Transfer Group 5) MVI M,data
The instructions of this group transfers data Function: [HL]  [8bit data]
from source to destination without altering the The 8bit data is given in
contents of source. The contents of flags are not instruction is copy or moves to
affected by any instruction in this group. the memory location whose
1) MOV r1,r2 address is in HL register pair.
Function: [r1]  [r2] Length 2 byte
The content of register r2 is Addressing mode Immediate
moved or copies to register r1. Flags affected No flags are affected.
Length 1 byte Example MVI M, 25H
Addressing mode Register
Flags affected No flags are affected. 6) LXI rp,16bit data
Example MOV A, B Function: [rp]  [16bit data]
[rh] 8MSBs of data
2) MOV r,M [rl] 8LSBs of data
Function: [r]  [HL] The 16bit data is given in
The content of memory whose instruction is copy or moves to
address is in register pair HL is register pair given in
moved or copies to register r. instruction.
Length 1 byte Length 3 byte
Addressing mode Indirect Addressing mode Immediate
Flags affected No flags are affected. Flags affected No flags are affected.
Example MOV B, M Example LXI H, 2300H

3) MOV M,r 7) LDA addr

Function: [HL]  [r] Function: [A]  [addr]
The content of register r is The content of memory
moved or copies to the location is given in instruction
memory whose address is in is copy or move or loaded into
register pair. accumulator i.e. A register.
Length 1 byte Length 3 byte
Addressing mode Indirect Addressing mode Direct
Flags affected No flags are affected. Flags affected No flags are affected.
Example MOV M, B Example LDA 2300H

4) MVI r,data 8) STA addr

Function: [r]  [8bit data] Function: [addr]  [A]
The 8bit data is given in The content of accumulator is
instruction is copy or moves to stored in the memory location
register given in instruction. whose address is specified in
Length 2 byte instruction.
Addressing mode Immediate Length 3 byte
Flags affected No flags are affected. Addressing mode Direct
Example MVI E, 14H Flags affected No flags are affected.
Example STA C500H
9) LHLD addr 12) STAX rp
Function: [L]  [addr] Function: [rp]  [A]
[H]  [addr+1] The content of accumulator is
The content of memory stored or moves or copies in
location whose address is the memory location whose
specified in the instruction is address is in the register pair
loaded or copy or moves into rp.
register L as well as content of Length 1 byte
next memory location i.e. Addressing mode Indirect
address is given instruction+1 Flags affected No flags are affected.
is loaded into register H. Example STAX D
Length 3 byte
Addressing mode Direct 13) XCHG
Flags affected No flags are affected. Function: [HL] > [DE]
Example LHLD 2900H Length 1 byte
Addressing mode Register
10) SHLD addr Flags affected No flags are affected.
Function: [addr]  [L] Example XCHG
[addr+1] [H]
The content of L is stored in Arithmetic Group
the memory location whose The instructions of this group perform
address is specified in the arithmetic operation such as addition, subtraction,
instruction. The content of increment, decrement etc of the content of register or
register H is stored in the next memory. Almost all the instructions in this group
memory location i.e. addr+1. affect the zero, sign, parity, carry and auxillary carry
Length 3 byte flag according to the flag definattion.
Addressing mode Direct All subtraction operations are performed
Flags affected No flags are affected. using 2‟s compilement and set if borrow or not.
Example SHLD 3900H 14) ADD r
Function: [A]  [A]+[r]
11) LDAX rp Whenever this type of an
Function: [A]  [rp] instruction is executed then
The content of memory content of register given in
location whose address is in instruction added with content
the register pair rp is loaded or of A register and result(sum) is
moves or copies into the stored in accumulator i.e. A
accumulator. register.
Length 1 byte Length: 1byte
Addressing mode Indirect Addressing mode: Register
Flags affected No flags are affected. Flags affected: All flags are affected.
Example LDAX B Example: ADD B
15) ADD M 18) ADC M
Function: [A] [A]+[HL] Function: [A][A]+[HL]+[cy]
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then
content of HL is added with content of HL and carry
content of register A and content are added to register A
result(sum) is stored in content and result (sum) is
accumulator i.e. A register. stored into A register i.e.
Length: 1 byte accumulator.
Addressing mode: Indirect Length: 1 byte
Flags affected: All flags are affected. Addressing mode: Indirect
Example: ADD M Flags affected: All flags are affected.
Example: ADC M
16) ADI data
Function: [A] [A]+[8-bit data] 19) ACI data
Whenever this type of an Function: [A][A]+[8-bit data]+[cy]
instruction is executed then 8- Whenever this type of an
bit data given in instruction is instruction is executed then 8-
added to content of register A bit data given in instruction
and result(sum) is stored in and content of carry is added
accumulator i.e. A register. to content of register A i.e.
Length: 2 byte accumulator and result(sum) is
Addressing mode: Immediate stored into register A i.e.
Flags affected: All flags are affected. accumulator.
Example: ADI 24H Length: 2 byte
Addressing mode: Immediate
17) ADC r Flags affected: All flags are affected.
Function: [A][A]+[r]+[cy] Example: ACI 26H
Whenever this type of an
instruction is executed then 20) DAD rp
content of carry and content of Function: [HL][HL]+[rp]
register given in instruction is Whenever this type of an
added to register A and instruction is executed then
result(sum) is stored into content of register pair i.e. rp
accumulator i.e. A register. are added to the content of HL
Length: 1 byte register pair.
Addressing mode: Register Length: 1 byte
Flags affected: All flags are affected. Addressing mode: Register
Example: ADC B Flags affected: Only carry
Example: DAD B
21) SUB r 24) SBB r
Function: [A][A]–[r] Function:
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then
content of register given in content of register given in
instruction is subtracted from instruction and content of
the content of an accumulator borrow is subtracted from the
i.e. A register. The result(diff) content of an accumulator i.e.
is stored in an accumulator i.e. A register. The result(diff) is
register A. stored in an accumulator i.e.
Length: 1 byte register A.
Addressing mode: Register Length: 1 byte
Flags affected: All flags are affected. Addressing mode: Register
Example: SUB C Flags affected: All flags are affected.
Example: SBB E
22) SUB M
Function: [A][A]–[HL]
Whenever this type of an 25) SBB M
instruction is executed then Function:
content of HL register pair
given in instruction is Whenever this type of an
subtracted from the content of instruction is executed then
an accumulator i.e. A register. content of HL register pair
The result(diff) is stored in an given in instruction and
accumulator i.e. register A. content of borrow is subtracted
Length: 1 byte from the content of an
Addressing mode: Indirect accumulator i.e. A register.
Flags affected: All flags are affected. The result(diff) is stored in an
Example: SUB M accumulator i.e. register A.
Length: 1 byte
23) SUI data Addressing mode: Indirect
Function: Flags affected: All flags are affected.
Whenever this type of an Example: SBB M
instruction is executed then 8-
bit data is given in instruction 26) SBI data
is subtracted from the content Function:
of an accumulator i.e. A Whenever this type of an
register. The result(diff) is instruction is executed then
stored in an accumulator i.e. content of 8-bit data is given in
register A. instruction and content of
Length: 2byte borrow is subtracted from the
Addressing mode: Immediate content of an accumulator i.e.
Flags affected: All flags are affected. A register. The result(diff) is
Example: SUI 21H stored in an accumulator i.e.
register A.
Length: 2 byte
Addressing mode: Immediate
Flags affected: All flags are affected.
Example: SBI 2EH
27) INR r 30) DCR r
Function: [r][r]+1 Function: [r][r]-1
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then
content of register „r‟ is content of register „r‟ is
incremented by one and decremented by one and
incremented result stores into decremented result stores into
same register. same register.
Length: 1 byte Length: 1 byte
Addressing mode: Register Addressing mode: Register
Flags affected: Except carry flag all other Flags affected: Except carry flag all other
flags other are affected. flags are affected.
Example: INR B Example: DCR B

28) INR M 31) DCR M

Function: [HL][HL]+1 Function: [HL][HL] – 1
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then
content of memory location content of memory location
addressed by HL pair is addressed by HL pair is
incremented by one and decremented by one and
incremented result is stored decremented result is stored
into same HL memory into same HL memory
location. location.
Length: 1 byte Length: 1 byte
Addressing mode: Indirect Addressing mode: Indirect
Flags affected: Except carry flag all other Flags affected: Except carry flag all other
flags are affected. flags are affected.
Example: INR M Example: DCR M

29) INX rp 32) DCX rp

Function: [rp][rp]+1 Function: [rp][rp] – 1
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then
content of register pair rp is content of register pair rp is
incremented by one and decremented by one and
incremented result is stored decremented result is stored
into same register pair. into same register pair.
Length: 1 byte Length: 1 byte
Addressing mode: Register Addressing mode: Register
Flags affected: No flags are affected. Flags affected: No flags are affected.
Example: INX H Example: DCX B
33) DAA 35) ANA M
Function: Function: [A]  [A] ^ [HL]
The DAA instruction convert Whenever this type of an
the binary(Hex) result in an instruction is executed then
accumulator into decimal or content of memory location is
BCD result. The instruction addressed by HL pair is
DAA is used in the program logically ANDed with the
after ADD, ADI, ACI, ADC content of an accumulator i.e.
instructions only. The A register. The result(ANDing
followings steps are taken to content) is always stored into
convert binary result to accumulator or A register.
decimal result. Length: 1 byte
Step 1: If the value of 4 LSBs Addressing Mode: Indirect
(Lower nibble) of greater than Flags affected: All flags are affected. After
9 OR AC flag is set to 1 then ANDing Some flags are
DAA adds 06H in content of modified again such as CY=0
Accumulator. and AC=1
Step 2: If the value of 4 MSBs Example: ANA M
(Higher nibble) of greater than
9 OR CY flag is set to 1 then 36) ANI data
DAA adds 60H in content of Function: [A]  [A] ^ [8-bit data]
Accumulator. Whenever this type of an
Length: 1 byte instruction is executed then 8-
Addressing mode: Implicit or Implied bit data is given in instruction
Flags affected: All flags are affected. is logically ANDed with the
Example: DAA content of an accumulator i.e.
A register. The result(ANDing
Logical Group content) is always stored into
The instructions of this group perform logical accumulator or A register.
operation such as AND, OR, Ex-OR, Compare, Length: 2 byte
rotate, compliment etc of data in register or memory. Addressing Mode: Immediate
34) ANA r Flags affected: All flags are affected. After
Function: [A]  [A] ^ [r] ANDing Some flags are
Whenever this type of an modified again such as CY=0
instruction is executed then and AC=1
content of register „r‟ is Example: ANI 2BH
logically ANDed with the
content of an accumulator i.e.
A register. The result(ANDing
content) is always stored into
accumulator or A register.
Length: 1 byte
Addressing Mode: Register
Flags affected: All flags are affected. After
ANDing Some flags are
modified again such as CY=0
and AC=1
Example: ANA E
37) ORA r 39) ORI data
Function: [A]  [A] V [r] Function: [A]  [A] V [8-bit data]
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then 8-
content of register „r‟ is bit data is given in instruction
logically ORed with the is logically ORed with the
content of an accumulator i.e. content of an accumulator i.e.
A register. The result(ORing A register. The result(ORing
content) is always stored into content) is always stored into
accumulator or A register. accumulator or A register.
Length: 1 byte Length: 2 byte
Addressing Mode: Register Addressing Mode: Immediate
Flags affected: All flags are affected. After Flags affected: All flags are affected. After
ORing Some flags are ORing Some flags are
modified again such as CY=0 modified again such as CY=0
and AC=0 and AC=0
Example: ORA D Example: ORI 2CH

38) ORA M 40) XRA r

Function: [A]  [A] V [HL] Function: [A]  [A]  [r]
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then
content of memory location is content of register „r‟ is
addressed by HL pair is logically XORed with the
logically ORed with the content of an accumulator i.e.
content of an accumulator i.e. A register. The result(XORing
A register. The result(ORing content) is always stored into
content) is always stored into accumulator or A register.
accumulator or A register. Length: 1 byte
Length: 1 byte Addressing Mode: Register
Addressing Mode: Indirect Flags affected: All flags are affected. After
Flags affected: All flags are affected. After XORing Some flags are
ORing Some flags are modified again such as CY=0
modified again such as CY=0 and AC=0
and AC=0 Example: XRA E
Example: ORA M
41) XRA M 44) CMC
Function: [A]  [A]  [HL] Function: CY  [CY ]
Whenever this type of an Whenever this type of an
instruction is executed then instruction is executed then
content of memory location is content of only carry flag is
addressed by HL pair is complimented and carry
logically XORed with the compliment is stored into same
content of an accumulator i.e. carry flag.
A register. The result(XORing Length: 1 byte
content) is always stored into Addressing Mode: Implicit or Implied
accumulator or A register. Flags affected: Only carry
Length: 1 byte Example: CMC
Addressing Mode: Indirect
Flags affected: All flags are affected. After 45) STC
XORing Some flags are Function: [CY]  1
modified again such as CY=0 Length: 1 byte
and AC=0 Addressing Mode: Implicit or Implied
Example: XRA M Flags affected: Only Carry
Example: STC
42) XRI data
Function: [A]  [A]  [8-bit data] 46) CMP r
Whenever this type of an Function: [A] – [r]
instruction is executed then 8- Whenever this type of
bit data is given in instruction instruction is executed then
is logically XORed with the content of register „r‟ is
content of an accumulator i.e. subtracted from the content of
A register. The result(XORing an accumulator. The result is
content) is always stored into not stored anywhere. The
accumulator or A register. content of flags will affected
Length: 2 byte according to the result of
Addressing Mode: Immediate subtraction such like as
Flags affected: All flags are affected. After follows:
XORing Some flags are i) if A > r then CY=0
modified again such as CY=0 ii) if A< r then CY=1
and AC=0 iii) if A= r then Z=1
Example: XRI 2DH Length: 1 byte
43) CMA Compliment accumulator Addressing Mode: Register
Function: A [ A ] Flags affected: All flags are affected.
Whenever this type of an Example: CMP B
instruction is executed then
content of an accumulator is
complimented i.e. 1‟s
compliment result is obtained.
The complimented
(1‟scomplimnet) is stored into
accumulator.
Length: 1 byte
Addressing Mode: Implicit or Implied
Flags affected: No flags are affected.
Example: CMA
47) CMP M 49) RLC Rotate accumulator left
Function: [A] – [HL] Function: [Dn+1] [Dn]
Whenever this type of [D0]  [D7]
instruction is executed then [CY][D7]
content of memory location is Whenever this type of an
addressed by HL pair is instruction is executed then
subtracted from the content of content of accumulator is
an accumulator. The result is
rotated towards left by one
not stored anywhere. The
content of flags will affected bit. The seventh bit of
according to the result of accumulator is moved to
subtraction such like as carry bit as well as to the
follows: zero bit of the accumulator
i) if A > HL then CY=0 as shown if following figure
ii) if A< HL then CY=1 Length: 1 byte
iii) if A= HL then Z=1 Addressing Mode: Implicit or Implied
Length: 1 byte Flags affected: Only Carry is affected.
Addressing Mode: Indirect Example: RLC
Flags affected: All flags are affected.
Example: CMP M 50) RAL
Function: [Dn+1] [Dn]
48) CPI data [CY]  [D7]
Function: [A] – [8-bit data] [D0][CY]
Whenever this type of Whenever this type of an
instruction is executed then 8- instruction is executed then
bit data is given in instruction content of accumulator is
is subtracted from the content rotated towards left through
of an accumulator. The result
carry by one bit. The
is not stored anywhere. The
content of flags will affected
seventh bit of accumulator is
according to the result of moved to carry and carry bit
subtraction such like as is moved to zero bit of
follows: accumulator as shown if
i) if A > 8-bit data following figure
then CY=0 Length: 1 byte
ii) if A< 8-bit data Addressing Mode: Implicit or Implied
then CY=1 Flags affected: Only Carry flag is affected.
iii) if A= 8-bit data Example: RAL
then Z=1
Length: 2 byte
Addressing Mode: Immediate
Flags affected: All flags are affected.
Example: CPI 26H
51) RRC Branch Control Group:
Function: [Dn-1] [Dn] The instructions of this group change the
[D7]  [D0] normal sequence of the program. There are two types
[CY][D0] of branch instruction.
Whenever this type of an 1) Unconditional Branch Instructions:
instruction is executed then The unconditional branch instructions
content of accumulator is transfers the program to the specified label or
address unconditionally i.e. without satisfying
rotated towards right by one
any condition.
bit. The zero bit of 2) Conditional Branch Instructions:
accumulator is moved to The conditional branch instructions
seventh bit the accumulator transfer the program to the specified label or
as well as to carry bit as address when certain condition is satisfied.
shown if following figure The condition is tested depending upon
Length: 1 byte the status of zero(Z), Parity(P), Sign(S), and
Addressing Mode: Implicit or Implied Carry (CY) flags. The program counter (PC)
Flags affected: Only Carry is affected. contains the address of next instructions to be
Example: RRC executed. The branch control group instruction
loads the new address in PC to execute the
program from new address.
52) RAR
Function: [Dn–1] [Dn] Unconditional Branch Control Instruction:
[CY]  [D0]
[D7][CY] 54) JMP addr (label) Unconditional Jump
Whenever this type of an Function: [PC]  addr
instruction is executed then Whenever this type of
content of accumulator is instruction then it jump to the
rotated towards right by one address of the label
unconditionally. The address
bit through carry. The zero
of the label is the address of
bit of accumulator is moved memory location for next
to carry and the carry bit is instruction to be executed.
moved to seventh bit of This instruction load the
accumulator as shown if address of label in program
following figure counter.
Length: 1 byte Length: 3 byte
Addressing Mode: Implicit or Implied Addressing mode: Immediate
Flags affected: Only Carry is affected. Flags affected: No flags are affected.
Example: RAR Example: JMP C523H
Conditional Branch Control Instruction: Unconditional Call Instruction
In conditional jump instructions if the
condition is true or satisfied then only jump is made 63) CALL addr/Label (Unconditional Call)
at the specified address. If condition is false or not Format: [SP-1]  [PCH]
satisfied then the next instruction in the sequence is [SP-2] [PCL]
executed. The conditional jump instruction are given [SP][SP-2]
below: [PC]addr / label
Whenever this type of
Jcondition addr/label instruction is executed then it
Function call subroutine or subprogram.
if condition is true then Before calling to the
PC  addr (label) subroutine the address of next
else instruction of the main
PC PC+3 program is saved in the stack.
i.e. it executes next instruction in sequence. The content of the stack
Length : 3 byte. pointer is decremented by two.
Addressing mode: Immediate Then the program jumps to
Flags affected : No flags are affected. subroutine or subprogram
Instructions conditional jumps: starting at address specified by
55) JZ addr (LABEL) label.
Jump if the result is zero i.e. Z=1. Thus program counter stores
address given in instruction.
56) JNZ addr (LABEL) Length: 3 byte.
Jump if the result is not zero i.e. Z=0. Addressing Mode: Immediate / Indirect
Flags affected: No flags are affected.
57) JC addr (LABEL) Example CALL C050H
Jump if the result is carry i.e. CY=1.
Conditional CALL instructions:
58) JNC addr (LABEL) In conditional CALL instruction if condition
Jump if the result is no carry i.e. CY=0. is true then program calls the specified subroutine or
subprogram. If the condition is false then the next
59) JP addr (LABEL) instruction in the sequence is executed. Before call
Jump if the result is plus i.e. S=0. the address if next instruction of the main program is
saved in the stack. The stack pointer is decremented
60) JM addr (LABEL) by two memory location.
Jump if the result is minus i.e. S=1. Thus program counter stores address given in
instruction if given condition is true. If false then
61) JPE addr (LABEL) next instruction in program is executed i.e. PC
Jump if even parity i.e. P=1. contains address of next instruction in main program.

62) JPO addr (LABEL)

Jump if odd parity i.e. P=0.
Ccondition addr / label Unconditional Return Instruction:
Function: If condition is true then
[SP-1] PCH 72) RET Unconditional Return
[SP-2] PCL RET
[SP] SP – 2 Format : [PCL]  [SP]
[PC] addr / label [PCH] [SP+1]
else [SP] [SP+2]
PCPC+3 Whenever this type of
i.e. executes the next instruction is executed then it
instruction in the main return from subroutine. The
program. RET instruction is used at the
Length: 3 byte. end of subroutine. Before the
Addressing mode: Immediate / Indirect execution of a subroutine the
Flags affected No flags are affected. address of the next instruction
The conditional CALL instructions are as of the main program is saved
given below: in the stack. The execution of
64) CZ addr (LABEL) RET instruction brings back
Calls a subroutine if the result the saved address from the
is zeo i.e. Z=1. stack to the program counter.
65) CNZ addr (LABEL) The content of stack pointer is
Calls a subroutine if the result incremented by 2. Then the
is not zeo i.e. Z=0. program jumps to the next
66) CC addr (LABEL) instruction after CALL in the
Calls a subroutine if the result main program.
is contains carry i.e. CY=1. Length : 1 byte
67) CNC addr (LABEL) Addressing Mode : Indirect
Calls a subroutine if the result Flags affected : No flags are affected.
is not contain carry i.e. CY=0. Example: RET
68) CP addr (LABEL)
Calls a subroutine if the result Conditional RET instruction:
is Plus i.e. S=0. In conditional RET
69) CM addr (LABEL) instruction if condition is true
Calls a subroutine if the result then the program returns form
is negative or minus i.e. S=1. the subroutine. If condition is
70) CPE addr (LABEL) false then the next instruction
Calls a subroutine if the result in the sequence is executed.
is even parity i.e. P=1. Rcondition
71) CPO addr (LABEL) Function: if condition is TRUE then
Calls a subroutine if the result [PCL]  [SP]
is Odd parity i.e. P=0. [PCH] [SP+1]
[SP] SP+2
else
PCPC+1
i.e. executes the next
instruction in the sequence.
Length: 1 byte.
Addressing Mode: Indirect.
Flags affected: No flags are affected.
Example: RC
The conditional RET instructions are as given
below: 82) PUSH PSW
Function : [SP-1] [A]
73) RZ Return from subroutine if the result is [SP-2]  [ flags or PSW ]
zero i.e. Z=1. [SP]  [SP – 2 ]
Whenever this type of
74) RNZ Return from subroutine if the result is instruction is executed then
not zero i.e. Z=1. content of processor status
word or program status word
75) RC Return from subroutine if the result is (PSW) is pushed or copied
contains carry i.e. CY=1. onto the stack. The stack
pointer is decremented by one
76) RNC Return from subroutine if the result is and the contents of
not contains carry i.e. CY=0. accumulator are copied onto
that location. The stack pointer
77) RP Return from subroutine if the result is is again decremented by one
plus i.e. S=0. i.e. SP-2 and the content of
flags or program status
78) RM Return from subroutine if the result is word(PSW) are copied at that
minus or negative i.e. S=1. location.
Length : 1 byte.
79) RPE Return from subroutine if the result is Addressing Mode : Indirect
even parity i.e. P=1. Flags affected : No flags are affected.
Example: PUSH PSW
80) RPO Return from subroutine if the result is
odd parity i.e. P=0. 83) POP rp
Function : ` [ rl ]  [SP]
Stack Group Instructions: [ rh ]  [SP+1]
81) PUSH rp [SP]  SP+2
Function : [SP-1]  [ rh ] Whenever this type of
[SP-2]  [ rl ] instruction is executed then
SP  SP – 2 POP the content of register
Whenever this type of pair i.e. rp from the stack. The
an instruction is executed then contents of memory location
the content of register pair rp pointed by SP are copied to the
is pushed or copied onto the lower order register of rp. The
stack. The stack pointer is SP is incremented by one and
decremented by one and the content of that memory
contents of higher order of rp location are copied to the
are copied into that location. higher order register of rp. The
The stack pointer is again SP is again incremented by
decremented by 1 i.e. SP-2 and one i.e SP+2. The rp can be
the contents of lower order one of BC/HL/DE.
register of rp are copied at that Length : 1 byte.
location. The rp can be like Addressing Mode : Indirect.
BC/DE/HL. Flags affected: No flags are affected.
Length: 1 byte. Example: POP B
Addressing Mode: Indirect.
Flags affected: No flags are affected.
Example: PUSH B
84) POP PSW
Function: [flags or PSW]  [SP] 86) SPHL
[A]  [SP+1] Function: [SP] [HL]
[SP]  SP+2 Whenever this type of
Whenever this type of instruction is executed then the
instruction is executed then content of HL register pair are
POP the content of processor moved to the SP register.
status word or program status Length: 1 byte.
word (PSW) from the stack. Addressing Mode: Register.
The contents of memory Flags affected: No flags are affected.
location pointed by SP are Example: SPHL
copied to the flags or program
status word (PSW). The SP is Input/Output Group Instructions:
incremented by one and
content of that location is 87) IN port addr
stored or copied.to the Function: [A]  [port address]
accumulator. The SP is again Whenever this type of
incremented by one i.e. SP+2. instruction is executed then
The POP process is content of port given in
exactly opposite to PUSH. So instruction is moved or copied
the contents are stored by to the accumulator. After the
PUSH are taken back using instruction IN the address of
POP instructions. port is specified. The address
Length: 1 byte. of a port is an 8-bit input port
Addressing Mode: Indirect. address.
Flags affected: No flags are affected. Length: 2 byte.
Example: POP PSW Addressing Mode: Direct.
Flags affected: No flags are affected.
85) XTHL Example: IN 10H
Function: [ L ] <-> [ SP ]
[ H ] <-> [ SP + 1 ] 88) OUT port addr
Whenever this type of Function: [port]  [A]
instruction is executed then it Whenever this type of
exchanges stack top with HL instruction is executed then
pair. The contents of L register content of accumulator is
are exchanged with stack moved or copied to the port i.e
location pointed by stack output port. After the
pointer. The content of H instruction OUT the address of
register are exchanged with the port is specified. The address
next stack location. The of a port is an 8-bit address.
contents of the stack pointer Length: 2 byte.
register are not altered or Addressing mode: Direct.
affected. Flags affected: No flags are affected.
Length: 1 byte. Example: OUT 10H
Addressing Mode: Indirect.
Flags affected: No flags are affected.
Example: XTHL
 Length: 1 byte.
Machine Control Instructions Addressing Mode Indirect
Flags affected No flags are affected.
89) HLT Halt Instructions Restart Address
Function: HALT OR OR Vector Address
Whenever this type Software Interrupt Or Software Interrupt
instruction is executed then it Instructions Address
stops the microprocessor. The RST 0 0000H
registers and status flags RST 1 0008H
remains unaffected. RST 2 0010H
Length: 1 byte. RST 3 0018H
Addressing Mode: None RST 4 0020H
Flags affected: No flags are affected. RST 5 0028H
Example: HLT RST 6 0030H
RST 7 0038H
90) NOP No operation
Function: Whenever this type of
Example : RST 1
instruction is executed then no
operation is performed. The
registers and flags remains EI Enable Interrupt
Function: Whenever this type
unaffected.
instruction is executed then the
Length: 1 byte.
interrupt system is enabled.
Addressing Mode: None
Length: 1 byte.
Flags affected: No flags are affected.
Addressing mode No addressing mode.
Example: NOP
Flags affected: No flags are affected.
Example EI
Interrupt Control Group:
DI Disable Interrupt
91) RST n Restart ( n is from 0 to 7)
Function: Whenever this type
Function [SP–1] -  PCH
instruction is executed then the
[SP–2]  PCL
interrupt system is disabled.
[SP]  SP–2
Length: 1 byte.
[PC]  8 times n
Addressing mode No addressing mode.
Whenever this type of an
Flags affected: No flags are affected.
instruction is executed then it transfers
the program control to specific Example DI
memory location known as restart
location or restart address. Restart is a
one word CALL instruction. The
restart address are referred as vectored
addresses. The microprocessor
multiplies the RST by 8 to estimate
these vector address as shown in
following table.
Before transferring the
program control to the vector address
the contents of program counter is
saved on the stack like CALL
instruction. This instruction can be
used as software interrupt.
 94) SIM Set Interrupt Mask. shows the accumulator contents for
Function: The execution of the RIM instruction:
SIM enables/disables interrupts
according to the bit pattern of the D7 D6 D5 D4 D3 D2 D1 D0
accumulator. This instruction is also SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
used for serial data communication on
SOD pin of 8085. The following is 1) SID : Serial Input Data.
accumulator contents for SIM 2) I 7.5 : Pending RST 7.5.
instructions OR interprt‟s meaning of if 1 then RST 7.5 is made for pending
or disabled.
D7 D6 D5 D4 D3 D2 D1 D0 if 0 then RST 7.5 is not made for
SID I 7.5 I 6.5 I 5.5 IE M 7.5 M 6.5 M 5.5 pending or enabled.
SIM 3) I 6.5 : Pending RST 6.5.
1) SOD : Serial Data Output if 1 then RST 6.5 is made for pending
2) SDE: Serial Data Enable or disabled.
if 1 then serial data is enabled. if 0 then RST 6.5 is not made for
if 0 then serial data is disabled. pending or enabled.
3) R7.5 : Reset RST 7.5. 4) I 5.5 : Pending RST 5.5.
if 1 then RST 7.5 is reset. if 1 then RST 5.5 is made for pending
if 0 then RST 7.5 is ser. or disabled.
4) MSE : Mask set enable. if 0 then RST 5.5 is not made for
if 1 then mask set enable is enabled. pending or enabled.
if 0 then mask set enable is disabled. 5) IE : Interrupt Enable Flag.
5) M7.5 : RST 7.5 Mask. if 1 then interrupt enable flag is
if 1 then RST 7.5 is masked or made enabled.
for pending or disabled. if 0 then interrupt enable flag is
if 0 then RST 7.5 is non masked or not disabled.
made for pending or enabled. 6) M 7.5 : RST 7.5 Mask.
6) M6.5 : RST 6.5 Mask. if 1 then RST 7.5 is masked or made
if 1 then RST 6.5 is masked or made for pending or disabled.
for pending or disabled. if 0 then RST 7.5 is non masked or not
if 0 then RST 6.5 is non masked or not made for pending or enabled.
made for pending or enabled. 7) M 6.5 : RST 6.5 Mask.
7) M 5.5 : RST 5.5 Mask. if 1 then RST 6.5 is masked or made
if 1 then RST 5.5 is masked or made for pending or disabled.
for pending or disabled. if 0 then RST 6.5 is non masked or not
if 0 then RST 5.5 is non masked or not made for pending or enabled.
made for pending or enabled. 8) M 5.5 : RST 5.5 Mask.
Length 1 byte. if 1 then RST 5.5 is masked or made
Addressing mode: No addressing mode. for pending or disabled.
Flags affected: No flags are affected. if 0 then RST 5.5 is non masked or not
Example SIM made for pending or enabled.
Length: 1 byte.
95) RIM Read Interrupt Mask. Addressing mode No addressing mode.
Function: Whenever this instruction is Flags affected: No flags are affected.
executed then the content of an EXAMPLE: RIM
accumulator is loaded with status of
pending interrupt. The status of restart
interrupt mask and the contents of SID
(serial input data). The following fig