2nd CHAPTER

INSTRUCTION SET AND

PROGRAMMING OF 8085
 C000H –ML-16bits
 20H-data-8bits
A,B,C,D ,E ,H ,L---reg
BC
DE
HL
A-result
B,C,D,E,H,L-temp data
BC-ML
HL-reg pair –[ML]

b+c
Basic points
8085 instruction is called a mnemonic
A mnemonic is made up of opcode
(operation code)and operand (A-C)
Opcode is the code which is going to work
Operand is data on which the code is going
to work.
Instruction are written in hex system
In the instruction address[ML] is written as
lower byte , higher byte.
ADDRESSING MODES IN 8085
The term addressing modes refers to the
way in which the operand of an instruction
is specified. OR Addressing mode is the
way of addressing a memory location in
instruction.
Types of addressing modes
Direct addressing mode
Register addressing mode
Register indirect addressing mode
Immediate addressing mode
Implicit/implied addressing mode
Direct addressing mode

In direct addressing, the address appears after

opcode of instruction in program memory.
The address of operand is specified within the
instruction.
The instruction using direct addressing modes are 3
byte instructions. Byte 1 is opcode of instruction,
byte 2 is lower order address and byte 3 is high order
address.
E.g. 1) LDA 2000H(H=20(1BYTE),L=00(1BYTE))
loads the Acc with the content of location 2000
2) STA 2000H
 stores the contents of the Acc at the location 2000.
Register addressing mode

In this mode , the data is specified in

registers.
These instruction are single byte
instruction.
All action occurs within the cpu.
E.g. 1) MOV B,C
 Move the contents of C register into B
register.
i.e. BC
2) INR B
 increments the contents of B register.
i.e. B B+1
Immediate addressing
mode(I)
 In immediate addressing the data appears immediately
after opcode of instruction in program memory.
 In this mode , the data is specified in the instruction
itself.
 These operation are specified with either 2 or 3 byte
instruction.
 E.g. 1) MVI A,35H
 Move immediate data 35 into the Acc
 A35H
 2) ADI 05H
 Adds immediate data 05H to the content of Acc.
 A A+5
Register indirect addressing mode(X,M)

 In register indirect addressing the content of

register pair points to the address of the operand.
 In this mode , the address of operand is specified
by a register pair.
 These are generally 1 byte instruction
 E.g. 1)MOV A,M (M=H+L)
 Move the data from M to Acc
 A M
 2) STAX B
 Stores the content of the Acc at the location
pointed by the contents of BC pair.
 A BC
Implicit / Implied addressing mode
In this type of instruction , generally operand
is not specified within the instruction and is
predermined.
Generally the operand is Acc.
Most of the logical group instruction belong to
this instruction .
These are single byte instruction.
E.g STC
Sets the carry flag in the flag register.
CMA
Complement the content of Acc
Instruction of Microprocessor 8085
 An instruction set is a group of commands for a CPU in
machine language.
They are grouped into 3 groups according to its
length as follows.
 1 byte instruction
 2 byte instruction
 3 byte instruction
1 byte instruction
 These instruction are having opcode and operand both
in 1 byte.
 These requires only 1 byte to store in memory.
 Opcode & operand  1byte
 E.g. MOV A,B
Instruction of Microprocessor 8085
2 byte instruction
 These instruction requires 2 bytes to store in memory.
 First byte gives opcode & 2nd byte give operand.
 Opcode1st byte and data/address2nd byte
 E.g. ADI FFH
3 byte instruction
 These instruction requires three bytes to store in memory.
 1st byte gives opcode and second and third byte gives 16 bit
address of memory location.
 2nd byte gives lower order address/data and 3rd byte gives higher
order address .
 Opcode 1st byte and low order 8 bit of address/data2nd byte
High order 8 bit of address/data 3rd byte
 E.g. LDA FFFFH,
 LXI H, FFE3 H
Classification of Instruction
Set
Data transfer group-MOV A,B-REG
Arithmetic Group-ADI O3H-IMMEDIATE
Logic Group-ANI O3H-IMMEDIATE
Branch Group
Stack , IO and Machine control Instruction
(PUSH B –DECREMEDTD BY 2 POP- ++ BY 2
Data Transfer Group
This group of instruction copies data from
one place to another place.
The content of source register are not
altered.
The data can be transferred from register
to register , memory to register and
register to memory.
E.g. MOV A , B copies the content of B to
A
BA
MVI A,03H Move immediately 03 into the
Acc.
Arithmetic Group
This group of instruction performs
arithmetic operation on data .
The arithmetic operation may be data
addition, subtraction, increment,
decrement etc.
E.g. ADI 03H Add immediately 03 with the
content of Acc, store result in Acc.
A=A+3
SUB B Subtract content of B register from
the Acc , store result in Acc.
A=A-B
Logic Group
This group of instruction performs logical
operation on data.
These instruction include AND,OR,EX-OR
etc.
E.g. ANI 03H AND logically 03 with the
content of Acc, store result in Acc.

ORA B OR logically content of B register

with the Acc, store result in Acc.
Branch Group
These instruction change the sequence of
flow of the program
There are 2 types of branch instruction
Condition branch instructions
In this type , control is transferred to
another memory location only if a
particular condition is satisfied.
Unconditional Branch instruction
In this type , control is transferred to
another memory location without any
condition.
Stack , IO and machine control
instruction.
These instruction control the stack (push
and pop) , I/O and Machine hardware.
E.g. PUSH B the content of BC register pair
is pushed to the stack , at the location
pointed by SP.
NOP no operation is performed . It is used
to produce delay time.
Data Transfer Group
MOV r1,r2 the contents of register r2 is moved
into register r1.
E.g. MOV A,B A B
No flag will be affected.
MOV r1,M the contents of the memory location
pointed by HL is moved into register r1.
E.g. MOV B,M BM[HL]
No flag will be affected.
MOV M , r2 the content of register r2 is moved
into the memory location pointed by HL .
E.g. MOV M,B [HL]MB
No flag will be affected.
Data Transfer Group
MVI r1,8-bit data[Move immediate 8 bit]
 The 8-bit data is immediately moved into the register
specified in the instruction.
 E.g. MVI C,23H
 C23H
 No flag will be affected.
LXI rp,16-bit data[Load register pair immediate]
 The 16 bit data is immediately moved into the
register pair specified in the instruction.
 E.g. LXI B,2300H
 BC2300H (B23,C00)
 No flag will be affected.
Data Transfer Group
MVI M,8-bit data[Move immediate 8 bit]
 The 8-bit data is immediately moved into the memory
location pointed by HL(memory pointer).
 E.g. MVI M,23
 [HL]23H
 No flag will be affected.
LDA 16-bit address[Load register pair immediate]
 The Acc is loaded with the contents of the memory location
whose address is given in the instruction itself.
 E.g. (Let[C500]=35H
 Instruction :LDA C500
 After execution [A]=35H
 [C500]=35H)
 No flag will be affected.
Data Transfer Group
STA 16-bit address
 The Acc content is stored into the memory location whose
address is specified in the instruction.
 E.g. ( Let [A]=35H
 Instruction : STA C500H
 After execution : [C500]=35H & [A]=35H )
 No flag will be affected.
LHLD 16-bit address
 The HL pair is loaded with the content of the locations
pointed by the given address and address+1.
 E.g. LHLD 2000 HL[2000] &[2001]
 i.e. L[2000]
 H[2001]
 No flag will be affected.
Data Transfer Group
SHLD 16-bit address
 The HL pair is stored into the locations pointed by the
given address and address+1.
 E.g. SHLD 2000 [2000]&[2001]
 i.e. 2000L,2001H
 No flag will be affected.
LDAX rp
 The Acc is loaded with the contents of memory
location pointed by value of the given register.
 E.g. LDAX B A[BC]
 i.e. if [BC]=2000 , A gets the value from location 2000
i.e. A2000.
 No flag will be affected.
Data Transfer Group
STAX rp
The content of Acc are transferred to the
memory location whose address is stored in
resister pair rp. The valid registers pairs are
B(i.e. B & C)
E.g. STAX B : [[BC]]A i.e. if [BC]=2000 ,
location 2000 will get the value of A .
i.e. [2000]A
No flag will be affected.
Data Transfer Group
PCHL (Load program counter with HL register
pair content)
 The program counter gets the contents of the HL
register pair.
 This statement causes a branch in the sequence of
the program.
 E.g. PCHL
 PCHL
 Let [H]=25 and [L]=39H
 Instruction : PCHL
 After execution [PC]=2539H
 No flag will be affected.
Data Transfer Group
SPHL (Copy H and L register to SP)
The stack pointer gets the contents of the
HL register pair.
This instruction is used for initializing the
stack pointer.
 E.g. SPHL SP HL
Let [H]=25H and [L]=59H
Instruction :SPHL
After execution [SP]=2559H
Data Transfer Group
XCHG [Exchange H and L with D and E]
This instruction exchange the contents of HL
pair and DE pair.
The content of register H are exchanged with
that of register D and the content of register L
are exchanged with that of register E.
E.g. let[H]=23H,[L]=32H,[D]=53H and [E]=55H
Instruction : XCHG
After execution: [H]=53H and [L]=55H
 [D]=23H and [E]=32H
No flag will be affected.
Arithmetic group
ADD R[Add register]
 This instruction adds the content of register R with the
Acc , stores result in the Acc.
 E.g. ADD B
 A A+B
 All flag may be affected.
ADD M[Add memory content to Acc]
 The content of Acc are added to the content of memory
location , whose address is stored in HL pair .
 The result is placed in Acc.
 All flags may be affected.
 E.g. ADD M
 AA+M[HL]
Arithmetic group
ADI DATA[Add immediate to Acc]
 This instruction adds the 8 bit immediate data to the
content of Acc.
 All flags may be affected.
 E.g. ADI 25H
 A A+25H
ADC r[Add register to Acc with Carry]
 This instruction adds the content of the register R with
the Acc and also adds the carry flag , and stores the
result in the Acc.
 E.g. ADC D
 AA+D+CY
 All flags may be affected.
Arithmetic group
ADC M[Add memory content to Acc with Carry]
 The contents of memory location whose address place in
HL register pair and content of CY are added to the
content of Acc.
 E.g. ADC M
 AA+M+CY
 All flag may be affected.
ACI DATA[Add immediate to Acc with carry]
 This instruction adds the immediate data with the Acc ,
and also adds the carry flag and stores the result in the
Acc.
 E.g. ACI 25
 AA+25H+CY
 All flag may be affected.
Arithmetic group[All flag may be
affected]
SUB r[Subtract register from Acc]
 AA-r
SUB M[ Subtract Memory from Acc]
 AA-M[HL]
SUI DATA[Subtract immediate data from Acc]
 AA-data
SBB r[subtract register and borrow from Acc]
 AA-r-cy
SBB M[Subtract Memory content and borrow from
Acc]
 A[A]-M[HL]-[CY]
SBI DATA[Subtract Immediate with Borrow]
 A[A]-data-[CY]
Arithmetic group[increment]

INR R[increment register content by 1]

This instruction increments the content of
the specified register.
The incremented value is stored back in the
same register.
E.g. INR B
BB+1
S , Z,P,AC flag may be affected[except CY
flag].
The register R can be A,B,C,D,E,Hand L.
Arithmetic group[increment]
INR M[increment memory by 1]
This instruction increments the contents of
memory location pointed by HL pair.
The incremented value is stored at the
same location.
E.g. INR M
MM+1
S , Z,P,AC flag may be affected[except CY
flag].
Arithmetic group[increment]
INX RP[increment register pair by 1]
This instruction increments the contents of
the specified register pair.
The incremented value is stored back in the
same register pair.
E.g. INX B
BCBC+1
No flag will be affected.
Arithmetic group[Decrement]
DCR R[Decrement register by 1]
The content of register is decremented by 1
and the results are stored in the same
place.
E.g. DCR B
BB-1
 S , Z,P,AC flag may be affected[except CY
flag].
Arithmetic group[Decrement]
DCR M[Decrement memory content by 1]
This instruction decrements the contents of
memory locations pointed by HL pair.
The decremented value is stored back at
the same location.
E.g. DCR M
MM-1
 S , Z,P,AC flag may be affected[except CY
flag].
Arithmetic group[Decrement]
DCX rp[Decrement register pair by 1]
This instruction decrements the content of
register pair by 1.
The decremented value is stored back in
the same register pair.
E.g. DCX B
BCBC-1 [ i.e. if [BC]=3001 then [BC]
becomes 3000]
No flag will be affected.
Arithmetic group(DAD rp)
 DAD rp[Add register pair to H and L register]
 The content of register pair rp are added to the
contents of H-L pair.
 Result is placed in H and L .
 Only carry flag is affected.
 E.g. Let [H]=03H , [L]=05 , [D]=15H and [E]=12H
 DAD D
 After execution [L]=05+12=17H
 [H]=03+15=18H
 [H-L]=1817H
 E.g. DAD B
39 0011 1001
12 0001 0010
 0100 1 0 1 14B [B=111011]
0100 1011
0000 0110
 0101 000151H
DAA(Decimal Adjust Acc)
 This instruction is used to get the answer in BCD from.
 The eight bit number in the Acc is adjusted to form
two four-bit binary coded decimal digits by this
instruction.
 If the value of the least significant 4 bits of the Acc
(A3-A0) is greater than 9 or if the AC flag is set. 06 is
added to low order 4-bits of Acc.
 If the value of the Most significant 4 bits of the Acc
(A7-A4) is greater than 9 or if the AC flag is set. 06 is
added to high order 4-bits of Acc.
 If both 4 LSBs and 4 MSBs of Acc are greater than 9
or AC and C flags are set respectively then 66 add to
the Acc content.
DAA(Decimal Adjust Acc)
E.g. Add 12(BCD) to 39(BCD)
8 4 2 1 8 4 2 1

39 BCD 0 0 1 1 1 0 0 1

12 BCD 0 0 0 1 0 0 1 0

+(51) BCD 0 1 0 0 1 0 1 1

4 B
DAA(Decimal Adjust Acc)
The binary sum is 4BH .but BCD Sum is
51H.
To adjust result add 6 to lower nibble
4B 0 1 0 0 1 0 1 1


06 0 0 0 0 0 1 1 0

51 0 1 0 1 0 0 0 1
Logical Group
AND
X Y Z(X.Y)

1 1 1

1 0 0

0 1 0

0 0 0

OR
X Y Z(X+Y)

1 1 1

1 0 1

0 1 1

0 0 0
Logical Group
ANA r[logical and with Acc]
The content of Acc are logically ANDed with
the content of register r.
Result is placed in Acc.
S,Z and P flags are modified.
The CY flag is reset and AC flag is set.
E.g. let [A]=25H and [B]=31H
Instruction :ANA B
A 25H 0 0 1 0 0 1 0 1
B 31H 0 0 1 1 0 0 0 1

AND  0 0 1 0 0 0 0 1

FLAG S0 Z0 X AC1 X P1 X CY0

ANA B
A=01
B=05
CHANGESS,Z,P
AC,C [AC1,C0]
0000 0001
0000 0101
0000 0001
Logical Group
ANA M[LOGICAL AND WITH MEMORY]
The contents Acc are logically ANDed with the
content of memory location, whose address is
stored in HL pair.
The result is placed in Acc.
The S,Z and P flags are modified.
The CY flag is reset and the AC flag is set.
E.g. let[A]=3BH , [HL]=D000H AND
[D000]=29H
A 3B 0 0 1 1 1 0 1 1
Instruction ANA M
HL 29 0 0 1 0 1 0 0 1

After execution
AND  0 0 1 0 1 0 0 1

FLAG S0 Z0 X AC1 X P0 X CY0

Logical Group
ANI data[ And immediate with Acc]
The contents of Acc are logically ANDed
with the 8-bit immediate data .
The result is placed in the Acc.
The S,Z and P flags are modified . CY
flag is reset and AC flag is set.
E.g. Let [A]=25
Instruction ANI 25
AA AND 25
Logical Group
ORA r[Logically OR with Acc]
The contents of Acc are logically ORed with
the contents register r.
The result is placed in Acc.
R may be any one of A,B,C,D,E,H and L.
Z,S,P are modified . AC and CY flags
are reset.
E.g. let [A]=50H and [B]=AAH
A 50 0 1 0 1 0 0 0 0
Instruction ORI 06H
DATA 06 0 0 0 0 0 1 1 O
 After execution
OR  0 1 0 1 0 1 1 0

FLAG S0 Z0 X AC0 X P1 X CY0

Logical Group
Similarly we have the other logical
instruction as follows:
ORA R
ORA M
ORI 8 bit data
EX-OR EX-OR
X Y Z(X Y)

0 0 0

0 1 1

1 0 1

1 1 0
Logical Group
XRA r[Exclusive OR with Acc]
The contents of Acc are logically exclusive –
ORed with the contents of register r.
The result is placed in Acc.
The r may be any one of the A,B,C,D,E,H,and L
register.
S,Z,P are modified and CY and AC flags
are reset.
Let [A]=25H and [B]=39H
A 25 0 0 1 0 0 1 0 1
Instruction XRA
B B
39 0 0 1 1 1 0 0 1

After execution
OR  0 0 0 1 1 1 0 0

FLAG S0 Z0 X AC0 X P0 X CY0

Logical Group
 Similarly we have the other instruction as follows:
 XRA R
 XRA M
 XRI 8 bit data
COMPARE
 CMP R
 Compares the contents of register R and Acc.
 Comparison essentially is subtraction. Hence , this
instruction performs A-R.
 It is very important to remember that the result
of this comparison is not stored in Acc, only the
flags are affected.
 The content of Acc remains unchanged.
Logical Group
The result of comparison is shown by
setting the flags as :
If [A]<[R] then CY flag is set to 1.
If [A]=[R] then Z flag is set to 1.
If [A]>[R] then Z and CY flags are reset.
The r may be any one of the A,B,C,D,E,H
and LConclusion
register. Zero Flag ‘Z’ Carry Flag ‘CY’

A>B 0 0

A=B 1 0

A<B 0 1
 CMP R
 A&R
 CMP B
 A=12H,B=20H
 ACC
 ABN
 CY1
 A=25H B=20H
 ACC
 ABN
 Z AND CY0
 A=15H B=15H
 ACC
 ABN
 Z1
Logical Group
E.g. Let[A] =15H and [H]=57H
Instruction CMP H
After execution CY=1, Z=0.
Conclusion Zero Flag ‘Z’ Carry Flag ‘CY’

A>B(ABN) 0 0

A=B 1 0

A<B(ACC) 0 1
Logical Group
CMP M[Compare Memory with Acc]
This instruction compares the content of
memory location whose address is stored in
HL pair with the content of Acc by
subtracting the content of memory location
from the content of Acc.
The content of Acc remains unchanged.
If [A]<[M] then CY flag is set to 1.
If [A]=[M] then Z flag is set to 1.
If [A]>[M] then
Conclusion
Z and
Zero Flag ‘Z’
CY flags are reset
Carry Flag ‘CY’
A>M(ABN) 0 0
A=M 1 0
A<M(ACC) 0 1
Logical Group
* CPI 8 bit-data[Compare immediate with
Acc]
STC [Set the Carry flag]
CY1
Only carry flag is affected.
CMC [Complements the Carry flag]
 [CY][CY]
Only carry flag is affected.
CMA[Complements the Acc]
A 1’s complement of A.
No flag is affected.
Rotate Instruction
RLC [Rotate Acc left]
The contents of Acc are rotated left by 1.
The contents of Acc are rotated to left by 1
bit position.
The bit
CY
A7A7is stored
A6 A5
in A4bit A0
A3
as
A2
well
A1
asA0 in
carry flag.
Rotate Instruction
RLC
 E.g. Let [A]=45H and [CY]=0
Instruction RLC
Before execution
cy A7 A6 A5 A4 A3 A2 A1 A0
0 0 1 0 0 0 1 0 1

After execution
Cy A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 1 0 1 0
Rotate Instruction
RLC
Thus [A]=27H and CY=1
Only CY flag is affected.
RRC[ Rotate Acc Right]
The contents of Acc are rotated right by 1.
The contents of Acc are rotated right by
one bit position. The bit A0 of Acc is stored
in the bit A7 as well as in carry flag.
The LSB goes to the Carry and the MSB.
Carry flag is affected.
CY A7 A6 A5 A4 A3 A2 A1 A0
Rotate Instruction
E.g. let [A]=83 and [CY]=0
Instruction RRC
Before executioncy  A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 0 0 1 1

After execution 
Cy A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 0 0 0 0 0 1

Thus [A]=C1H and CY=1

Rotate Instruction
RAL[Rotate Acc left through CY]
This instruction rotates the content of Acc
one position left through carry flag.
The MSB goes to the CY and the CY goes to
LSB.
CY flag is affected.
CY A7 A6 A5 A4 A3 A2 A1 A0
Rotate Instruction
RAL
 E.g. let [A]=55H and [CY]=1H
 Before execution

Cy A7 A6 A5 A4 A3 A2 A1 A0
1 0 1 0 1 0 1 0 1

 Inst RAL
 After execution
 Cy A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 1 0 1 0 1 1

 Thus [A]=ABH and [CY]=0H

Rotate Instruction
RAR [Rotate Acc right through CY]
The contents of Acc are rotated right by 1.
The LSB goes to the CY and CY goes to the
MSB.
The carry flag status is stored in bit A7 of
Acc and the bit A0 of Acc is stored in CY
flag. cy A7 A6 A5 A4 A3 A2 A1 A0

CY flag is affected.

Rotate Instruction
E.g. let[A]=3BH [CY]=0H
Before execution
 cy A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 1 0 1 1

Instruction RAR
After execution
cy A7 A6 A5 A4 A3 A2 A1 A0
 1 0 0 0 1 1 1 0 1

Thus [A]=1DH and [CY]=1

Branching group
CONDITION ADDR[jump
unconditionally]
The control is transferred unconditionally to
the memory location , whose address
specified in the instruction.
JCondition Addr[condition JUMP]
In condition
Condition Description
jumpJumpinstruction
True if
,Z=0the jump is
JNZ on not zero

taken onlyJZ if the condition

Jump on zero is true.
Z=1
JNC Jump on no carry C=0
JC Jump on carry C=1
JPO Jump on odd parity P=0
JPE Jump on even parity P=1
JP Jump on plus S=0
JM Jump on minus S=1
JMP ADDR
Jcondition
JNZ
JZ
JPE
JPO
JP
JM
JC
JNC
Machine control group
(Stack Operation)
PUSH rp [push register pair on stack]
 It pushes the given register pair into the stack.
 Push is the only operation ( not the only instruction) that
access the higher byte of a 2 byte number before the
lower byte.
 This is because the lower byte needs to be accessed first
during POP and the stack operation in LIFO.
 No stack operation uses 8 bit operands so we can not
push a single register , we have to push a register pair.
 E.g. PUSH B
 SP  SP-1
 [SP]B
 SP SP-2
 [SP]C
Machine control group
(Stack Operation)
PUSH rp
 E.g. let [SP]= D015H ,[B]=25H and [C]=55H
 Instruction : PUSH B
 After execution: [D014]=25H
 [D013]=55H
 and [SP]=D013H
 BeforeD013execution
10 stack D013 After execution
10

stackD014 20 D014 20

 D015
SP D015
 SP


Machine control group
(Stack Operation)
POP rp[ POP off Stack to register pair]
 [rl][SP]
 [rh][SP]+1
 [SP][SP]+2
 The contents of the memory location , whose address is
specified by the stack pointer are moved to low order
register of register pair rp.
 The contents of the memory location , whose address is
one more than the content of stack pointer are moved
to high order register of register pair.
 The SP is incremented by 2.
 E.g. Let [SP]=2001H
 Instruction : POPH
Machine control group
(Stack Operation)
Before execution stack After
2001 10
execution stack
2001 10

2002 20
SP 2002 20
2003
 2003

 SP

1
Machine control group
(Stack Operation)
XTHL[Exchange H and L with top of stack]
 [L][SP]
 [H][SP]+1
 The contents of the L register are exchanged with the content of
the location , whose address is stored in SP.
 The content of H register are exchanged with the next location.
 Contents of SP are not altered.
 E.g. let[H]=20H [L]=FFH
 Instruction XTHL
 Before execution After execution
 SP FF SP
[L]
AB [L]
20 [H]
CD [H]



Other instructions(I/O)
IN port[Input 8 bit data from an input port
to Acc]
A data
E.g. IN 10H
This instruction is used to read data from an I/O
port , whose address is given in the instruction.
This data can be read into the Acc only.

8-bit data is inputed from a port , whose

address is 10H.
No flags are affected.
Other instructions(I/O)
OUT port [output 8 bit data from Acc to an Output
port]
 Data  A
 8085 has 256 I/O ports having 8 bit address 00H
…..FFH.
 This instruction is used to send data from an Acc to I/O
port, whose address is given in the instruction.
 This data can be sent into the Acc only.
 E.g. OUT 32H
 When this instruction is executed , microprocessor
sends 8 bit data from Acc to selected port . whose
address is 32H.
 No flags are affected.
Other instructions(I/O)
EI [enable interrupt]
 EI means Interrupt Enable.
 This instruction is used to enable the interrupts in the
microprocessor.
 This instruction effects all the interrupts except TRAP.
 No flag will be affected.
 E.g. EI INTE1
DI [Disable interrupt]
 DI means disable interrupts.
 This instruction is used to disable the interrupts in the
microprocessor.
 This instruction effects all the interrupts except TRAP.
 No flag will be affected.
 DI INTE0
Acc of 8085 contains data 56H. What will be the
contents after the execution following instruction
independently.
A) CMA B) ANI ACH C) INR A
 A=56H
Instruction CMA
Before execution After execution

5 6
5 6
8 4 2 1 8 4 2 1
8 4 2 1 8 4 2 1
 1 0 1 0 1 0 0 1
0 1 0 1 0 1 1 0


ANI ACH
Instruction ANI ACH
After execution 8 4 2 1 8 4 2 1

A56H 0 1 0 1 0 1 1 0

 ACH 1 0 1 0 1 1 0 0

AND 0 0 0 0 0 1 0 0

Result [A]=04H
INR A
Instruction INR A
After execution

8 4 2 1 8 4 2 1

A56H 0 1 0 1 0 1 1 0

 +1 0 0 0 0 0 0 0 1
 Result A=57H
AND 0 1 0 1 0 1 1 1
H 5 7


 CLASSWORK
1) The Acc of 8085 contains data 43H. What will be
its contents after the execution following
instructions independently?
 A) CMA B)ANI 09H C)INR A
2) The Acc of 8085 microprocessor contains the
data 45H and register E contains the data 7BH.
What will be the content of Acc after execution of
each of following instruction independently.
 A) XRA E B) ADI C5H C)ORI 5BH
3) Acc contains data 2AH. What will be content of
Acc after execution of each instruction
independently.
 A) CMA B)ANI 05H C)STC
4) Acc contains 45H , register E contains 3BH . Write
the contents of Acc after execution of following
instructions independently.
 1) SUB E 2)XRA E 3) RRC 4) MOV E,A
5) If Acc contains data BCH , register C contains ADH
. What will be the content of Acc after execution of
each of the following instruction independently.
 1) SUB C 2)CMA 3)XRA C
6) The Acc contains the data A4H. What will be its
contents after execution of following instructions
independently.
 1) XRI 08H 2)CMA 3)SUB A
 8085 Microprocessor
Code

1) Write a program to do addition between

two 8 bit numbers. Two numbers are stored
in C030H & C031H . Store the result in
C032H.
ADDRESS LABEL MNEMONICS HEX COMMENT
CODE

OPCODE OPERAND

C000 START LXI H,C030H 21 Initialize Hl As A Memory Pointer

C001 30 Lower Address Byte

C002 C0 Upper Address Byte

C003 MOV A,M 7E Move The First Number In A reg

C004 INX H 23 Increment Hl Pointer By One

C005 ADD M 86 Add Acc Data With Hl Pointer Data

C006 STA CO32 32 Store Result In Memory Location

C007 32 Lower Address Byte

C008 C0 Upper Address Byte

C009 STOP RST 1 CF Stop Program Execution

Details After Program
Execution
Before execution After
execution
MEMORY DATA
MEMORY
LOCATION
DATA
LOCATION

C030 06 C030 06

C031 07 C031 07

C032 00 C032 0D
8085 Microprocessor Code

3) Write a program that subtracts the

number stored in C030H from the number
stored in C031H. Store the absolute
difference in memory location C032H as
result.
ADDRESS LABEL MNEMONICS HEX CODE COMMENT

OPCODE OPERAND

C000

C001
. LXI H,C030H 21

30
Initialize Hl As Memory Pointer

Lower Address Byte

C002 C0 Upper Address Byte

C003 MOV B,M 46 Move Subtracter To B Reg

C004 INX H 23 Increment Hl Pointer By 1

C005 MOV A,M 7E Move Minuend To A Reg.

C006 SUB B 90 Subtract A Minus B

C007 JP C00DH F2 If Result Is Positive Go To Label VP

C008 0D Lower Address Byte

C009 C0 Higher Address Byte

C00A CMA 2F Take 1’s Complement Of A Reg.

C00B ADI 01H C6 Add 1 To A Register To Get 2’s Complement

C00C 01

C00D VP INX H 23 Increment Hl By 1

C00E MOV M,A 77 Move A To Memory

C00F RST 1 CF Stop Program Execution

Details After Program
Execution
Before execution After execution

MEMORY DATA
MEMORY DATA LOCATION
LOCATION

C030 06
C030 06

C031 0A C031 07

C032 00 C032 04