Sharon priyanka
18251A04C0
To realize 4to1,8to1 Multiplexers and 1to4,1to8 Demultiplexers using verilog
Aim:to realize Multiplexer and deMultiplexer using verilog.
Software : Edaplayground
Program:
//4to1 mux:
//Test bench
module behtb4_1mux;
// Inputs
reg [3:0] a;
reg [1:0] s;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
beh4_1mux uut (
.a(a),
.s(s),
.y(y)
);
Initial
begin
$dumpfile(“dump.vcd”);
$dumpvars();
// Initialize Inputs
a = 0;
s = 0;
// Wait 100 ns for global reset to finish
#100;s=2'b00;a[0]=1;
#100;s=2'b01;a[1]=0;
#100;s=2'b01;a[1]=1;
#100;s=2'b10;a[2]=0;
#100;s=2'b10;a[2]=1;
#100;s=2'b11;a[3]=0;
#100;s=2'b11;a[3]=1;
// Add stimulus here
end
endmodule
CODE:
module beh4_1mux(a, s, y);
input [3:0] a;
input [1:0] s;
output reg y;
always @(a or s)
begin
case(s)
2'b00: y=a[0];
2'b01: y=a[1];
2'b10: y=a[2];
2'b11: y=a[3];
default: y=0;
endcase
end
endmodule
//8to1 mux
//TESTBENCH
// Code your testbench here
// or browse Examples
module behtb8_1mux;
// Inputs
reg [7:0] a;
reg [2:0] s;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
beh8_1mux uut (
.a(a),
.s(s),
.y(y)
);
initial
begin
$dumpfile("dump.vcd");
$dumpvars();
// Initialize Inputs
a = 0;
s = 0;
// Wait 10 ns for global reset to finish
#10;s=3'b000;a[0]=1;
#10;s=3'b001;a[1]=0;
#10;s=3'b001;a[1]=1;
#10;s=3'b010;a[2]=0;
#10;s=3'b010;a[2]=1;
#10;s=3'b011;a[3]=0;
#10;s=3'b011;a[3]=1;
#10;s=3'b100;a[4]=0;
#10;s=3'b100;a[4]=1;
#10;s=3'b101;a[5]=0;
#10;s=3'b101;a[5]=1;
#10;s=3'b110;a[6]=0;
#10;s=3'b110;a[6]=1;
#10;s=3'b111;a[7]=0;
#10;s=3'b111;a[7]=1; // Add stimulus here
end
endmodule
CODE:
// Code your design here
module beh8_1mux(a, s, y);
input [7:0] a;
input [2:0] s;
output reg y;
always @(a or s)
begin
case(s)
3'b000: y = a[0];
3'b001: y = a[1];
3'b010: y = a[2];
3'b011: y = a[3];
3'b100: y = a[4];
3'b101: y = a[5];
3'b110: y = a[6];
3'b111: y = a[7];
default: y = 0;
endcase
end
endmodule
//DEMULTIPLEXERS
//1to4
//TESTBENCH
// Code your testbench here
// or browse Examples
module behtb1_4demux;
// Inputs
reg a;
reg [1:0] s;
// Outputs
wire [3:0] y;
// Instantiate the Unit Under Test (UUT)
beh1_4demux uut (
.y(y),
.a(a),
.s(s)
);
initial
begin
$dumpfile("dump.vcd");
$dumpvars();
// Initialize Inputs
a = 1;
s = 0;
// Wait 10 ns for global reset to finish
#10;s=2'b00;
#10;s=2'b01;
#10;s=2'b10;
#10;s=2'b11;
// Add stimulus here
end
endmodule
CODE:
// Code your design here
module beh1_4demux(y, a, s);
input a;
input [1:0] s;
output reg [3:0] y;
always @(y or s)
begin
case(s)
2'b00:begin y[0]=a; y[3:1]=0; end
2'b01:begin y[1]=a; y[0]=0; end
2'b10:begin y[2]=a; y[1:0]=0; end
2'b11:begin y[3]=a; y[2:0]=0; end
default: y=0;
endcase
end
endmodule
//1to8
//TESTBENCH
// Code your testbench here
// or browse Examples
module behtb1_8demux;
// Inputs
reg a;
reg [2:0] s;
// Outputs
wire [7:0] y;
// Instantiate the Unit Under Test (UUT)
beh1_8demux uut (
.y(y),
.a(a),
.s(s)
);
initial
begin
$dumpfile("dump.vcd");
$dumpvars();
// Initialize Inputs
a = 1;
s = 0;
// Wait 10 ns for global reset to finish
#10;s=3'b000;
#10;s=3'b001;
#10;s=3'b010;
#10;s=3'b011;
#10;s=3'b100;
#10;s=3'b101;
#10;s=3'b110;
#10;s=3'b111;
// Add stimulus here
end
endmodule
CODE:
// Code your design here
module beh1_8demux(y, a, s);
input a;
input [2:0] s;
output reg [7:0] y;
always @(y or s)
begin
case(s)
3'b000:begin y[0]=a; y[7:1]=0; end
3'b001:begin y[1]=a; y[0]=0; end
3'b010:begin y[2]=a; y[1:0]=0; end
3'b011:begin y[3]=a; y[2:0]=0; end
3'b100:begin y[4]=a; y[3:0]=0; end
3'b101:begin y[5]=a; y[4:0]=0; end
3'b110:begin y[6]=a; y[5:0]=0; end
3'b111:begin y[7]=a; y[6:0]=0; end
default: y=0;
endcase
end
endmodule
Result: the 4to1,8to1 mux and 1to4,1to8 demux are realised in behavioral style in verilog using
edaplayground
