Computer Organization & Architecture

PEN-Drive / G-Drive Course / VOD & Tablet Users

Workbook

Computer Science Engineering

GATE / ESE / PSUs

Vishal Rawtiya

Sachin Tanwar
Computer Organization & Architecture
PEN-Drive / G-Drive Course / VOD & Tablet Users

Workbook
Computer Science

Copyright © All Rights Reserved

GATE ACADEMY ®

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Edition : COA-HPD-2021OCT

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 GATE Syllabus
Machine instructions and addressing modes. ALU, data‐path and control unit. Instruction
pipelining, pipeline hazards. Memory hierarchy: cache, main memory and secondary storage; I/O
interface (interrupt and DMA mode).

Table of Contents

Sr. Chapter Pages

1. Basics of Computer Organization……………………………………………….….…..… 1 to 2

2. Memory Hierarchy..…………………………..………………….....…………………………… 3 to 12

3. Machine Instruction, Instruction Cycle & Addressing Modes..………….…… 13 to 23

4. ALU, Data Path & Control Unit……………………..……….…………………...………… 24 to 27

5. Instruction Pipelining.……………..……………..………………..………….…………….… 28 to 36

6. IO Interface (Interrupt & DMA Modes).…..………………..………….…………….… 37 to 40

7. Miscellaneous…………………………………….…..………………..………….…………….… 41 to 44
 Video Lecture Information (Vishal Rawtiya)
Sr. Lecture Name Duration
Chapter 01 Basics of Computer Organization
Lecture 01 Syllabus and Flow of Subject (Part 1) 0:31:24
Lecture 02 Syllabus and Flow of Subject (Part 2) 0:36:34
Lecture 03 Functionality & Components of Computer 0:17:51
Lecture 04 Logical View of Memory 0:30:30
Lecture 05 System Bus 0:42:27
Lecture 06 Byte Addressable Vs Word Addressable Memory 0:21:12
Lecture 07 Endianness Mechanism 0:38:29
Lecture 08 Control Signals & Hardware Pins 0:42:52
Lecture 09 Memory Chip Representation (Part 1) 0:38:00
Lecture 10 Memory Chip Representation (Part 2) 0:14:47
Lecture 11 Memory Chip Representation (Part 3) 0:26:06
Lecture 12 Mandatory Registers or Special Purpose Registers 0:38:25
Lecture 13 Few Basic Terms 0:07:38
Lecture 14 Workbook Question 1 0:09:13
Lecture 15 Workbook Question 2 0:08:48
Lecture 16 Workbook Question 3 0:17:26
Lecture 17 Workbook Question 4 0:34:55
Chapter 02 Memory Organization
Lecture 01 Introduction To Memory Organization 0:47:59
Lecture 02 General Hierarchical Memory Organization 0:58:52
Lecture 03 Hierarchical Memory Access Time (Part 1) 0:21:04
Lecture 04 Hierarchical Memory Access Time (Part 2) 0:46:46
Lecture 05 Hierarchical Memory Access Time (Part 3) 0:36:19
Lecture 06 Hierarchical Memory Access Time (Part 4) 0:48:18
Lecture 07 Simultaneous Memory Organization & Its Access Time (Part 1) 0:45:49
Lecture 08 Simultaneous Memory Organization & Its Access Time (Part 2) 0:40:13
Lecture 09 Workbook Question 1 0:05:40
Lecture 10 Workbook Question 2 0:05:08
Lecture 11 Workbook Question 3 0:05:39
Lecture 12 Workbook Question 4 0:06:40
Lecture 13 Workbook Question 5 0:04:06
Lecture 14 Workbook Question 6 0:07:04
Lecture 15 Avg Access Time W.R.T. Block Transfer Time 0:34:10
Lecture 16 Workbook Question 7 0:19:23
Lecture 17 Workbook Question 8 0:07:20
Lecture 18 Workbook Question 9‐10 0:27:57
Lecture 19 Workbook Question 11 0:11:31
Lecture 20 Workbook Question 12 0:13:26
Lecture 21 Workbook Question 13 0:20:51
Lecture 22 Workbook Question 14 0:19:48
Lecture 23 Cache Memory 0:16:42
Lecture 24 Memory Organization (In Blocks) W.R.T. Cache Concept (Part 1) 0:50:08
Lecture 25 Memory Organization (In Blocks) W.R.T. Cache Concept (Part 2) 0:34:24
Lecture 26 Mapping Techniques & Need Of Mapping Techniques 0:21:54
Lecture 27 Fully Associative Mapping (Part 1) 0:50:03
Lecture 28 Fully Associative Mapping (Part 2) 0:59:15
Lecture 29 Fully Associative Mapping (Part 3) 0:51:42
Lecture 30 Direct Mapping (Part 1) 0:37:53
Lecture 31 Direct Mapping (Part 2) 0:30:56
Lecture 32 Direct Mapping (Part 3) 0:53:10
Lecture 33 Direct Mapping (Part 4) 0:42:09
Lecture 34 Direct Mapping (Part 5) Advantage & Disadvantage 0:26:56
Lecture 35 Workbook Question 15 0:06:36
Lecture 36 Workbook Question 16 0:03:24
Lecture 37 Workbook Question 17 0:09:49
Lecture 38 Workbook Question 18‐19 0:36:27
Lecture 39 Workbook Question 20‐21 0:45:40
Lecture 40 Workbook Question 22 0:12:28
Lecture 41 Workbook Question 23 0:06:04
Lecture 42 Set Associative Mapping (Part 1) 0:24:49
Lecture 43 Set Associative Mapping (Part 2) 0:46:30
Lecture 44 Set Associative Mapping (Part 3) 1:03:23
Lecture 45 Set Associative Mapping (Part 4) 0:36:13
Lecture 46 Types Of Cache Misses 0:49:50
Lecture 47 Locality Of Reference 0:13:13
Lecture 48 Workbook Question 24 0:10:40
Lecture 49 Workbook Question 25 0:13:19
Lecture 50 Workbook Question 26 0:13:32
Lecture 51 Workbook Question 27 0:20:21
Lecture 52 Workbook Question 28‐29 0:18:49
Lecture 53 Workbook Question 30‐32 0:55:55
Lecture 54 Replacement Policies 0:43:25
Lecture 55 Examples For Replacement Algorithms 0:29:11
Lecture 56 Workbook Question 33 0:06:42
Lecture 57 Workbook Question 34 0:09:01
Lecture 58 Workbook Question 35 0:20:26
Lecture 59 Workbook Question 36 0:28:28
Lecture 60 Need Of Updating Techniques (Part 1) 0:42:21
Lecture 61 Need Of Updating Techniques (Part 2) 0:25:27
Lecture 62 Write Through Updating Technique (Part 1) 0:46:35
Lecture 63 Write Through Updating Technique (Part 2) 0:19:17
Lecture 64 Write Through Updating Technique (Part 3) 0:55:34
Lecture 65 Write Through Updating Technique For Simultaneous Organization 0:55:38
Lecture 66 Write‐Back Updating Technique (Part 1) 1:00:59
Lecture 67 Write‐Back Updating Technique (Part 2) 0:26:27
Lecture 68 Multilevel Cache 1:00:20
Lecture 69 Inclusive, Exclusive & Non‐Inclusive Multi‐Level Cache 0:50:28
Lecture 70 Workbook Question 37 0:09:23
Lecture 71 Workbook Question 38 0:06:06
Lecture 72 Workbook Question 39 0:09:25
Lecture 73 Workbook Question 40 0:14:53
Lecture 74 Workbook Question 41 0:21:24
Lecture 75 Workbook Question 42 0:08:51
Lecture 76 Workbook Question 43 0:10:58
Lecture 77 Workbook Question 44 0:05:44
Lecture 78 Workbook Question 45 0:14:34
Lecture 79 Workbook Question 46 0:11:46
Chapter 03 Machine Instruction and Instruction Cycle
Lecture 01 Instruction Cycle & Instruction Fetch Sub‐Cycle (Part 1) 0:20:59
Lecture 02 Instruction Cycle & Instruction Fetch Sub‐Cycle (Part 2) 0:56:51
Lecture 03 Workbook Question 1 0:05:05
Lecture 04 Execute Cycle (The Beginning) 0:10:53
Lecture 05 Instruction Format (Begin) 0:17:57
Lecture 06 Stack Machine &0‐address Instn Format (Part 1) 0:28:14
Lecture 07 Stack Machine &0‐address Instn Format (Part 2) 0:36:37
Lecture 08 Accumulator Machine & 1‐ Address Instn Format (Part 1) 0:58:00
Lecture 09 Accumulator Machine & 1‐ Address Instn Format (Part 2) 0:50:03
Lecture 10 Accumulator Machine & 1‐ Address Instn Format (Part 3) 0:18:07
Lecture 11 General Register CPU Organization 0:14:55
Lecture 12 Reg‐Mem Reference Organization & 2‐Address Instn Format 0:36:40
Lecture 13 Register Register Reference Organization & 3‐Address Instn Format 0:46:47
Lecture 14 4‐Address Instn Format 0:12:36
Lecture 15 Workbook Question 2 0:09:44
Lecture 16 Workbook Question 3 0:13:01
Lecture 17 Workbook Question 4 0:09:56
Lecture 18 Workbook Question 5 0:17:14
Lecture 19 Workbook Question 6 0:08:10
Lecture 20 Workbook Question 7 0:23:59
Lecture 21 Workbook Question 8 0:19:59
Lecture 22 Workbook Question 9 0:10:07
Lecture 23 Workbook Question 10 0:11:27
Lecture 24 Workbook Question 11 0:16:47
Lecture 25 Workbook Question 12 0:10:28
Lecture 26 Addressing Modes (Part 1) 0:21:55
Lecture 27 Addressing Modes (Part 2) 0:32:18
Lecture 28 Addressing Modes (Part 3) 0:34:08
Lecture 29 Addressing Modes (Part 4) 0:30:56
Lecture 30 Addressing Modes (Part 5) 0:40:14
Lecture 31 Addressing Modes (Part 6) 0:33:44
Lecture 32 Addressing Modes (Part 7) 0:25:05
Lecture 33 Addressing Modes (Part 8) 0:48:26
Lecture 34 Addressing Modes (Part 9) 0:16:53
Lecture 35 Addressing Modes (Part 10) 0:12:55
Lecture 36 Workbook Question 13 0:02:35
Lecture 37 Workbook Question 14 0:02:37
Lecture 38 Workbook Question 15 0:07:51
Lecture 39 Workbook Question 16 0:09:45
Lecture 40 Workbook Question 17 0:10:49
Lecture 41 Workbook Question 18 0:08:29
Lecture 42 Workbook Question 19 0:01:48
Lecture 43 Workbook Question 20 0:07:55
Lecture 44 Workbook Question 21 0:13:11
Lecture 45 Revisiting Instn Cycle 0:29:54
Lecture 46 Flag Register & Flags (Part 1) 0:57:35
Lecture 47 Flag Register & Flags (Part 2) 0:37:00
Lecture 48 Flag Register & Flags (Part 3) 0:36:42
Lecture 49 Instruction Set (Part 1) Data Transfer Operation 0:16:49
Lecture 50 Instruction Set (Part 2) Data Manipulation Operation 0:14:40
Lecture 51 Instruction Set (Part 3) Shift Operation 0:48:07
Lecture 52 Instruction Set (Part 4) Rotate Operation 0:38:59
Lecture 53 Instruction Set (Part 5) Control Transfer Operation 0:42:09
Lecture 54 Instruction Set (Part 6) Subroutine 0:44:42
Lecture 55 Interrupt (Part 1) 0:47:47
Lecture 56 Interrupt (Part 2) Types of Interrupt 0:29:59
Lecture 57 Interrupt (Part 3) Interrupt Priority 0:20:11
Lecture 58 RISC vs CISC 0:12:40
Lecture 59 Workbook Question 22 0:12:38
Lecture 60 Workbook Questions 23‐25 0:19:45
Lecture 61 Workbook Question 26 0:13:03
Lecture 62 Workbook Question 27 0:05:25
Lecture 63 Workbook Question 28 0:09:39
Lecture 64 Workbook Question 29 0:02:44
Lecture 65 Workbook Question 30 0:15:03
Lecture 66 Workbook Questions 31‐32 0:17:49
Lecture 67 Workbook Questions 33‐34 0:12:29
Chapter 04 ALU, Data-Path & Control Unit
Lecture 01 Second Component of Computer (IE CPU) 0:28:29
Lecture 02 Microoperations (Part 1) 0:52:07
Lecture 03 Microoperations (Part 2) and Data Path 0:22:06
Lecture 04 Microinstruction & Microprogram 0:51:08
Lecture 05 Workbook Question 1 0:05:53
Lecture 06 Workbook Questions 2‐3 0:37:35
Lecture 07 Workbook Question 4 0:24:32
Lecture 08 Control Unit 0:18:00
Lecture 09 Task Of Processor Designer 0:30:33
 Lecture 10 Hardwired Control Unit Design (Part 1) 0:42:29
Lecture 11 Hardwired Control Unit Design (Part 2) 0:11:26
Lecture 12 Workbook Question 5 0:08:33
Lecture 13 Microprogrammed Control Unit (Part 1) 0:47:37
Lecture 14 Microprogrammed Control Unit (Part 2) 0:31:46
Lecture 15 eg 1 Microprogrammed Control Unit 0:14:26
Lecture 16 eg 2 Microprogrammed Control Unit 0:26:39
Lecture 17 Horizontal Vs Vertical Microprogrammed Control Unit 0:42:20
Lecture 18 Workbook Question 6 0:01:38
Lecture 19 Workbook Question 7 0:04:18
Lecture 20 Workbook Question 8 0:09:55
Lecture 21 Workbook Question 9 0:11:45
Lecture 22 Workbook Question 10 0:21:11
Chapter 05 Instruction Pipelining
Lecture 01 Performance and CPU Time 0:46:50
Lecture 02 Workbook Question 1 0:06:29
Lecture 03 Workbook Question 2 0:14:23
Lecture 04 Workbook Question 3 0:12:51
Lecture 05 Workbook Question 4 0:13:01
Lecture 06 High Performance Computer Architecture 0:21:44
Lecture 07 Introduction to Pipelining 0:41:31
Lecture 08 Performance Evaluation of Pipeline Processor 0:48:24
Lecture 09 Types of Pipeline 0:36:47
Lecture 10 Eg of Execution Time Calculation in Pipeline 0:07:04
Lecture 11 Eg of Execution Time Calculation for Asynchronous Pipeline 0:32:38
Lecture 12 Advanced Pipeline of RISC Processor 0:42:51
Lecture 13 Operations in The Stages of Pipeline 0:42:02
Lecture 14 Structural Dependency 0:38:40
Lecture 15 Data Dependency 0:56:10
Lecture 16 Control Dependency 0:56:28
Lecture 17 More About Dependency & Handling Mechanism (Part 1) 0:58:38
Lecture 18 More About Dependency & Handling Mechanism (Part 2) 0:53:04
Lecture 19 More About Dependency & Handling Mechanism (Part 3) 0:55:35
Lecture 20 Performance Evaluation of Pipeline Processor with Stalls 0:26:15
Lecture 21 Workbook Questions 5‐7 0:19:27
Lecture 22 Workbook Questions 8‐9 0:11:09
Lecture 23 Workbook Questions 10‐11 0:21:41
Lecture 24 Workbook Questions 12‐14 0:07:04
Lecture 25 Workbook Question 15 0:25:28
Lecture 26 Workbook Question 16 0:09:25
Lecture 27 Workbook Question 17 0:16:12
Lecture 28 Workbook Question 18 0:23:26
Lecture 29 Workbook Question 19 0:12:05
Lecture 30 Workbook Questions 20‐22 0:21:41
Lecture 31 Workbook Questions 23‐24 0:09:52
Lecture 32 Workbook Questions 25‐27 0:19:50
Lecture 33 Workbook Question 28 0:10:03
Lecture 34 Workbook Questions 29‐30 0:13:17
Chapter 06 IO Organization
Lecture 01 Magnetic Disk (Part 1) 0:55:58
Lecture 02 Magnetic Disk (Part 2) 0:28:55
Lecture 03 Magnetic Disk (Part 3) Disk Access Time 0:24:27
Lecture 04 E.g. of Disk Access Time & Data Transfer Time 0:23:58
Lecture 05 Bus Connection For CPU, Memory And IO 0:55:10
Lecture 06 IO Devices 0:13:31
Lecture 07 IO Transfer Modes & Programmed IO Mode 0:35:19
Lecture 08 Interrupt Driven 10 Mode 0:37:04
Lecture 09 DMA Mode (Part 1) 0:32:55
Lecture 10 DMA Mode (Part 2) 0:18:18
Lecture 11 DMA Mode (Part 3) 1:01:22
Lecture 12 Workbook Question 1 0:09:02
Lecture 13 Workbook Question 2 0:08:48
Lecture 14 Workbook Question 3 0:15:34
Lecture 15 Workbook Question 4 0:21:46
Lecture 16 Workbook Question 5 0:17:31
Lecture 17 Workbook Question 6 0:17:51
Lecture 18 Workbook Question 7 0:15:48
Lecture 19 Workbook Question 8 0:12:22
Chapter 07 Miscellaneous
Lecture 01 Overlapping Register Windows In Risc 0:49:10
Lecture 02 Workbook Questions 1‐2 0:06:52
Lecture 03 Workbook Questions 3‐8 0:44:26
Lecture 04 Refresh Operation In Dram Chip 0:14:57
Lecture 05 Workbook Questions 9‐10 0:24:15
Lecture 06 Workbook Questions 11‐12 0:05:38
Lecture 07 Reservation Table (Part 1) 0:31:46
Lecture 08 Reservation Table (Part 2) 0:42:44
Lecture 09 Workbook Question 13 0:27:40
Lecture 10 Booth Recoding Of Multiplier 0:50:32
Lecture 11 Booth Multiplication Algorithm 0:50:39
Lecture 12 Workbook Questions 14‐17 0:20:18
Video Lecture Information (Sachin Tanwar)
Sr. Lecture Name Duration
Lecture 00 Introduction to COA 0:14:45
Chapter 01 Basics
/ 01 Basic Components
Lecture 01 Basic Components 0:31:46
/ 02 Basic Terminolgies
Lecture 01 Concept of Binary 0:35:16
Lecture 02 Data Representation 0:46:55
Lecture 03 Data Representation Summary 0:15:23
Lecture 04 Address Computations 0:36:14
/ 03 Memory Basics
Lecture 01 Basic 0:48:39
Lecture 02 Addressability 0:49:58
Lecture 03 Questions 0:48:53
/ 04 Types of Pins & CPU Cycles
Lecture 01 Types of Pins & CPU Cycles 0:46:10
/ 05 System Bus & Ambiguity Issue
Lecture 01 System Bus & Ambiguity Issue 0:15:57
/ 06 IO Basics
Lecture 01 IO Basics 0:38:14
Chapter 02 Machine Instructions & Interrupts
/ 01 Instruction Fetch Cycle
Lecture 01 Instruction Fetch Cycle 0:31:58
Lecture 02 Instruction Format & Length Analysis 0:30:41
/ 02 Execution Cycle
Lecture 01 Execution Cycle (Stack CPU) 0:36:41
Lecture 02 Accumulator CPU 0:44:16
Lecture 03 Register CPU 0:16:09
Lecture 04 Examples 0:41:30
/ 03 Workbook Questions
Lecture 01 Workbook Questions 1‐6 0:39:48
Lecture 02 Workbook Questions 7‐12 0:37:34
/ 04 Flags or PSW
Lecture 01 Flags (Carry & Parity Flag) 0:28:07
Lecture 02 Auxiliary Carry & Sign Flag 0:40:09
Lecture 03 Zero Overflow & Control Flags 0:31:10
/ 05 Workbook Questions
Lecture 01 Workbook Questions 27 0:02:10
/ 06 Addressing Modes
Lecture 01 Introduction 0:39:32
Lecture 02 Memory & Register AM 0:40:13
Lecture 03 Indexed & Indexed Indirect AM 0:47:26
Lecture 04 Transfer of Control 0:35:57
/ 07 Workbook Questions
Lecture 01 Workbook Questions 13‐21 0:36:20
/ 08 Instruction Set
Lecture 01 Arithmetic & Logical Instructions 0:27:56
Lecture 02 Transfer of Control Instructions 0:33:33
Lecture 03 Subprograms Implementation 0:18:38
/ 09 Workbook Questions
Lecture 01 Workbook Questions 22‐26 0:35:23
/ 10 Interrupts
Lecture 01 Interrupts 0:24:02
Lecture 02 Processing & Type of Interrupts 0:29:53
/ 11 Workbook Questions
Lecture 01 Workbook Questions 28‐34 0:24:40
Chapter 03 RISC CISC
Lecture 01 RISC vs CISC 0:19:26
Lecture 02 Register Organization in RISC 0:13:02
Chapter 04 Microinstructions & Control Unit
Lecture 01 Registers and MicroInstructions 0:21:57
Lecture 02 Microprograms 0:29:16
Lecture 03 Basic CU Design 0:10:04
Lecture 04 Hardwired CU 0:42:43
Lecture 05 Micro Programmed Control Unit 0:49:34
Lecture 06 Workbook Questions 1‐5 0:39:18
Lecture 07 Workbook Questions 6‐10 0:26:03
Chapter 05 HPC and Pipelining
Lecture 01 Performance 0:26:00
Lecture 02 CPU Calculation Time 0:16:15
Lecture 03 Flynn 0:32:26
Lecture 04 Workbook Questions 1‐4 0:39:39
Lecture 05 Basics of Pipeline 0:40:28
Lecture 06 Types of Pipelines 0:27:31
Lecture 07 RISC Pipeline 0:35:54
Lecture 08 Workbook Questions 5‐10 0:48:03
 Lecture 09 Workbook Questions 11‐16 0:33:20
Lecture 10 Introduction to Hazards & Structural Hazards 0:19:08
Lecture 11 Data Hazard 0:20:45
Lecture 12 Workbook Questions 17‐18 0:18:33
Lecture 13 Control Hazarad 0:23:52
Lecture 14 Workbook Questions 19‐22 0:19:36
Lecture 15 Instruction Scheduling 0:29:52
Lecture 16 Workbook Questions 23‐30 0:41:48
Chapter 06 Memory Organization
/ 01 Memory Organization
Lecture 01 Memory Access 0:53:32
Lecture 02 Organisation & Locality of Reference 0:16:53
Lecture 03 Workbook Questions 1‐7 0:43:35
Lecture 04 Workbook Questions 8‐14 0:44:07
/ 02 Cache Memory
Lecture 01 Cache Memory 0:47:51
/ 03 Mapping
Lecture 01 Introduction 0:08:52
Lecture 02 Direct Mapping 0:42:29
Lecture 03 Associative 0:22:50
Lecture 04 Set Associative 0:52:33
Lecture 05 Important Update 0:03:54
/ 04 Workbook Questions
Lecture 01 Workbook Questions 15‐19 0:56:47
Lecture 02 Workbook Questions 20‐23 0:53:14
Lecture 03 Workbook Questions 24‐29 0:54:51
Lecture 04 Workbook Questions 30‐34 0:33:05
Lecture 05 Workbook Questions 35‐36 0:24:37
/ 05 Updating Techniques
Lecture 01 Updating Techniques 0:45:05
/ 06 Workbook Questions
Lecture 01 Workbook Questions 37‐39 0:06:13
/ 07 Multilevel Cache
Lecture 01 Multilevel Cache 0:09:05
/ 08 Workbook Questions
Lecture 01 Workbook Questions 40‐42 0:27:25
Lecture 02 Workbook Questions 43‐46 0:27:42
Chapter 07 IO Organization
Lecture 01 IO Organization 0:43:05
Lecture 02 Workbook Questions 1‐4 0:25:38
Lecture 03 Workbook Questions 5‐8 0:29:01
Chapter 08 Miscellaneous
Lecture 01 Workbook Questions 1‐12 0:35:12
Lecture 02 Workbook Questions 13 (Non‐Linear Pipeline) 0:34:52
Lecture 03 Booth's Algorithm (Part 1) 0:33:56
Lecture 04 Booth's Algorithm (Part 2) 0:36:21
Lecture 05 Workbook Questions 14‐15 0:07:53
 Basics of
1
Classroom Practice Questions
Computer Organization
Q.4 If the numerical value of a 2-byte unsigned
integer on a little-endian computer is 255
Q.1 The capacity of a memory unit is defined
more than that on a big-endian computer,
by the number of words multiplied by the
which of the following choices represent(s)
number of bits/word. How many separate
the unsigned integer on a little-endian
address and data lines are needed for a
computer?
memory of 4K 16 ?
(A) 0x6665 (B) 0x0001
(A) 10 address, 16 data lines
(B) 11 address, 8 data lines (C) 0x4243 (D) 0x0100

(C) 12 address, 16 data lines [GATE 2021 : IIT Bombay]

(D) 12 address, 12 data lines Self - Practice Questions
[GATE 1995 : IIT Kanpur] Q.1 How many address lines are needed to
Q.2 A processor can support a maximum address each memory location in a 2048*4
memory of 4GB, where the memory is memory chip?
word-addressable (a word consists of two (A) 10 (B) 11
bytes). The size of the address bus of the
(C) 8 (D) 12
processor is at least ______ bits.
[GATE 2016 : IISc Bangalore] Q.2 MIMD stands for

Q.3 The chip select logic for a certain DRAM (A) multiple instruction multiple data
chip in a memory system design is shown (B) multiple instruction memory data
below. Assume that the memory system has (C) memory instruction multiple data
16 address lines denoted by A15 to A0.
(D) multiple information memory data
What is the range of address (in
hexadecimal) of the memory system that Q.3 If each address space represents one byte of
can get enabled by the chip select (CS) storage space, how many address lines are
signal? needed to access RAM chips arranged in a
A15 4  6 array, where each chip is 8K  4 bits?
A14 (A) 13 (B) 14
A13 CS
A12 (C) 16 (D) 17
A11 Q.4 A computer uses RAM chips of 1024 1
(A) C800 to CFFF capacity.
(B) CA00 to CAFF How many chips are needed to provide
(C) C800 to C8FF memory capacity of 16 K bytes?
(D) DA00 to DFFF (A) 8 (B) 1024
[GATE 2019 : IIT Madras] (C) 16 (D) 128
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Computer Organization & Architecture [Work Book] 2 GATE ACADEMY®
Q.5 Which of the following affects the
processing power of CPU
I. Data bus width
II. Clock speed
III. Address bus width
(A) I and III (B) I, II and III
(C) Only I (D) Only II
Q.6 A computer uses ternary system instead of
the traditional system, An n bit string in the
binary system will occupy
(A) 3  n ternary digits
(B) 2n/3 ternary digits
(C) n log 2 3 f0 ternary digits
(D) n log3 2 f0 ternary digits

Answer Keys

Classroom Practice Questions

1. C 2. 31 3. A 4. A,D

Self - Practice Questions

1. B 2. A 3. D 4. D 5. B

6. D


 Memory Hierarchy :
2
Classroom Practice Questions
Cache, Main memory,
Secondary Memory
Q. 6 In a two-level cache system, the access
times of L1 and L2 caches are 1 and 8 clock
Q.1 Consider a system in which cache access is
cycles, respectively. The miss penalty from
5 times faster than main memory access,
the L2 cache to main memory is 18 clock
also cache access time is 5 ns less than
cycles. The miss rate of L1 cache is twice
average access time. If average access time
that of L2. The average memory access time
is 35 ns, then the hit rate of the cache
(AMAT) of this cache system is 2 cycles.
memory is.
The miss rates of L1 and L2 respectively are
Q.2 Consider a 2-level cache hierarchy. Level 1
cache access time is 10 nsec and hit ratio of (A) 0.111 and 0.056
level 1 cache is 0.85. If average access time (B) 0.056 and 0.111
to access a word from the given memory
(C) 0.0892 and 0.1784
organization is 100 nsec, then the miss
penalty of a miss in level 1 cache is (D) 0.1784 and 0.0892
Q.3 Consider a 2 level cache hierarchy where [GATE 2017 : IIT Roorkee]
average access time of memory system is Q.7 Consider a 3-level memory hierarchy with
10 nsec, main memory access time is 150 following specification
nsec. And miss penalty of a miss in top
level cache is 35 nsec. If hit rate of top level Level Access Block size Hit
cache is 0.8 and level 2 cache is 0.9, then time (in words) ratio
what is the summation of access times of (per word)
caches.
1 20 nsec - 0.8
(A) 20 (B) 23
(C) 25 (D) 28 2 25 nsec 2 0.9
Q.4 Consider a hierarchical memory 3 100 nsec 4 -
organization in which it takes 20 nsec to
access a word if it is a hit in cache and 100 What is the average access time for above
nsec if it is a miss in cache. By considering memory organization
the cache hit ratio of 0.9 the average access Q.8 Consider a memory system as shown below
time to access a word is________.
Q.5 Assume that for a certain processor, a read L1 Main
CPU Memory
request takes 50 nanoseconds on a cache 1 Word Cache 4 Word
miss and 5 nanoseconds on a cache hit. If the block size in L1 cache is of 4 words,
Suppose while running a program, it was
observed that 80% of the processor’s read L1 cache access time is 10 nsec, main
requests result in a cache hit. The average memory access time is 50 nsec and hit ratio
read access time in nanoseconds is ______. is 0.9, then what is the average access time
[GATE 2015 : IIT Kanpur] to access a word?
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Computer Organization & Architecture [Work Book] 4 GATE ACADEMY®

Common Data for Questions 9 & 10 all the eight words of the block, and finally
transmits the words of the requested block
A computer system has an L1 cache, an L2 cache, at the rate of 1 word per cycle. The
and a main memory unit connected as shown maximum bandwidth for the memory
below. The block size in L1 cache is 4 words. The system when the program running on the
block size in L2 cache is 16 words. The memory processor issues a series of read operations
access times are 2 nanoseconds, 20 nanoseconds
is___ × 106 bytes/sec
and 200 nanoseconds for L1 cache, L2 cache and
[GATE 2019 : IIT Madras]
main memory unit respectively.
Data Data Q.13 A CPU has a cache with block size 64
L1
Bus
L2
Bus
Main bytes. The main memory has k banks, each
Cache Cache Memory bank being c bytes wide. Consecutive c-
4 words 4 words
byte chunks are mapped on consecutive
Q.9 When there is a miss in L1 cache and a hit
banks with wrap-around. All the k banks
in L2 cache, a block is transferred from L2
can be accessed in parallel, but two
cache to L1 cache. What is the time taken
accesses to the same bank must be
for this transfer?
serialized. A cache block access may
(A) 2 nanoseconds (B) 20 nanoseconds involve multiple iterations of parallel bank
(C) 22 nanoseconds (D) 88 nanoseconds accesses depending on the amount of data
[GATE 2010 : IIT Guwahati] obtained by accessing all the k banks in
Q.10 When there is miss in both L1 cache and L2 parallel. Each iteration requires decoding
the bank numbers to be accessed in parallel
cache, first a block is transferred from main
memory to L2 cache, and then a block is and this takes k/2 ns. The latency of one
transferred from L2 cache to L1 cache. bank access is 80 ns. If c = 2 and k = 24,
then latency of retrieving a cache block
What is the time taken for this transfer?
starting at address zero from main memory
(A) 222 nanoseconds is
(B) 888 nanoseconds (A) 92 ns (B) 104 ns
(C) 902 nanoseconds (C) 172 ns (D) 184 ns
(D) 968 nanoseconds [GATE 2006 : IIT Kharagpur]
[GATE 2010 : IIT Guwahati] Q.14 A file system uses an in-memory cache to
cache disk blocks. The miss rate of the
Q.11 Consider a two-level cache hierarchy with
cache is shown in the figure. The latency to
L1 and L2 caches. An application incurs 1.4
read a block from the cache is 1 ms and to
memory accesses per instruction on
read a block from the disk is 10 ms. Assume
average. For this application, the miss rate
that the cost of checking whether a block
of L1 cache is 0.1; the L2 cache
exists in the cache is negligible. Available
experiences, on average, 7 misses per 1000
cache sizes are in multiples of 10 MB.
instructions. The miss rate of L2 expressed 90
correct to two decimal places is ________. 80

[GATE 2017 : IIT Roorkee] 70

60
Q.12 A certain processor deploys a single-level
Miss rate (%)

50
cache. The cache block size is 8 words and
40
the word size is 4 bytes. The memory 30
system uses a 60-MHz clock. To service a 20
cache miss, the memory controller first 10
takes 1 cycle to accept the starting address 0
0 10 20 30 40 50 60 70 80 90
of the block, it then takes 3 cycles to fetch Cache size (MB)
GATE ACADEMY® 5 Memory Hierarchy

The smallest cache size required to ensure Q.18 How many data cache misses will occur in
an average read latency of less than 6 ms is total?
______ MB. (A) 48 (B) 50
[GATE 2016 : IISc Bangalore] (C) 56 (D) 59
Q.15 Consider a machine with a byte addressable [GATE 2007 : IIT Kanpur]
main memory of 232 bytes divided into Q.19 Which of the following lines of the data
blocks of size 32 bytes. Assume that a direct cache will be replaced by new blocks in
mapped cache having 512 cache lines is accessing the array for the second time?
used with this machine. The size of the tag
(A) line 4 to line 11
field in bits is_____________.
(B) line 4 to line 12
[GATE 2017 : IIT Roorkee]
(C) line 0 to line 7
Q.16 Consider a computer system with a byte-
(D) line 0 to line 8
addressable primary memory of size 232
[GATE 2007 : IIT Kanpur]
bytes. Assume the computer system has a
direct-mapped cache of size 32 KB Common Data for Questions 20 & 21
(1KB = 210 bytes) , and each cache block is A CPU has a 32 KB direct mapped cache with 128-
of size 64 bytes. The size of the tag field is byte block size. Suppose A is a two dimensional
________ bits. array of size 512 × 512 with elements that occupy
[GATE 2021 : IIT Bombay] 8-bytes each. Consider the following two C code
segments, P1 and P2 .
Q.17 Consider a machine with a byte addressable
main memory of 220 bytes, block size of 16 P1 : for (i = 0; i < 512; i + + )
bytes and a direct mapped cache having 212 for ( j = 0 ; j < 512; j + + )
cache lines. Let the address of two
consecutive bytes in main memory be x + = A [i ][ j ];
(E201F)16 . What are the tag and cache line P2 : for (i = 0; i < 512; i + + )
address (in hex) for main memory address for ( j = 0 ; j < 512; j + + )
(E201F)16 ?
x + = A [ j ][i ];
(A) E , 201 (B) F , 201 P1 and P 2 are executed independently with the
(C) E , E 20 (D) 2, 01F same initial state, namely, the array A is not in the
cache and i, j , x are in registers. Let the number of
[GATE 2015 : IIT Kanpur]
cache misses experienced by P1 be M 1 and P 2 be
Common Data for Questions 18 & 19 M 2.

Consider a machine with a byte addressable main Q.20 The value of M 1 is

memory of 216 bytes. Assume that a direct mapped (A) 0 (B) 2048
data cache consisting of 32 lines of 64 bytes each
is used in the system. A 50 × 50 two-dimensional (C) 16384 (D) 262144
array of bytes is stored in the main memory starting [GATE 2006 : IIT Kharagpur]
from memory location 1100H. Assume that data Q.21 The value of the ratio M 1 /M 2 is
cache is initially empty. The complete array is
accessed twice. Assume that the contents of the (A) 0 (B) 1/16
data cache do not change in between the two (C) 1/8 (D) 16
accesses. [GATE 2006 : IIT Kharagpur]
Computer Organization & Architecture [Work Book] 6 GATE ACADEMY®
Q.22 A direct mapped cache memory of 1 MB (A) A1 and A4 are mapped to different
has a block size of 256 bytes. The cache has cache sets.
an access time of 3 ns and a hit rate of 94%. (B) A2 and A3 are mapped to the same
During a cache miss, it takes 20 ns to bring cache set.
the first word of a block from the main
(C) A3 and A4 are mapped to the same
memory, while each subsequent word takes
cache set.
5 ns. The word size is 64 bits. The average
memory access time in ns (round off to 1 (D) A1 and A3 are mapped to the same
decimal place) is______. cache set.

[GATE 2020 : IIT Delhi] [GATE 2020 : IIT Delhi]

Q.23 A certain processor uses a fully associative Q.26 The size of the physical address space of a
cache of size 16 kB, the cache block size is processor is 2 P bytes. The word length is
16 bytes. Assume that the main memory is 2W bytes. The capacity of cache memory is
byte addressable and uses a 32-bit address. 2 N bytes. The size of each cache block is
How many bits are required for the Tag and 2 M words. For a K-way set-associative
the Index fields respectively in the cache memory, the length (in number of
addresses generated by the processor? bits) of the tag field is
(A) 24 bits and 0 bits (A) P − N − log 2 K
(B) 28 bits and 4 bits
(B) P − N + log 2 K
(C) 24 bits and 4 bits
(C) P − N − M − W − log 2 K
(D) 28 bits and 0 bits
[GATE 2019 : IIT Madras] (D) P − N − M − W + log 2 K
Q.24 A block-set associative cache memory [GATE 2018 : IIT Guwahati]
consists of 128 blocks divided into four Q.27 In a k-way set associative cache, the cache
block sets. The main memory consists of is divided into v sets, each of which consists
16,384 blocks and each block contains 256 of k lines. The lines of a set are placed in
eight-bit words. sequence one after another. The lines in set
(i) How many bits are required for s are sequenced before the lines in set
addressing the main memory? ( s + 1). The main memory blocks are
(ii) How many bits are needed to represent numbered 0 onwards. The main memory
the TAG, SET and WORD fields? block numbered j must be mapped to any
[GATE 1990 : IISc Bangalore] one of the cache lines from

Q.25 A computer system with a word length of (A) ( j mod v )*k to ( j mod v )* k + ( k − 1)
32 bits has a 16 MB byte- addressable main (B) ( j mod v ) to ( j mod v ) + ( k − 1)
memory and a 64 KB, 4-way set associative
(C) ( j mod k ) to ( j mod k ) + (v − 1)
cache memory with a block size of 256
bytes. Consider the following four physical (D) ( j mod k )*v to ( j mod k )*v + (v − 1)
addresses represented in hexadecimal [GATE 2013 : IIT Bombay]
notation.
Common Data for Questions 28 & 29
A1 = 0x42C8A4,
Consider two cache organizations : The first one is
A2 = 0x546888,
32 KB 2-way set associative with 32-byte block
A3 = 0x6A289C, size. The second one is of the same size but direct
A4 = 0x5E4880 mapped. The size of an address is 32 bits in both
Which one of the following is TRUE? cases. A 2-to-1 multiplexer has latency of 0.6 ns
GATE ACADEMY® 7 Memory Hierarchy

while a k-bit comparator has a latency of k/10 ns. Q.32 The cache hit ratio for the initialization loop
The hit latency of the set associative organization is
is h1 while that of the direct mapped one is h2 . (A) 0% (B) 25%
Q.28 The value of h1 is (C) 50% (D) 75%
[GATE 2008 : IISc Bangalore]
(A) 2.4 ns (B) 2.3 ns
Q.33 Consider a 2-way set associative cache
(C) 1.8 ns (D) 1.7 ns
memory with 4 sets and total 8 cache blocks
[GATE 2006 : IIT Kharagpur] (0−7) and a main memory with 128 blocks
Q.29 The value of h2 is (0−127). What memory blocks will be
present in the cache after the following
(A) 2.4 ns (B) 2.3 ns
sequence of memory block references if
(C) 1.8 ns (D) 1.7 ns LRU policy is used for cache block
[GATE 2006 : IIT Kharagpur] replacement. Assuming that initially the
cache did not have any memory block from
Common Data for Questions 30 to 31
the current job?
Consider a machine having a two-way set 0 5 3 9 7 0 16 55
associative data cache of size 64 Kbytes and block
(A) 0 3 5 7 16 55 (B) 0 3 5 7 9 16 55
size 16 bytes. The cache is managed using 32 bit
(C) 0 5 7 9 16 55 (D) 3 5 7 9 16 55
virtual address and the page size is 4 Kbytes. A
program to be run on this machine begins as [GATE 2005 : IIT Bombay]
follows: Q.34 Consider a 4-way set-associative cache
Double ARR [1024] [1024] (initially empty) with total 16 cache blocks.
The main memory consists of 256 blocks
inti, j;
and the request for memory blocks is in the
/* Initialize array ARR to 0.0*/ following order:
for (i = 0; i < 1024; i + + ) 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8,
for ( j = 0; j < 1024; j + + ) 48, 32, 73, 92, 155
Which one of the following memory block
ARR [i ][ j ] = 0.0;
will NOT be in cache if LRU replacement
The size of double 8 bytes. Array ARR is located policy is used?
in memory starting at the beginning of virtual page (A) 3 (B) 8
0 × FF 000 and stored in row major order. The
(C) 129 (D) 216
cache is initially empty and no pre-fetching is done.
[GATE 2009 : IIT Roorkee]
The only data memory references made by the
program are those to array ARR…. Q.35 Consider a 2-way set associative cache with
256 blocks and uses LRU replacement.
Q.30 The total size of the tags in the cache
Initially the cache is empty. Conflict misses
directory is
are those misses which occur due to
(A) 32 Kbits (B) 34 Kbits contention of multiple blocks for the same
(C) 64 Kbits (D) 68 Kbits cache set. Compulsory misses occur due to
[GATE 2008 : IISc Bangalore] first time access to the block. The following
sequence of accesses to memory blocks
Q.31 Which of the following array elements has
the same cache index as ARR [0] [0]? (0, 128, 256, 128, 0, 128, 256, 128, 1, 129,
257, 129, 1, 129, 257, 129) is repeated 10
(A) ARR [0] [4] (B) ARR [4] [0]
times. The number of conflict misses
(C) ARR [0] [5] (D) ARR [5] [0] experienced by the cache is_________.
[GATE 2008 : IISc Bangalore] [GATE 2017 : IIT Roorkee]
Computer Organization & Architecture [Work Book] 8 GATE ACADEMY®
Q.36 An access sequence of cache block Q.39 The memory access time is 1 nanosecond
addresses is of length N and contains n for a read operation with a hit in cache, 5
unique block addresses. The number of nanoseconds for a read operation with a
unique block addresses between two miss in cache, 2 nanoseconds for a write
consecutive accesses to the same block operation with a hit in cache and 10
address is bounded above by k. What is the nanoseconds for a write operation with a
miss ratio if the access sequence is passed miss in cache. Execution of a sequence of
through a cache of associativity A ≥ k instructions involves 100 instruction fetch
exercising least-recently-used replacement operations, 60 memory operand read
policy? operations and 40 memory operand write
(A) n /N (B) 1/N operations. The cache hit-ratio is 0.9. The
average memory access time (in
(C) 1/A (D) k /n
nanoseconds) in executing the sequence of
[GATE 2014 : IIT Kharagpur] instructions is________.
Q.37 For inclusion to hold between two cache [GATE 2014 : IIT Kharagpur]
levels L1 and L2 in multi-level cache Q.40 A computer system has a level-1 instruction
hierarchy, which of the following are cache (1-cache), a level-1 data cache (D-
necessary? cache) and a level-2 cache (L2-cache) with
1. L1 must be write-through cache the following specifications:
2. L2 must be write-through cache Mapping Block
Capacity
3. The associativity of L2 must be greater Method size
than of L1 4K Direct
I-Cache 4 words
4. The L2 cache must be least as large as words Mapping
the L1 cache 2-way set
4K
(A) 4 only (B) 1 and 4 only D-Cache associative 4 words
words
(C) 1, 3 and 4 only (D) 1, 2, 3 and 4 mapping
4-way set
[GATE 2008 : IISc Bangalore] 64K 16
L2-Cache associative
Q.38 Assume a two-level inclusive cache words words
mapping
hierarchy, L1 and L2, where L2 is the larger
of the two. Consider the following The length of the physical address of a word
statements. in the main memory is 30 bits. The capacity
S1: Read misses in a write through L1 of the tag memory in the I-cache, D-cache
cache do not result in writebacks of and L2-cache is, respectively,
dirty lines to the L2 (A) 1K × 18-bit, 1K × 19-bit, 4K × 16-bit
(B) 1K × 16-bit, 1K × 19-bit, 4K × 18-bit
S2: Write allocate policy must be used in
(C) 1K × 16-bit, 512 × 18-bit, 1K × 16-bit
conjunction with write through caches
and no-write allocate policy is used (D) 1K × 18-bit, 512 × 18-bit, 1K × 18-bit
with writeback caches. [GATE 2006 : IIT Kharagpur]
Q.41 The read access times and the hit ratios for
Which of the following statements is
different caches in a memory hierarchy are
correct?
as given below.
(A) S1 is true and S2 is false
Read access time
(B) S1 is false and S2 is true Cache Hit ratio
(in nanoseconds)
(C) S1 is true and S2 is true I-cache 2 0.8
(D) S1 is false and S2 is false D-cache 2 0.9
[GATE 2021 : IIT Bombay] L2-cache 8 0.9
GATE ACADEMY® 9 Memory Hierarchy

The read access time of main memory is 90 Q.45 In a two-level virtual memory, the memory
nanoseconds. Assume that the caches use access time for main memory, tM = 10− 8
the referred-words-first read policy and the sec, and the memory access time for the
write back policy. Assume that all the
secondary memory, t D = 10− 3 sec. What
caches are direct mapped caches. Assume
that the dirty bit is always 0 for all the must be the hit ratio, H such that the access
blocks in the caches. In execution of a efficiency is within 80 percent of its
program, 60% of memory reads are for maximum value?
instruction fetch and 40% are for memory [GATE 1990 : IISc Bangalore]
operand fetch. The average read access Q.46 Consider a system with 2 level cache.
time in nanoseconds (up to 2 decimal Access times of Level 1 cache, Level 2
places) is________ cache and main memory are 1 ns, 10 ns, and
[GATE 2017 : IIT Roorkee] 500 ns respectively. The hit rates of Level 1
Q.42 If the associativity of a processor cache is and Level 2 caches are 0.8 and 0.9,
doubled while keeping the capacity and respectively. What is the average access
block size unchanged, which one of the time of the system ignoring the search time
following is guaranteed to be NOT within the cache?
affected? (A) 13.0 (B) 12.8
(A) Width of tag comparator (C) 12.6 (D) 12.4
(B) Width of set index decoder [GATE 2004 : IIT Delhi]
(C) Width of way selection multiplexor Self - Practice Questions
(D) Width of processor to main memory Q.1 Identify the true statement from the given
data bus statements. Program relocation at run time:
[GATE 2014 : IIT Kharagpur]
1. Requires transfer complete block to
Q.43 An 8 KB direct-mapped write-back cache is some memory locations
organized as multiple blocks, each of size
2. Requires both base address and
32-bytes. The processor generates 32-bit
relative address
address. The cache controller maintains the
3. Requires only absolute address
tag information for each cache block
(A) (1) (B) (1) and (2)
comprising of the following.
1 Valid bit, 1Modified bit (C) (1), (2) and (3) (D) (1) and (3)
As many bits as the minimum needed to Q.2 Which of the following mapping is not used
identify the memory block mapped in the for mapping process in cache memory?
cache. (A) Associative mapping
What is the total size of memory needed at (B) Direct mapping
the cache controller to storage meta-data (C) Set-Associative mapping
(tags) for the cache? (D) Segmented-page mapping
(A) 4864 bits (B) 6144 bits Q.3 Consider a system with 2 level cache.
(C) 6656 bits (D) 5376 bits Access times of Level 1, Level 2 cache and
[GATE 2011 : IIT Madras] main memory are 0.5 ns, 5 ns and 100 ns
Q.44 A cache line is 64 bytes. The main memory respectively. The hit rates of Level 1 and
has latency 32 ns and bandwidth 1 Level 2 caches are 0.7 and 0.8 respectively.
GBytes/s. The time required to fetch the What is the average access time of the
entire cache line from the main memory is: system ignoring the search time within
(A) 32 ns (B) 64 ns cache?
(C) 96 ns (D) 128 ns (A) 20.75 ns (B) 7.55 ns
[GATE 2006 : IIT Kharagpur] (C) 24.35 ns (D) 35.20 ns
Computer Organization & Architecture [Work Book]10 GATE ACADEMY®
Q.4 In a cache memory if total number of sets (A) 16384 (B) 512
are ‘s’, then the set offset is : (C) 2048 (D) 1024
8
(A) 2 (B) log 2 s Q.11 In designing a computer's cache system, the
(C) s 2
(D) s cache block (or cache line) sizes an
Q.5 Which of the following has lowest access important parameter. Which one of the
time? following statements is correct in this
context?
(A) Main Memory (B) Optical disk
(C) Cache (D) Registers (A) Smaller block size incurs lower cache
Q.6 Principle of locality is used in _____ miss penalty.
(A) Register (B) DMA (B) Smaller block size implies better
(C) Cache Memory (D) Interrupt spatial locality.
Q.7 How many total bits are required for a (C) Smaller block size implies smaller
direct-mapped cache with 128 KB of data cache tag.
and 1 word block size, assuming a 32-bit (D) Smaller block size implies lower cache
address ad 1 word size of 4 bytes? hit time.
(A) 2 Mbits (B) 1.7 Mbits Q.12 A cache memory needs an access time of 30
(C) 2.5 Mbits (D) 1.5 Mbits ns and main memory 150 ns, what is
Q.8 Which of the following is an efficient average access time of CPU (assume hit
method of cache updating? ratio = 80%)?
(A) Snoopy writes (B) Write through (A) 60 ns (B) 30 ns
(C) Write within (D) Buffered write (C) 150 ns (D) 70 ns
Q.9 A two-way set associative cache memory
Q.13 More than one word are put in one cache
unit with a capacity of 16 kB is built using
block to
a block size of 8words. The word length
is 32-bits. The physical address space is 4 (A) Exploit the temporal locality of
GB. reference in a program
The number of bits in the TAG, SET fields (B) Exploit the spatial locality of reference
are in a program
(A) 20, 7 (B) 19, 8 (C) Reduce the miss penalty
(C) 20, 8 (D) 21, 9 (D) None of the above
Q.10 A CPU has a 32 kB direct mapped cache [GATE 2001 : IIT Kanpur]
with 128−byte block size. Suppose A is
Q.14 Consider a direct mapped cache of size 32
a 2-d array of size 512×512 with elements
KB with block size 32 bytes. The CPU
that occupy 8 bytes each. Consider the
generates 32 bit addresses. The number of
code segment
bits needed for cache indexing and the
for(i=0;i<512;i++)
number of tag bits are respectively,
{
(A) 10,17 (B) 10,22
for(j=0;j<512;j++)
{ (C) 15,17 (D) 5,17
x +=A[i][j]; [GATE 2005 : IIT Bombay]
} Q.15 The width of the physical address on a
} machine is 40 bits. The width of the tag
Assuming that array is stored in field in a 512 KB 8-way set associative
order A[0][0] , A[0][1] , A[0][2]…, the cache is ______ bits.
number of cache misses is [GATE 2016 : IISc Bangalore]
GATE ACADEMY® 11 Memory Hierarchy

Q.16 A computer system has a 4 K word cache Q.21 A 4-way set-associative cache memory unit
organized in block-set-associative manner with a capacity of 16KB is built using a
with 4 blocks per set, 64 words per block. block size of 8 words. The word length is
The number of bits in the SET and WORD 32 bits. The size of the physical address
fields of the main memory address format space is 4 GB. The number of bits for the
is: TAG field is___.
(A) 15,40 (B) 6,4 [GATE 2014 : IIT Kharagpur]
(C) 7,2 (D) 4,6 Q.22 Consider a set-associative cache of size
[GATE 1995 : IIT Kanpur] 2KB (1KB = 210 bytes) with cache block
Q.17 Consider a 4-way set associative cache size of 64 bytes. Assume that the cache is
consisting of 128 lines with a line size of 64 byte-addressable and a 32 -bit address is
words. The CPU generates a 20-bit address used for accessing the cache. If the width of
of a word in main memory. The number of the tag field is 22 bits, the associativity of
bits in the TAG, LINE and WORD fields the cache is______.
are respectively. [GATE 2021 : IIT Bombay]
(A) 9, 6, 5 (B) 7, 7, 6
Q.23 Consider a small two-way set-associative
(C) 7, 5, 8 (D) 9, 5, 6 cache memory, consisting of four blocks.
[GATE 2007 : IIT Kanpur] For choosing the block to be replaced, use
Q.18 The main memory of a computer has 2c m the least recently used (LRU) scheme. The
blocks while the cache has 2c blocks. If the number of cache misses for the following
cache uses the set associative mapping sequence of block addresses is:
scheme with 2 blocks per set, then block k 8,12,0,12,8.
of the main memory maps to the set :
(A) 2 (B) 3
(A) (k mod m) of the cache
(C) 4 (D) 5
(B) (k mod c) of the cache
[GATE 2004 : IIT Delhi]
(C) (k mod 2c) of the cache
(D) (k mod 2cm) of the cache Common Data for Questions 24 & 25

[GATE 1999 : IIT Bombay] Consider a computer with a 4-ways set-

associative mapped cache of the following
Common Data for Questions 19 & 20
characteristics: a total of 1 MB of main
A computer has a 256 K Byte, 4-way set memory, a word size of 1 byte, a block size
associative, write back data cache with block size of 128 words and a cache size of 8 KB.
of 32 bytes. The processor sends 32 bit addresses
Q.24 The number of bits in the TAG, SET and
to the cache controller. Each cache tag directory
WORD fields, respectively are:
entry contains, in addition to address tag, 2 valid
bits. 1 modified bit and 1 replacement bit. (A) 7,6,7 (B) 8,5,7
Q.19 The number of bits in the tag field of an (C) 8,6,6 (D) 9,4,7
address is [GATE 2008 : IISc Bangalore]
(A) 11 (B) 14 Q.25 While accessing the memory location
(C) 16 (D) 27 0C795H by the CPU, the contents of the
[GATE 2012 : IIT Delhi] TAG field of the corresponding cache line
is:
Q.20 The size of the cache tag directory is
(A) 160 K bits (B) 136 K bits (A) 000011000 (B) 110001111
(C) 40 K bits (D) 32 K bits (D) 00011000 (D) 110010101
[GATE 2012 : IIT Delhi] [GATE 2008 : IISc Bangalore]
Computer Organization & Architecture [Work Book]12 GATE ACADEMY®
Q.26 A cache memory unit with capacity of N (D) A smaller block size incurs a smaller
words and block size of B words is to be cache miss penalty
designed. If it is designed as direct mapped [GATE 2014 : IIT Kharagpur]
cache, the length of the TAG field is 10 bits.
Q.28 Consider a main memory system that
If the cache unit is now designed as a 16-
consists of 8 memory modules attached to
way set-associative cache, the length of the
the system bus, which is one word wide.
TAG field is _________ bits.
When a write request is made, the bus is
[GATE 2017 : IIT Roorkee] occupied for 100 nanoseconds (ns) by the
Q.27 In designing a computer’s cache system, data, address, and control signals. During
the cache block (or cache line) size is an the same 100 ns, and for 500 ns thereafter,
important parameter. Which one of the the addressed memory module executes
following statements is correct in this one cycle accepting and storing the data.
context? The (internal) operation of different
(A) A smaller block size implies better memory modules may overlap in time, but
spatial locality only one request can be on the bus at any
time. The maximum number of stores (of
(B) A smaller block size implies a smaller
one word each) that can be initiated in 1
cache tag and hence lower cache tag
millisecond is ________.
overhead
(C) A smaller block size implies a smaller [GATE 2014 : IIT Kharagpur]
cache tag and hence lower cache hit
time
Answer Keys

Classroom Practice Questions

1. 0.966 2. 600 3. B 4. 28 5. 14
6. A 7. 38 8. 15 9. C 10. C
11. 0.05 12. 160 13. D 14. 30 15. 4.72
16. 17 17. A 18. C 19. A 20. C
21. B 22. 13.5 23. B 24. * 25. B
26. B 27. A 28. A 29. D 30. D
31. B 32. C 33. C 34. D 35. 76
36. A 37. A 38. A 39. 1.68 40. A
41. 4.72 42. D 43. C 44. C 45. 20
46. C
Self - Practice Questions
1. B 2. D 3. B 4. B 5. D
6. C 7. D 8. A 9. B 10. A
11. A 12. A 13. B 14. A 15. 24
16. D 17. D 18. B 19. C 20. A
21. 20 22. 2 23. C 24. D 25. A
26. 14 27. D 28. 10000
Classroom Practice Questions
* 24 (i) 22 (ii) 9, 5, 8

 Machine Instruction,

3
Classroom Practice Questions
Instruction Cycle
& Addressing Modes
Q.5 Consider a system in which 20-bit
instruction is placed in one memory cell.
Q.1 A CPU has 24-bit instructions. A program
There are 14, 2-address instructions and
starts at address 300 (in decimal). Which
1280, 0-address instructions supported by
of the following is a legal program counter
the processor. If system supports 256-word
(all values in decimal)?
memory, what is the number of 1-address
(A) 400 (B) 500 instructions supported?
(C) 600 (D) 700 Q.6 Consider a hypothetical processor in which
[GATE 2006 : IIT Kharagpur] 24-bit instruction is placed in one memory
cell. It supports an instruction format which
Q.2 A hypothetical processor supports 1 word
contains an opcode field, one register field,
instruction. There are a total of 110
to address one of the 30 processor registers
registers present in CPU, if there are 3, 2-
and one memory field. If processor
address instructions supported by the
supports 64K word memory and it has 5, 2-
processor having format, opcode followed
address instructions, then how many 1-
by the register address then what is the
address register reference instructions can
maximum number of 1-address instructions
be formulated?
that can be supported by the given
processor? (Assume 1 word = 2 Bytes). Q.7 A processor has 16 integer registers
Q.3 A hypothetical processor having 20-bit (R0, R1,  , R15) and 64 floating-point
instruction supports 12, 2-address registers (F0, F1,  , F63). It uses a 2-byte
instructions and 1000, 1-address instruction format. There are four
instructions. If 256-word memory is categories of instructions : Type-1, Type-2,
supported by the processor and instruction Type-3, and Type-4. Type-1 category
format consists of opcode followed by the consists of four instructions, each with 3
memory addresses for the operands. What integer register operands (3Rs). Type-2
is the maximum number of 0-address category consists of eight instructions, each
instructions that can be supported by the with 2 floating point register operands
given processor? (Assume Memory to be (2Fs). Type-3 category consists of fourteen
word addressable). instructions, each with one integer register
Q.4 A hypothetical processor supports 8-bit operand and one floating point register
instruction having 20 registers. What can be operand (1R + 1F). Type-4 category
minimum and maximum number of 1- consists of N instructions, each with a
address and 0-address instructions, such floating point register operand (1F).
that both the type of instructions are The maximum value of N is _______.
supported by the CPU? (Consider operand
to be register operand if required) [GATE 2018 : IIT Guwahati]

Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Computer Organization & Architecture [Work Book]14 GATE ACADEMY®
Q.8 A processor has 64 registers and uses 16-bit (ii) arithmetic instructions can have only
instruction format. It has two types of register or immediate operands
instructions : I-type and R-type. Each I-type The value of X is _______.
instruction contains an opcode, a register
name, and a 4-bit immediate value. Each R- [GATE 2017 : IIT Roorkee]
type instruction contains an opcode and two Q.11 The program below uses six temporary
register names. If there are 8 distinct I-type variables a, b, c, d, e, f.
opcodes, then the maximum number of a=1
distinct R-type opcodes is _______.
b = 10
[GATE 2020 : IIT Delhi]
c = 20
Q.9 Consider evaluating the following
expression tree on a machine with load- d=a+b
store architecture in which memory can be e=c+d
accessed only through load and store
f=c+e
instructions. The variables a, b, c,
d, and e are initially stored in memory. The b=c+e
binary operators used in this expression tree e=b+f
can be evaluated by the machine only
d=5+e
when operands are in registers. The
instructions produce result only in a return d + f
register. If no intermediate results can be Assuming that all operations take their
stored in memory, what is the minimum operands from registers, what is the
number of registers needed to evaluate this minimum number of registers needed
expression? to execute this program without
spilling?
+
(A) 2 (B) 3
(C) 4 (D) 6
− −
[GATE 2010 : IIT Guwahati]

a e Q.12 In a simplified computer the instructions

b +
are :
OP R j , Ri Performs R j or Ri and stores
c d
the result in register Ri .
(A) 2 (B) 9
(C) 5 (D) 3 OP m, Ri Performs val OP Ri and stores

[GATE 2011 : IIT Madras] the result in Ri . val denotes the

Q.10 Consider the expression content of memory location m.

  (b + c)   MOV m, Ri Moves the content of memory

(a − 1) *    + d . location m to register Ri .
 3  
Let X be the minimum number of registers MOV Ri , m Moves the content of register
required by an optimal code generation Ri to memory location m.
(without any register spill) algorithm for a
load/store architecture, in which The computer has only two registers, and
(i) only load and store instructions can OP is either ADD or SUB. Consider the
have memory operands and following basic block :
GATE ACADEMY® 15 Machine Instruction, Instruction Cycle

t1 = a + b Q.15 Consider the C struct defined below :

t2 = c + d struct data
{ int marks [100];
t3 = e − t2
char grade;
t4 = t1 − t3
};
Assume that all operands are initially in struct data student;
memory. The final value of the
The base address of student is available in
computation should be in memory. What is
register R1.
the minimum number of MOV instructions
in the code generated for this basic block? The field student grade can be accessed
efficiently using
(A) 2 (B) 3
(C) 5 (D) 6 (A) Post-increment addressing mode, (R1)
+
[GATE 2007 : IIT Kanpur]
(B) Pre-decrement addressing mode, –
Q.13 Match each of the high level language
(R1)
statements given on the left hand side with
the most natural addressing mode from (C) Register direct addressing mode, R1
those listed on the right hand side. (D) Index addressing mode, X (R1), where
1. A[1] = B[J]; X is an offset represented in 2’S
2. while (*A++); complement 16-bit representation.
3. int temp = *x; [GATE 2017 : IIT Roorkee]
Q.16 Consider a RISC machine where each
a. Indirect addressing
instruction is exactly 4 bytes long.
b. Indexed addressing
Conditional and unconditional branch
c. Auto-increment instructions use PC-relative addressing
(A) (1, c), (2, b), (3, a) mode with Offset specified in bytes to the
(B) (1, a), (2, c), (3, b) target location of the branch instruction.
(C) (1, b), (2, c), (3, a) Further the Offset is always with respect
(D) (1, a), (2, b), (3, c) to the address of the next instruction in the
program sequence. Consider the following
[GATE 2005 : IIT Bombay]
instruction sequence
Q.14 Which of the following is/are true of the
Instr. No. Instruction
auto-increment addressing mode?
i: add R2, R3, R4
I. It is useful in creating self-relocating
code. i+1: sub R5, R6, R7
II. If it is included in an Instruction Set i+2: cmp R1, R9, R10
Architecture, then an additional ALU i+3: beq R1, Offset
is required for effective address If the target of the branch instruction
calculation. is i, then the decimal value of the Offset is
III. The amount of increment depends on ____________.
the size of the data item accessed. [GATE 2017 : IIT Roorkee]
(A) I only Q.17 Consider a three word machine instruction
(B) II only ADD A[R0], @ B
(C) III only The first operand (destination) “A [R0]”
(D) II and III only uses indexed addressing mode with R0 as
[GATE 2008 : IISc Bangalore] the index register.
Computer Organization & Architecture [Work Book]16 GATE ACADEMY®
The second operand (source) “@ B” uses Q.21 Assume that EA = (X)+ is the effective
indirect addressing mode. A and B are address equal to the contents of location X,
memory address residing at the second and with X incremented by one word length
the third words, respectively. The first word after the effective address is calculated;
of the instruction specified the opcode, the EA = −(X) is the effective address equal to
index register designation and the source the contents of location X, with X
and destination addressing modes. During decremented by one word length before the
execution of ADD instruction, the two effective address is calculated; EA = (X)−
operands are added and stored in the is the effective address equal to the contents
destination (first operand). of location X, with X decremented by one
The number of memory cycles needed word length after the effective address is
during the execution cycle of the instruction calculated. The format of the instruction is
is (opcode, source, destination), which means
(destination ← source op destination).
(A) 3 (B) 4 Using X as a stack pointer, which of the
(C) 5 (D) 6 following instructions can pop the top two
elements from the stack, perform the
[GATE 2005 : IIT Bombay]
addition operation and push the result back
Q.18 A machine has a 32-bit architecture, with 1- to the stack.
word long instructions. It has 64 registers,
(A) ADD (X)−, (X)
each of which is 32 bits long. It needs to
support 45 instructions, which have an (B) ADD (X), (X)−
immediate operand in addition to two (C) ADD −(X), (X)+
register operands. Assuming that the
immediate operand is an unsigned integer, (D) ADD −(X), (X)
the maximum value of the immediate [GATE 2008 : IISc Bangalore]
operand is _______.
Q.22 Consider a computer system consisting of
[GATE 2014 : IIT Kharagpur] registers R1, R2, R3 and MEMORY[X]
Q.19 A processor has 40 distinct instructions and denotes the content at the memory location
24 general purpose registers. A 32-bit of X. Assume memory is byte addressable.
instruction word has an opcode, two Size
register operands and an immediate Instruction Semantics
(bytes)
operand. The number of bits available for
MOV R1
the immediate operand field is _________ R1← M[5000] 4
(5000)
[GATE 2016 : IISc Bangalore]
MOV R2 (R3) R2← M[R3] 4
Q.20 Consider a processor with 64 registers and
ADD R2,R1 R2←R1+R2 2
an instruction set of size twelve. Each
instruction has five distinct fields, namely, MOV(R3), R2 M[R3]← R2 4
opcode, two source register identifiers, one
INC R3 R3← R3+1 2
destination register identifier, and a twelve-
bit immediate value. Each instruction must DEC R1 R1← R1–1 2
be store in memory in a byte-aligned Branch if non- 2
fashion. If a program has 100 instructions, BNEZ 1004 zero to the
the amount of memory (in bytes) consumed absolute address
by the program text is _______
HALT Stop 1
[GATE 2016 : IISc Bangalore]
 GATE ACADEMY® 17 Machine Instruction, Instruction Cycle

Assume that the content of the memory Q.24 Consider the data given in above question.
location 5000 is 10 and the content of the Assume that the memory is word
register R3 is 3000. The content of each of addressable. After the execution of this
the memory locations from 3000 to 3010 is program, the content of memory location
50. The instruction sequence starts from the 2010 is :
memory location 1000. All the numbers are (A) 100 (B) 101
in decimal format. Assume that the memory
(C) 102 (D) 110
is byte addressable.
[GATE 2007 : IIT Kanpur]
After the execution of the program, the
content of memory location 3010 is __. Q.25 Consider the data given in above questions.
Assume that the memory is byte
[GATE 2021 : IIT Bombay]
addressable and the word size is 32 bits. If
Common Data Questions 23, 24 & 25 an interrupt occurs during the execution of
the instruction “INC R3”, what return
Consider the following program segment. Here R1,
address will be pushed on to the stack?
R2 and R3 are the general purpose registers.
(A) 1005 (B) 1020
Instruction Operation Size (in
(C) 1024 (D) 1040
words)
[GATE 2007 : IIT Kanpur]
MOV R1,(3000) R1 ← M[3000] 2
Q.26 Following table indicates the latencies of
LOOP : operations between the instruction
MOV R2, (R3) R2 ← M[R3] 1 producing the result and instruction using
the result.
ADD R2, R1 R2 ← R2 + R1 1
Instruction
Instruction using
MOVE (R3),R2 M [R3] ← R2 1 producing the Latency
the result
INC R3 1 result
ALU Operation ALU Operation 2
DEC R1 R1 ← R1 − 1 1
ALU Operation Store 2
BNZ LOOP Branch on not 2
zero Load ALU Operation 1

HALT Stop 1 Load Store 0

Q.23 Assume that the content of memory Consider the following code segment:
location 3000 is 10 and the content of the
Load R1,Loc1; Load R1 from
register R3 is 2000. The content of each of
memory location Loc1
the memory locations from 2000 to 2010 is
100. The program is loaded from the Load R2, Loc2; Load R2 from
memory location 1000. All the numbers are memory location Loc 2
in decimal. Add R1, R2, R1; Add R1 and R2 and
Assume that the memory is word save result in R1
addressable. The number of memory Dec R2; Decrement R2
references for accessing the data in Dec R1; Decrement R1
executing the program completely is :
Mpy R1, R2, R3; Multiply R1 and R2
(A) 10 (B) 11 and save result in R3
(C) 20 (D) 21 Store R3, Loc3; Store R3 in memory
[GATE 2007 : IIT Kanpur] location Loc 3
Computer Organization & Architecture [Work Book]18 GATE ACADEMY®
What is the number of cycles needed to The content of PC just before the fetch of a
execute the above code segment assuming CALL instruction is (5FA0)16 .After
each instruction takes one cycle to execute? execution of the CALL instruction, the
(A) 7 (B) 10 value of the stack pointer is
(C) 13 (D) 14 (A) (016A)16 (B) (016C)16
[GATE 2007 : IIT Kanpur]
(C) (0170)16 (D) (0172)16
Q.27 The following are some events that occur
[GATE 2015 : IIT Kanpur]
after a device controller issues an interrupt
while process L is under execution. Q.29 A processor that has the carry, overflow and
sign flag bits as part of its program status
P. The processor pushes the process
word (PSW) performs addition of the
status of L onto the control stack.
following two 2's complement
Q. The processor finishes the execution of
numbers 01001101 and 11101001. After
the current.
the execution of this addition operation, the
R. The processor executes the interrupt status of the carry, overflow and sign flags,
service routine. respectively will be:
S. The processor pops the process status (A) 1, 1, 0 (B) 1, 0, 0
of L from the control stack.
(C) 0, 1, 0 (D) 1, 0, 1
T. The processor loads the new PC value
[GATE 2008 : IISc Bangalore]
based on the interrupt.
Q.30 Consider a new instruction named branch-
Which of the following is the correct order
on-bit-set (mnemonic bbs). The instruction
in which the events occur?
“bbs reg, pos, label” jumps to label if bit in
(A) QPTRS (B) PTRSQ position pos of register operand reg is one.
(C) TRPQS (D) QTPRS A register is 32 -bits wide and the bits are
[GATE 2018 : IIT Guwahati] numbered 0 to 31, bit in position 0 being the
Q.28 Consider a processor with byte-addressable least significant. Consider the following
memory. Assume that all registers, emulation of this instruction on a processor
including Program Counter (PC) and that does not have bbs implemented.
Program Status Word (PSW), are of size 2 temp ← reg and mask
bytes. A stack in the main memory is Branch to label if temp is non-zero. The
implemented from memory location variable temp is a temporary register. For
(0100)16 and it grows upward. The stack correct emulation, the variable mask must
be generated by
pointer (SP) points to the top element of the
stack. The current value of SP is (016E)16 . (A) mask ← 0x1 << pos

The CALL instruction is of two words; the (B) mask ← 0xffffffff << pos
first word is the op-code and the second (C) mask ← pos
word is the starting address of the
(D) mask ← 0xf
subroutine (one word = 2 bytes). The CALL
instruction is implemented as follows : [GATE 2006 : IIT Kharagpur]
• Store the current value of PC in the Common Data Questions 31 & 32
stack.
Consider the following assembly language
• Store the value of PSW register in the program for a hypothetical processor. A, B,
stack. and C are 8-bit registers. The meanings of
• Load the starting address of the various instructions are shown as
subroutine in PC. comments.
GATE ACADEMY® 19 Machine Instruction, Instruction Cycle

MOV B, ; B←0 (A) RRC A, # 1

#0 (B) NOP; no operation
MOV C, ; C←8 (C) LRC A, # 1; left rotate A through
#8 carry flag by one bit
Z: CMP C, # ; compare C with 0 (D) ADD A, # 1
0 [GATE 2003 : IIT Madras]
JZX ; jump to X if zero
Common Data Questions 33 & 34
flag is set
SUB C, # ; C←C–1 Consider the following program segment for a
1 hypothetical CPU having three user registers R1,
R2 and R3.
RRC A, # ; right rotate A
1 through carry by Instruction Operation Instruction
Size
one bit. Thus: if the
(in words)
initial values of A
and the carry flag MOV R1,5000 ; R1 ← 2

are a7  a0 and c0 Memory[5000]

respectively, their MOV R2,(R1) ; R2 ← 1

values after the Memory[(R1)]

execution of this ADD R2,R3 ; R2 ← R2 + R3 1
instruction will be MOV 6000, R2 ; Memory[6000] 2
c0 a7  a1 and a0 ← R2
respectively HALT ; Machine halts 1
JC Y ; jump to Y if carry
flag is set Q.33 Consider that the memory is byte
JMP Z ; jump to Z addressable with size 32 bits, and the
program has been loaded starting from
Y: ADD B, ; B←B+1
memory location 1000 (decimal). If an
#1
interrupt occurs while the CPU has been
JMP Z ; jump to Z halted after executing the HALT
X: instruction, the return address (in decimal)
saved in the stack will be
Q.31 If the initial value of register A is A0 the (A) 1007 (B) 1020
value of register B after the program (C) 1024 (D) 1028
execution will be
[GATE 2004 : IIT Delhi]
(A) the number of 0 bits in A0
Q.34 Let the clock cycles required for various
(B) the number of 1 bits in A0 operations be as follows : Register to/from
memory transfer : 3 clock cycles ADD with
(C) A0
both operands in register : 1 clock cycle
(D) 8 Instruction fetch and decode : 2 clock
[GATE 2003 : IIT Madras] cycles per word, then total number of clock
Q.32 Which of the following instructions when cycles required to execute the program is
inserted at location X will ensure that the (A) 29 (B) 24
value of register A after program execution (C) 23 (D) 20
is the same as its initial value? [GATE 2004 : IIT Delhi]
Computer Organization & Architecture [Work Book]20 GATE ACADEMY®

Self - Practice Questions (A) (X, III) (Y, I) (Z, II)

Q.1 For computers based on three-address (B) (X, II) (Y, III) (Z, I)
instruction formats, each address field can (C) (X, III) (Y, II) (Z, I)
be used to specify which of the following : (D) (X, I) (Y, III) (Z, II)
S1 : A memory operand [GATE 2001 : IIT Kanpur]
S2 : A processor register Q.5 In absolute addressing mode
S3 : An implied accumulator register. (A) the operand is inside the instruction
(A) Either S1 or S2 (B) the address of the operand is inside the
(B) Either S2 or S3 instruction.
(C) Only S2 and S3 (C) the register containing the address of
(D) All of S1, S2 and S3 the operand is specified inside the
[GATE 2015 : IIT Kanpur] instruction.
Q.2 Which of the addressing modes permits (D) the location of the operand is implicit
relocation without any change whatsoever [GATE 2002 : IISc Bangalore]
in the code? Q.6 Which of the following addressing modes
(A) Indirect addressing are suitable for program relocation at run
(B) Indexed addressing time?
(C) Base register addressing. 1. Absolute addressing
(D) PC relative addressing. 2. Based addressing
[GATE 1998 : IIT Delhi] 3. Relative addressing
Q.3 The most appropriate matching for the 4. Indirect addressing
following pairs (A) 1 and 4 (B) 1 and 2
List I (C) 2 and 3 (D) 1, 2 and 4
X : Indirect addressing [GATE 2004 : IIT Delhi]
Y : Immediate addressing Q.7 Which of the following statements about
Z : Auto decrement addressing relative addressing mode is FALSE?
List II (A) It enables reduced instruction size
1. Loops (B) It allows indexing of array element
2. Pointers with same instruction
3. Constants (C) It enables easy relocation of data
(A) X-3, Y-2, Z-1 (B) X-1, Y-3, Z-2 (D) It enables faster address calculation
(C) X-2, Y-3, Z-1 (D) X-3, Y-1, Z-2 than absolute addressing
[GATE 2000 : IIT Kharagpur] [GATE 2006 : IIT Kharagpur]
Q.4 Which is the most appropriate match for the Q.8 Consider a hypothetical processor with an
items in the first column with the items in instruction of type LW R1, 20(R2), which
the second column during execution reads a 32-bit word from
X. Indirect Addressing memory and stores it in a 32-bit register R1.
Y. Indexed Addressing The effective address of the memory
location is obtained by the addition of a
Z. Base Register Addressing
constant 20 and the contents of register R2.
I. Array implementation Which of the following best reflects the
II. Writing re-locatable code addressing mode implemented by this
III. Passing array as parameter instruction for operand in memory?
GATE ACADEMY® 21 Machine Instruction, Instruction Cycle

(A) Immediate Addressing Q.13 For a memory system, the cycle time is
(B) Register Addressing (A) Same as the access time
(C) Register Indirect Scaled Addressing (B) Longer than the access time
(D) Base Indexed Addressing
(C) Shorter than the access time
[GATE 2011 : IIT Madras]
(D) Multiple of the access time
Q.9 The memory locations 1000, 1001 and
1020 have data values 18,1 and 16 Q.14 The part of machine level instruction,
respectively before the following program which tells the central processor what has
is executed. to be done, is
MOVI R s ,1 ; Move immediate (A) Operation code (B) Address
LOAD R d ,1000(R s ) ; Load from memory (C) Locator (D) Flip flop
ADDI R d ,1000 ; Add immediate Q.15 Consider the following x86 - assembly
STOREI 0(R d ), 20 ; Store immediate language instructions :
Which of the statements below is TRUE MOV AL, 153
after the program is executed? NEG AL
(A) Memory location 1000 has value 20
The contents of the destination register AL
(B) Memory location 1020 has value 20 (in 8-bit binary notation), the status of
(C) Memory location 1021 has value 20 Carry Flag (CF) and Sign Flag (SF) after
(D) Memory location 1001 has value 20 the execution of above instructions, are
Q.10 Which of the following statements is true? (A) AL = 0110 0110; CF = 0; SF = 0
(A) ROM is a Read/Write Memory.
(B) AL = 0110 0111; CF = 0; SF = 1
(B) PC points to the last instruction that
was executed. (C) AL = 0110 0110; CF = 1; SF = 1
(C) Stack works on the principle of LIFO (D) AL = 0110 0111; CF = 1; SF = 0
(D) All the instructions affect the flags.
Q.16 Consider the following statements :
[GATE 1995 : IIT Kanpur]
(i) Auto increment addressing mode is
Q.11 Which of the following is not a form of
useful in creating self-relocating code.
memory?
(A) Instruction cache (ii) If auto addressing mode is included in
an instruction set architecture, then and
(B) Instruction register
additional ALU is required for
(C) Instruction opcode
effective address calculation.
(D) Translation look aside buffer
(iii) In auto increment addressing mode,
[GATE 2002 : IISc Bangalore]
the amount of increment depends on
Q.12 A computer uses a memory unit with 256 K
the size of the data item accessed.
word of 32 bits each. A binary instruction
code is stored in one word of memory. The Which of the above statements is/are true?
instruction has four parts : an indirect bit, Choose the correct answer from the code
an operation code and a register code part given below :
to specify one of 64 registers and an address Code :
part. How many bits are there in operation
(A) (iii) only
code, the register code part and the address
part? (B) (ii) and (iii) only
(A) 7, 7, 18 (B) 18, 7, 7 (C) (i) and (ii) only
(C) 7, 6, 18 (D) 6, 7, 18 (D) (ii) only
Computer Organization & Architecture [Work Book]22 GATE ACADEMY®
Q.17 A stack organized computer has which of Q.21 A stack organised computer is
the following instructions? characterised by instructions with
(A) zero address (B) one address (A) Indirect addressing
(C) two address (D) three address (B) Direct addressing
Q.18 INCA (Increase register A by 1) is an
(C) Zero addressing
example of which of the following
addressing mode? (D) Index addressing
(A) Immediate addressing Q.22 Consider a 32-bit processor which supports
(B) Indirect addressing 70 instructions. Each instruction is 32 bit
(C) Implied addressing long and has 4 fields namely opcode, two
(D) Relative addressing register identifiers and an immediate
operand of unsigned integer type.
Q.19 A computer uses a memory unit of 512 K
Maximum value of the immediate operand
words of 32 bits each. A binary instruction
that can be supported by the processor is
code is stored in one word of the memory.
8191. How many registers the processor
The instruction has four parts : an
has?
addressing mode field to specify one of the
two-addressing mode (direct and direct), an (A) 32 (B) 64
operation code, a register code part to (C) 128 (D) 16
specify one of the 256 registers and an
Q.23 Statement associated with registers of a
address part. How many bits are there in
CPU are given. Identify the false statement
addressing mode part, opcode part, register
code part and the address part? (A) The program counter holds the
memory address of the instruction in
(A) 1, 3, 9, 19 (B) 1, 4, 9, 18
execution
(C) 1, 4, 8, 19 (D) 1, 8, 8, 20
Q.20 A computer which issues instructions in (B) Only opcode is transferred to the
order, has only 2 registers and 3 opcodes control unit
ADD, SUB and MOV. Consider 2 different (C) An instruction in the register consists
implementations of the following basic of the opcode and the operand
block : (D) The value of the counter is
Case 1 Case 2 incremented by 1 once its value has
t1 = a + b; t2 = c + d ; been read to the memory address
register
t2 = c + d ; t3 = e − t2 ;
Q.24 The immediate addressing mode can be
t3 = e − t 2 ; t1 = a + b;
used for
t4 = t1 − t2 ; t4 = t1 − t2 ; 1. Loading internal registers with initial
Assume that all operands are initially in values
memory. Final value of computation also 2. Perform arithmetic or logical
has to reside in memory. Which one is operations on data contained in
better in terms of memory accesses and by instructions. Which of the following
how many MOV instructions? is true?
(A) Case 2, 2
(A) Only 1
(B) Case 2, 3
(B) Only 2
(C) Case 1, 2
(D) Case 1, 3 (C) Both 1 and 2
(E) None of the above (D) Immediate mode refers to data in cache
GATE ACADEMY® 23 Machine Instruction, Instruction Cycle

Q.25 An instruction is stored at location 500 with Q.26 A byte addressable computer has a memory
it address field at location 501. The address capacity of 2m kB (k bytes) and can
field has the value 400. A processor register perform 2n operations. An instruction
R1 contains the number 200. Match the involving 3 operands and one operator
addressing mode (List-I) given below with needs maximum of :
effective address (List-II) for the given (A) 3m bits
instruction : (B) 3m + n bits
List-I List-II (C) m + n bits
(a) Direct (i) 200
(D) none of the above
(b) Register indirect (ii) 902
(c) Index with R1 (iii) 400
as the index
(d) Relative (iv) 600
Choose the correct option from those given
below :
(A) (a)-(iii), (b)-(i), (c)-(iv), d-(ii)
(B) (a)-(i), (b)-(ii), (c)-(iii), d-(iv)
(C) (a)-(iv), (b)-(ii), (c)-(iii), d-(i)
(D) (a)-(iv), (b)-(iii), (c)-(ii), d-(i)

Answer Keys

Classroom Practice Questions

1. C 2. 128 3. 6144 4. * 5. 507
6. 196608 7. 32 8. 14 9. D 10. 2
11. B 12. B 13. C 14. C 15. D
16. – 16 17. D 18. 16338 19. 16 20. 500
21. A 22. 50 23. D 24. A 25. C
26. C 27. A 28. D 29. B 30. D
31. B 32. A 33. C 34. B
Self - Practice Questions
1. A 2. D 3. C 4. A 5. B
6. C 7. D 8. D 9. D 10. C
11. C 12. C 13. B 14. A 15. A
16. A 17. A 18. C 19. C 20. E
21. C 22. B 23. A 24. C 25. A
26. D

Classroom Practice Questions

* 4 MAX 1-address = 7, MIN 1 - address = 1
MAX 0-address = 224, MIN 0 - address = 1

 4
Classroom Practice Questions
ALU, Data Path
& Control Unit
The minimum number of clock cycles
needed for execution cycle of this
Q.1 Consider the following sequence of micro-
instruction is :
operations
(A) 2 (B) 3
MBR  PC
(C) 4 (D) 5
MAR  X
Q.3 The instruction “call Rn, sub” is a two word
PC  Y
instruction. Assuming that PC is
Memory  MBR
incremented during the fetch cycle of the
Which one of the following is a possible first word of the instruction, its register
operation performed by this sequence? transfer interpretation is
(A) Instruction fetch Rn  PC  1;
(B) Operand fetch
PC  M [ PC ];
(C) Conditional branch
The minimum number of CPU clock cycles
(D) Initiation of interrupt service
needed during the execution cycle of this
[GATE 2013 : IIT Bombay] instruction is :
Common Data for Questions 2 & 3 (A) 2 (B) 3
Consider the following data path of a CPU (C) 4 (D) 5
Q.4 Consider the following data path of a
simple non-pipelined CPU. The registers
A, B, A1 , A2 , MDR, the bus and the ALU
are 8-bits wide. SP and MAR are 16-bits
registers. The MUX is of size 8  (2 :1) and
the DEMUX is of size 8  (1: 2). Each
The, ALU, the bus and all the registers in memory operation takes 2 CPU clock
the data path are of identical size. All cycles and uses MAR (Memory Address
operations including incrementation of the Register) and MDR (Memory Data
PC and the GPRs are to be carried out in the Register). SP can be decremented locally.
ALU. Two clock cycles are needed for
memory read operation-the first one for
loading address in the MAR and the next
one for loading data from the memory but
into the MDR.
Q.2 The instruction “add R0, R1” has the
The CPU instruction “push r”, where
register transfer interpretation
r  A or B, has the specification
R0  R0  R1.
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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GATE ACADEMY® 25 ALU, Data Path & Control Unit

M [SP]  r Q.7 An instruction set of a processor has 125

SP  SP 1 signals which can be divided into 5 groups
of mutually exclusive signals as follows:
How many CPU clock cycles are needed
to execute the “push r” instruction? Group 1 : 20 signals, Group 2 : 70 signals,
Group 3 : 2 signals, Group 4 : 10 signals,
(A) 2 (B) 3
Group 5 : 23 signals.
(C) 4 (D) 5
How many bits of the control words can be
[GATE 2001 : IIT Kanpur] saved by using vertical microprogramming
Q.5 A CPU has only three instructions I1, I2 and over horizontal microprogramming?
I3, which use the following signals in time (A) 0 (B) 103
steps T1-T5: (C) 22 (D) 55
I1 : T1 : Ain, Bout, Cin [GATE 2005 : IIT Bombay]
T2 : PCout, Bin Q.8 Consider a CPU where all the instructions
T3 : Zout, Ain require 7 clock cycles to complete
T4 : Bin, Cout execution. There are 140 instructions in the
T5 : End instruction set. It is found that 125 control
signals are needed to be generated by the
I2 : T1 : Cin, Bout, Din
control unit. While designing the horizontal
T2 : Aout, Bin microprogrammed control unit, single
T3 : Zout, Ain address field format is used for branch
T4 : Bin, Cout control logic. What is the minimum size of
T5 : End the control word and control address
I3 : T1 : Din, Aout register?
(A)125, 7 (B) 125, 10
T2 : Ain, Bout
(C) 135, 7 (D) 135, 10
T3 : Zout, Ain
[GATE 2008 : IISc Bangalore]
T4 : Dout, Ain
Q.9 The microinstructions stored in the control
T5 : End memory of a processor have a width of 26
Which of the following logic functions will bits. Each microinstruction is divided into
generate the hardwired control for the three fields : a micro-operation field of 13
signal Ain ? bits, a next address field (X), and a MUX
(A) T1.I1 + T2.I3 + T4.I3 + T3 select field (Y). There are 8 status bits in the
(B) (T1 + T2 + T3).I3 + T1.I1 inputs of the MUX.
(C) (T1 + T2 ).I1 + (T2 + T4).I3 + T3
(D) (T1 + T2 ).I2 + (T1 + T3).I1 + T3
[GATE 2004 : IIT Delhi]
Q.6 Horizontal micro programming
(A) Does not require use of signal
decoders.
(B) Results in larger sized
How many bits are there in the X and Y
microinstructions than vertical
fields, and what is the size of the control
microprogramming
memory in number of words?
(C) Use one bit for each control signal. (A) 10, 3, 1024 (B) 8, 5, 256
(D) All of the above (C) 5, 8, 2048 (D) 0, 3, 512
[GATE 2002 : IISc Bangalore] [GATE 2004 : IIT Delhi]
Computer Organization & Architecture [Work Book]26 GATE ACADEMY®
Q.10 The data path shown in the figure computes Q.2 Consider the following data path diagram -
the number of 1s in the 32-bit input word
corresponding to an unsigned even integer
stored in the shift register. The
unsigned counter, initially zero, is
incremented if the most significant bit of
the shift register is Consider an instruction: R0  R1 + R2.
Shift The following steps are used to execute it
Register over the given data path. Assume that PC is
Increment
incremented approximately. The subscripts
Reset_counter k-bit r and w indicate read and write operations,
Counter Shift_left respectively.
1. R2r , TEMP1r , ALUadd , TEMP2w
Load output Output
2. R1r ,TEMP1w
The micro-program for the control is 3. PCr , MAR w , MEMr
shown in the table below with missing 4. TEMP2r , R0w
control words for micro-instructions I1,
I2, …... In. 5. MDR r ,1R w
Micro- Which one of the following is the correct
reset_counter shift_left load_output
instruction order of execution of the above steps?
BEGIN 1 0 0 (A) 3, 5, 1, 2, 4 (B) 3, 5, 2, 1, 4
I1 ? ? ? (C) 1, 2, 4, 3, 5 (D) 2, 1, 4, 5, 3
[GATE 2020 : IIT Delhi]
In ? ? ? Q.3 A hardwired CPU uses 10 control signals
S1 to S10, in various time steps T1 to T5, to
END 0 0 1
implement 4 instructions I1 to I4 as shown
The counter width (k), the number of below :
missing micro-instructions (n), and the
T1 T2 T3 T4 T5
control word for microinstructions
I1 S1, S3, S2, S1, S10 S3,
I2, …... In are, respectively,
S5 S4, S7 S8
(A) 32, 5, 010 (B) 5, 32, 010
S6
(C) 5, 31, 011 (D) 5, 31, 010
I2 S1, S3, S8, S5, S6 S10
[GATE 2006 : IIT Kharagpur]
S5 S9, S6,
Self - Practice Questions S10 S7
Q.1 A micro instruction is to be designed to I3 S1, S3, S7, S2, S10 S1,
specify S5 S8, S6, S3
(a) None or one of the three micro S10 S9
operations of one kind and I4 S1, S3, S2, S5, S6, S10
(b) None or up to six micro operations of S5 S6, S7 S10 S9
another kind Which of the following pairs of expressions
The minimum number of bits in the micro- represent the circuit for generating control
instruction is signals S5 and S10 respectively?
(A) 9 (B) 5 {(Ij + Ik) Tn indicates that the control signal
(C) 8 (D) None of the above should be generated in time step Tn if the
[GATE 1997 : IIT Madras] instruction being executed is Ij or Ik}
GATE ACADEMY® 27 ALU, Data Path & Control Unit

(A) S5 = T1+I2.T3 and (D) Programming the control steps of a

S10 = (I1+I3).T4+(I2+I4).T5 computer
(B) S5 = T1+(I2+I4).T3 and Q.6 Consider the following statements :
S10 = (I1+I3).T4+(I2+I4).T5 Arithmetic Logic Unit (ALU)
(C) S5 = T1+(I2+I4).T3 and S10 = 1. Performs arithmetic operations
(I2+I3+I4).T2+(I1+I3).T4+(I2+I4).T5 2. Performs comparisons
(D) S5 = T1+(I2+I4).T3 and S10 = 3. Communicates with I/O devices
(I2+I3).T2+I4.T3+(I1+I3).T4+(I2+I4)
4. Keeps watch on the system
.T5
Which of these statements are correct?
[GATE 2005 : IIT Bombay]
(A) 1 only (B) 1 and 2 only
Q.4 Arrange the following configurations for
CPU in decreasing order of operating (C) 1 and 4 (D) 2 and 3
speeds : Q.7 A microinstruction format has
Hardwired control, vertical micro- microoperation field which is divided into
programming, horizontal micro- 2 subfields F1 and F2 . Each having 15
programming distinct micro operations condition field
(A) Hardwired control, vertical micro- CD for four status bits. Branch field BR
programming, horizontal micro- having four options used in conjunction
programming with address field AD. The address space is
(B) Hardwired control, horizontal micro- of 128 memory words. The size of micro
programming, vertical micro- instruction is
programming (A) 19 (B) 18
(C) Horizontal micro-programming, (C) 17 (D) 20
vertical micro-programming, Q.8 Micro program is :
hardwired control
(A) the name of a source program in micro
(D) Vertical micro-programming, computers
horizontal micro-programming,
(B) set of microinstructions that defines
hardwired control
the individual operations in response
[GATE 1999 : IIT Bombay]
to a machine-language instruction
Q.5 Micro programming is a technique for
(C) a primitive form of macros used in
(A) Writing small programs effectively assembly language programming
(B) Programming output/input routines
(D) a very small segment of machine code
(C) Programming the microprocessors

Answer Keys

Classroom Practice Questions

1. D 2. B 3. D 4. D 5. A
6. D 7. B 8. D 9. A 10. D
Self - Practice Questions
1. C 2. B 3. D 4. B 5. D
6. B 7. A 8. B


 5
Classroom Practice Questions
Instruction Pipeline
20% floating point operations, which of the
following ordering reflects the relative
Q.1 Consider two processors P1 and P2
performances of three designs?
executing the same instruction set. Assume ( Di  D j denotes that Di is faster than D j )
that under identical conditions, for the same
(A) D1  D  D2 (B) D2  D  D1
input, a program running on P2 takes 25%
less time but incurs 20% more CPI (clock (C) D  D2  D1 (D) D  D1  D2
cycles per instruction) as compared to the [GATE 2007 : IIT Kanpur]
program running on P1 . If the clock Q.4 Suppose the functions F and G can be
computed in 5 and 3 nanoseconds by
frequency of P1 is 1GHz, then the clock
functional units U F and U G , respectively.
frequency of P2 (in GHz) is _____.
Given two instances of U F and two
[GATE 2014 : IIT Kharagpur]
instances of U G , it is required to implement
Q.2 In an enhancement of a design of a CPU,
the speed of a floating-point unit has been the computation F (G( X i )) for 1  i  10.
increased by 20% and the speed of a fixed- Ignoring all other delays, the minimum
point unit has been increased by 10%. What time required to complete this computation
is the overall speedup achieved if the ratio is ____________ nanoseconds.
of the number of floating-point operations [GATE 2016 : IISc Bangalore]
to the number of fixed-point operations is Q.5 Consider a non-pipelined processor with a
2:3 and the floating-point operation used to clock rate of 2.5 gigahertz and average
take twice the time taken by the fixed-point cycles per instruction of four. The same
operation in the original design? processor is upgraded to a pipelined
(A) 1.155 (B) 1.185 processor with five stages; but due to the
(C) 1.255 (D) 1.285 internal pipelined delay, the clock speed is
[GATE 2004 : IIT Delhi] reduced to 2 gigahertz. Assume that there
Q.3 The floating-point unit of a processor using are no stalls in the pipeline. The speedup
a design D takes 2t cycles compared to t achieved in this pipelined processor is
cycles taken by the fixed-point unit. There ________. [GATE 2015 : IIT Kanpur]
are two more design suggestions D1 and Q.6 The stage delays in a 4-stage pipeline are
800, 500, 400 and 300 picoseconds. The
D2 . D1 uses 30% more cycles for fixed
first stage (with delay 800 picoseconds) is
point unit but 30% less cycles for floating replaced with a functionally equivalent
point unit as compared to design D. D2 uses design involving two stages with respective
40% less cycles for fixed point unit but 10% delays 600 and 350 picoseconds. The
more cycles for floating point unit as throughput increase of the pipeline is
compared to design D. For a given program _______ percent.
which has 80% fixed point operations and [GATE 2016 : IISc Bangalore]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
https://www.gateacademy.shop/ Live class room: https://play.google.com/store/apps/details?id=com.gateacademy1 http://onlinetestseries.gateacademy.co.in
GATE ACADEMY® 29 Instruction Pipeline

Q.7 Consider a 3 GHz (gigahertz) processor Q.10 Consider a 4-stage pipeline processor. The
with a three-stage pipeline and stage number of cycles needed by the four
latencies 1 , 2 , and 3 such that instructions I1 , I 2 , I3 , I 4 in stages
1  32 /4  23 . If the longest pipeline S1 , S2 , S3 , S4 is shown below.
stage is split into two pipeline stages of S1 S2 S3 S4
equal latency, the new frequency is
I1 2 1 1 1
__________ GHz, ignoring delays in the
pipeline registers. I2 1 3 2 2
[GATE 2016 : IISc Bangalore] I3 2 1 1 3
Q.8 The instruction pipeline of a RISC I4 1 2 2 2
processor has the following stages:
What is the number of cycles needed to
Instruction Fetch (IF), Instruction Decode
execute the following loop?
(ID), Operand Fetch (OF), Perform
For (i = 1 to 2){(I1; I2; I3; I4)}
Operation (PO) and Writeback (WB), The
(A) 16 (B) 23
IF, ID, OF and WB stages take 1 clock
(C) 28 (D) 30
cycle each for every instruction. Consider a
[GATE 2009 : IIT Roorkee]
sequence of 100 instructions. In the PO
Q.11 Consider a pipeline processor with 4 stages
stage, 40 instructions take 3 clock cycles
S1 to S4. We want to execute the following
each, 35 instructions take 2 clock cycles
loop:
each, and the remaining 25 instructions take
for (i = 1; i < = 1000; i++)
1 clock cycle each. Assume that there are
{I1, I2, I3, I4}
no data hazards and no control hazards.
where the time taken (in ns) by instructions
The number of clock cycles required for
I1 to I4 for stages S1 to S4 are given below::
completion of execution of the sequence of
S1 S 2 S3 S 4
instruction is ______ .
[GATE 2018 : IIT Guwahati] I1 1 2 1 2
Q.9 Consider an instruction pipeline with four I2 2 1 2 1
stages (S1, S2, S3 and S4) each with I3 1 1 2 1
combinational circuit only. The pipeline
I4 2 1 2 1
registers are required between each stage
and at the end of the last stage. Delays for The output of I1 for i=2 will be available
the stages and for the pipeline registers are after
as given in the figure. (A) 11 ns (B) 12 ns
(C) 13 ns (D) 28 ns
Pipeline Register (Delay 1ns)

Pipeline Register (Delay 1ns)

Pipeline Register (Delay 1ns)

Pipeline Register (Delay 1ns)

[GATE 2004 : IIT Delhi]

Stage Stage Stage Stage
S1 S2 S3 S4 Q.12 A 4-stage pipeline has the stage delays as
Delay Delay Delay Delay
5ns 6ns 11ns 8ns 150, 120, 160 and 140 nanoseconds
respectively. Registers that are used
between the stages have a delay and 5
What is the approximate speedup of the nanoseconds each. Assuming constant
pipeline in steady state under ideal clocking rate, the total time taken to process
conditions when compared to the 1000 data items on this pipeline will be
corresponding non-pipeline (A) 120.4 microseconds
implementation?
(B) 160.5 microseconds
(A) 4.0 (B) 2.5 (C) 165.5 microseconds
(C) 1.1 (D) 3.0 (D) 590.0 microseconds
[GATE 2011 : IIT Madras] [GATE 2004 : IIT Delhi]
Computer Organization & Architecture [Work Book]30 GATE ACADEMY®
Q.13 A non-pipelined single cycle processor Q.16 Instruction execution in a processor is
operating at 100 MHz is converted into a divided into 5 stages. Instruction Fetch (IF),
synchronous pipelined processor with five Instruction Decode (ID), Operand Fetch
stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, (OF), Execute (EX), and Write Back (WB).
1.5 nsec and 2.5 nsec, respectively. The These stages take 5, 4, 20, 10, and 3
delay of the latches is 0.5 nsec. The speedup nanoseconds (ns) respectively. A pipelined
of the pipeline processor for a large number implementation of the processor requires
of instructions is buffering between each pair of consecutive
(A) 4.5 (B) 4.0 stages with a delay of 2 ns. Two pipelined
implementation of the processor are
(C) 3.33 (D) 3.0
contemplated :
[GATE 2008 : IISc Bangalore] (i) A naive pipeline implementation (NP)
Q.14 We have two designs D1 and D2 for a with 5 stages and
synchronous pipeline processor. D1 has 5 (ii) An efficient pipeline (EP) where the
pipeline stages with execution times of 3 OF stage is divided into stages OF1
nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while and OF2 with execution times of 12 ns
the design D2 has 8 pipeline stages each and 8 ns respectively.
with 2 nsec execution time How much time The speedup (correct to two decimal
can be saved using design D2 over design places) achieved by EP over NP in
D1 for executing 100 instructions? executing 20 independent instructions with
(A) 214 nsec (B) 202 nsec no hazards is _________.
(C) 86 nsec (D) 200 nsec [GATE 2017 : IIT Roorkee]
[GATE 2005 : IIT Bombay] Q.17 A 5-stage pipelined processor has
Instruction Fetch (IF), Instruction Decode
Q.15 A 5 stage pipelined CPU has the following
(ID), Operand Fetch (OF), perform
sequence of stages IF-Instruction fetch
Operation (PO) and write Operand (WO)
from instruction memory, RD-Instruction
stages. The IF, ID, OF and WO stages take
decode and register read, EX-Execute:
1 clock cycle each for any instruction. The
ALU operation for data and address
PO stage takes 1 clock cycle for ADD and
computation, MA-Data memory access for
SUB instructions, 3 clock cycles for MUL
write access the register read at RD stage it
instruction, and 6 clock cycles for DIV
used. WB-Register write back.
instruction respectively. Operand
Consider the following sequence of forwarding is used in the pipeline. What is
instructions: the number of clock cycles needed to
I1 : L R0, Loc1; R0   M [ Loc1] execute the following sequence of
instructions?
I 2 : A R0, R0; R0   R0  R0
Instruction Meaning of instruction
I3 : S R2, R0; R2   R2  R0
I 0 : MUL R2 , R0 , R1 R2  R0 * R1
Let each stage take one clock cycle.
I1 : DIV R5 , R3 , R4 R5  R3 /R4
What is the number of clock cycles taken to
complete the above sequence of I 2 : ADD R2 , R5 , R2 R2  R5  R2
instructions starting from the fetch of I1 ? I3 : SUB R5 , R2 , R6 R5  R2  R6
(A) 8 (B) 10
(A) 13 (B) 15
(C) 12 (D) 15 (C) 17 (D) 19
[GATE 2005 : IIT Bombay] [GATE 2010 : IIT Guwahati]
GATE ACADEMY® 31 Instruction Pipeline

Q.18 Consider a pipelined processor with 5 (A) 132 (B) 165

stages, Instruction Fetch (IF), Instruction (C) 176 (D) 328
Decode (ID). Execute (EX), Memory
[GATE 2013 : IIT Bombay]
Access (MEM), and Write Back (WB).
Q.20 A CPU has a five-stage pipeline and runs at
Each stage of the pipeline, except the EX-
1 GHz frequency. Instruction fetch happens
stage, takes one cycle. Assume that the ID
in the first stage of the pipeline. A
stage merely decodes the instruction and
conditional branch instruction computes the
the register read is performed in the EX-
target address and evaluates the condition
stage. The EX-stage takes one cycle for
in the third stage of the pipeline. The
ADD instruction and two cycles for MUL
processor stops fetching new instructions
instruction. Ignore pipeline register
following a conditional branch until the
latencies. Consider the following sequence
branch outcome is known. A program
of 8 instructions:
executes 109 instructions out of which 20%
ADD, MUL, ADD, MUL, ADD, MUL,
are conditional branches. If each instruction
ADD, MUL
takes one cycle to complete on average, the
Assume that every MUL instruction is data- total execution time of the program is:
dependent on the ADD instruction just
(A) 1.0 second (B) 1.2 seconds
before it and every ADD instruction (except
the first ADD) is data-dependent on the (C) 1.4 seconds (D) 1.6 seconds
MUL instruction just before it. The [GATE 2006 : IIT Kharagpur]
Speedup is defined as follows: Q.21 Which of the following are NOT true in a
Speed up = pipelined processor?
ET without operand forwarding 1. Bypassing can handle all RAW
ET with operand forwarding hazards.
The Speedup achieved in executing the 2. Register renaming can eliminate all
given instruction sequence 011 the register carried WAR hazards.
pipelined processor (rounded to 2 decimal 3. Control hazard penalties can be
places) is_____. eliminated by dynamic branch
[GATE 2021 : IIT Bombay] prediction.
Q.19 Consider an instruction pipeline with five (A) 1 and 2 only (B) 1 and 3 only
stages without any branch prediction: Fetch (C) 2 and 3 only (D) 1, 2 and 3
Instruction (FI), Decode Instruction (DI), [GATE 2008 : IISc Bangalore]
Fetch Operand (FO), Execute Instruction Q.22 For a pipelined CPU with a single ALU,
(EI) and Write Operand (WO). The stage consider the following situations
delays for FI, DI, FO, EI and WO are 5 ns,
1. The j  1 instruction uses the result of
7ns, 10 ns, 8 ns and 6 ns, respectively.
the j  th instruction as an operand
There are intermediate storage buffers after
each stage and the delay of each buffer is 1 2. The execution of a conditional jump
ns. A program consisting of 12 instructions instruction
I1 , I 2 , I3 , ....., I12 is executed in this 3. The j  th and j  1 instructions
pipelined processor. Instruction I 4 is the require the ALU at the same time
only branch instruction and its branch target Which of the above can cause a hazard?
is I 9 . If the branch is taken during the (A) 1 and 2 only (B) 2 and 3 only
execution of this program, the time (in ns) (C) 3 only (D) All of above
needed to complete the program is [GATE 2003 : IIT Madras]
Computer Organization & Architecture [Work Book]32 GATE ACADEMY®

Common Data Question 23 & 24 I1 : ADD R1, R2, R3

I2 : MUL R7, R1, R3
A pipelined processor uses a 4-stage instruction
pipeline with the following stages: Instruction fetch I3 : SUB R4, R1, R5
(IF), Instruction decode (ID), Execute (EX) and I4 : ADD R3, R2, R4
Writeback (WB). The arithmetic operations as well I5 : MUL R7, R8, R9
as the load and store operations are carried out in Consider the following three statements:
the EX stage. The sequence of instructions
S1: There is an anti-dependence between
corresponding to the statement
instructions I2 and I5.
X   S – R *  P  Q   T is given below. The
S2: There is an anti-dependence between
values of variables P, Q, R, S and T are available in instructions I2 and I4.
the registers R0, R1, R2, R3 and R4 respectively,
S3: Within an instruction pipeline an anti-
before the execution of the instruction sequence.
dependence always creates one or more
ADD R5, R0, R1; R5 ← R0 + R1
stalls.
MUL R6, R2, R5; R6 ← R2 * R5
Which one of above statements is/are
SUB R5, R3, R6; R5 ← R3 – R6 correct?
DIV R6, R5, R4; R6 ← R5/R4
(A) Only S1 is true
STORE R6, X; X ← R6
(B) Only S2 is true
Q.23 The number of Read-After-Write (RAW)
(C) Only S1 and S2 are true
dependencies, Write-After-Read (WAR)
dependencies, and Write-After-Write (D) Only S2 and S3 are true
(WAW) dependencies in the sequence of [GATE 2015 : IIT Kanpur]
instructions are, respectively Q.26 Consider a 6-stage instruction pipeline,
(A) 2, 2, 4 (B) 3, 2, 3 where all stages are perfectly balanced.
(C) 4, 2, 2 (D) 3, 3, 2 Assume that there is no cycle-time
[GATE 2006 : IIT Kharagpur] overhead of pipelining. When an
Q.24 The IF, ID and WB stages take 1 clock application is executing on this 6-stage
cycle each. The EX stage takes 1 clock pipeline, the speedup achieved with respect
cycle each for the ADD, SUB and STORE to non-pipelined execution if 25% of the
operations, and 3 clock cycles each for instructions incur 2 pipeline stall cycles
MUL and DIV operations. Operand is__________.
forwarding from the EX stage to the ID [GATE 2014 : IIT Kharagpur]
stage is used. The number of clock cycles Q.27 Consider a non-pipelined processor
required to complete the sequence of operating at 2.5 GHz. It takes 5 clock cycles
instructions is to complete an instruction. You are going to
(A) 10 (B) 12 make a 5-stage pipeline out of this
(C) 14 (D) 16 processor. Overheads associated with
pipelining force you to operate the
[GATE 2006 : IIT Kharagpur]
pipelined processor at 2 GHz. In a given
Q.25 Consider the following code sequence
program, assume that 30% are memory
having five instructions I1 to I5. Each of
instructions, 60% are ALU instructions and
these instructions has the following format.
the rest are branch instructions. 5% of the
OP Ri, Rj, Rk memory instructions cause stalls of 50
where operation OP is performed on clock cycles each due to cache misses and
contents of registers Rj and Rk and the 50% of the branch instructions cause stalls
result is stored in register Ri. of 2 cycles each.
GATE ACADEMY® 33 Instruction Pipeline

Assume that there are no stalls associated (C) the first instruction in the taken path is
with the execution of ALU instructions. For executed.
this program, the speedup achieved by the (D) the branch takes longer to execute than
pipelined processor over the non-pipelined any other instruction.
processor (round off to 2 decimal places) is
[GATE 2008 : IISc Bangalore]
__________ .
Q.30 The following code is to run on a pipelined
[GATE 2020 : IIT Delhi]
processor with one branch delay slot:
Q.28 An instruction pipeline has five stages
I1: ADD R2←R7+R8
namely, instruction fetch (IF), instruction
decode and register fetch (ID/RF), I2 : SUB R4← R5-R6
instruction execution (EX), memory access I3 : ADD R1← R2+R3
(MEM), and register write back (WB) with I4 : STORE Memory [R4]←[R1]
stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and
BRANCH to Label if R1== 0
0.75 ns, respectively (ns stands for
nanoseconds). To gain in terms of Which of the instructions I1, I2, I3 or I4 can
frequency, the designers have decided to legitimately occupy the delay slot without
split the ID/RF stage into three stages (ID, any other program modification?
RF1, RF2) each of latency 2.2/3 ns. Also, (A) I1 (B) I2
the EX stage is spilt into two stages (EX1, (C) I3 (D) I4
EX2) each of latency 1 ns. The new design
[GATE 2008 : IISc Bangalore]
has a total of eight pipeline stages. A
program has 20% branch instructions Self - Practice Questions
which execute in the EX stage and produce Q.1 Comparing the time T1 taken for a single
the next instruction pointer at the end of the
instruction on a pipelined CPU, with time
EX stage in the old design and at the end of
T2 taken on a non-pipelined but identical
the EX2 stage in the new design. The IF
stage stalls after fetching a branch CPU, we can say that _____?
instruction until the next instruction pointer (A) T1  T2
is computed. All instructions other than the
(B) T1  T2
branch instruction have an average CPI of
one in both the designs. The execution (C) T1  T2
times of this program on the old and the
(D) T1 is T2 plus time taken for one
new design are P and Q nanoseconds,
instruction fetch cycle
respectively. The value of P/Q is_______.
[GATE 2014 : IIT Kharagpur] Q.2 Suppose the pipelined stages take {15, 8,
25, 4, 8} nanoseconds(ns) respectively.
Common Data Question 29 & 30 With a buffering delay of 5 ns. Two
Delayed branching can help in the handling of pipelined implementation of the processor
control hazards. are used? (i) A native pipeline
Q.29 For all delayed conditional branch implementation (NP) and (ii) An efficient
instructions, irrespective of whether the pipeline (EP) where the third stage is split
condition evaluates to true or false, into {12ns, 5ns and 8 ns} respectively. The
speedup achieved by EP over NP in
(A) the instruction following the
executing 100 independent instructions
conditional branch instruction in
with no hazards is :
memory is executed.
(A) 1.471 (B) 1.517
(B) the first instruction in the fall through
path is executed. (C) 1.638 (D) 1.567
Computer Organization & Architecture [Work Book]34 GATE ACADEMY®
Q.3 A pipeline is having speed up factor as 10 R0 , R1 and R2 contents of these registers
and operating with efficiency of 80%. What must not be modified.
will be the number of stages in the pipeline?
(A) 5 (B) 6
(A) 10 (B) 8
(C) 7 (D) 8
(C) 13 (D) None
Q.8 One instruction tries to write an operand
Q.4 Consider a non-pipelined machine with 6 before it is written by previous instruction.
stages the length of each stage are 20ns, 10 This may lead to a dependency called
ns, 30 ns, 25ns, 40ns, and 15 ns
(A) True dependency
respectively. Suppose for implementing the
pipelining the machine adds 5ns of (B) Anti dependency
overhead to each stage for clock skew and (C) Output dependency
set up. What is the speed up factor of the (D) Control hazard
pipelining system (ignoring any hazard
Q.9 A data driven machine is one that executes
impact)?
an instruction if the needed data is
(A) 7 (B) 14 available. The physical ordering of the code
(C) 3.11 (D) 6.22 listing does not dictate the course of
Q.5 We have 10 stage pipeline, where the execution. Consider the following pseudo-
branch target conditions are resolved at code :
stage 5. How many stalls are there for an A. Multiply E by 0.5 to get F
incorrect predicted branch? B. Add A and B to get E
(A) 5 (B) 6 C. Add B with 0.5 to get D
(C) 7 (D) 4
D. Add E and F to get G
Q.6 Consider a 5-segment pipeline with a clock
E. Add A with 10.5 to get C
cycle time 20 ns in each sub operation. Find
Assume A, B, C are already assigned
out the approximate speed-up ratio between
pipelined and non-pipelined system to values and the desired output is GG. Which
execute 100 instructions. (if an average, of the following sequence of execution is
every five cycles, a bubble due to data valid?
hazard has to be introduced in the pipeline) (A) B, C, D, A, E
(A) 5 (B) 4.03 (B) C, B, E, A, D
(C) 4.81 (D) 4.17 (C) A, B, C, D, E
Q.7 A non-pipeline CPU has 12 general purpose (D) E, D, C, B, A
registers ( R0 , R1 , R2 , R12 ). Following Q.10 A particular parallel program computation
operations are supported requires 100 sec when executed on a single
ADD Ra, Rb, Rr Add Ra to Rb and store the processor, if 40% of this computation is
result in Rr inherently sequential (i.e. will not benefit
from additional processors), then
MUL Ra, Rb, Rr Multiply Ra to Rb and
theoretically best possible elapsed times of
store the result in Rr
this program running with 2 and 4
MUL operations takes two clock cycles, processors, respectively, are :
ADD takes one clock cycle.
(A) 20 sec and 10 sec
Calculate the minimum number of clock
(B) 30 sec and 15 sec
cycles required to compute the value of the
expression XY  XYZ  YZ . The variables (C) 50 sec and 25 sec
X, Y, Z are initially available in registers (D) 70 sec and 55 sec
GATE ACADEMY® 35 Instruction Pipeline

Q.11 Which interrupt in 8085 Microprocessor is Q.15 A processor takes 12 cycles to complete an
un-maskable? instruction I. The corresponding pipelined
(A) RST 5.5 processor uses 6 stages with the execution
times of 3, 2, 5, 4, 6 and 2 cycles
(B) RST 7.5
respectively. What is the asymptotic
(C) TRAP speedup assuming that a very large number
(D) Both (a) and (b) of instructions are to be executed?
Q.12 The performance of a pipelined processor (A) 1.83 (B) 2
suffers if (C) 3 (D) 6
(A) The pipeline stages have different [GATE 2007 : IIT Kanpur]
delays Q.16 Register renaming is done in pipelined
(B) Consecutive instructions are processors
dependent on each other (A) As an alternative to register allocation
(C) The pipeline stages share dependent at compile time
hardware resources (B) For efficient access to function
(D) All of the above parameters and local variables
[GATE 2002 : IISc Bangalore] (C) To handle certain kinds of hazards

Q.13 A five-stage pipeline has stage delays of (D) As part of address translation
150, 120. 150, 160 and 140 nanoseconds. [GATE 2012 : IIT Delhi]
The registers that are used between the Q.17 Consider a pipelined processor with the
pipeline stages have a delay of 5 following four stages.
nanoseconds each. The total time to execute IF : Instruction Fetch
100 independent instructions on this
ID : Instruction Decode and Operand
pipeline, assuming there are no pipeline
Fetch
stalls, is ________ nanoseconds.
EX : Execute
[GATE 2021 : IIT Bombay]
WB : Write Back
Q.14 Consider the following processors (ns
The IF, ID and WB stages take one clock
stands for nanoseconds). Assume that the
cycle each to complete the operation. The
pipeline registers have zero latency.
number of clock cycles for the EX stage
P1 : Four-stage pipeline with stage latencies depends on the instruction. The ADD and
1 ns, 2 ns, 2 ns, 1 ns. SUB instructions need 1 clock cycle and the
P2 MUL instruction needs 3 clock cycles in the
: Four-stage pipeline with stage
EX stage. Operand forwarding is used in
latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
the pipelined processor.
P3 : Five-stage pipeline with stage latencies What is the number of clock cycles taken to
0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. complete the following sequence of
P4 : Five-stage pipeline with stage latencies instructions?
0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns. ADD R 2, R1, R0, R2  R1  R0
Which processor has the highest peak MUL R 4, R3, R 2, R4  R3* R2
clock frequency? SUB R6, R5, R 4, R6  R5  R4
(A) P1 (B) P2 (A) 7 (B) 8
(C) P3 (D) P4 (C) 10 (D) 14
[GATE 2014 : IIT Kharagpur] [GATE 2007 : IIT Kanpur]
Computer Organization & Architecture [Work Book]36 GATE ACADEMY®
Q.18 Consider the sequence of machine Q.19 Data forwarding techniques can be used to
instructions given below. speed up the operation in presence of data
MUL R5, R0, R1 dependencies. Consider the following
replacements of LHS with RHS.
DIV R6, R2, R3
ADD R7, R5, R6 (i) R1  Loc, Loc  R2
 R1  R2, R1  Loc
SUB R8, R7, R4
In the above sequence, R0 to R8 are general (ii) R1  Loc, Loc  R2  R1  R2
purpose registers. In the instruction shown, (iii) R1  Loc, R2  Loc  R1  Loc
the first register stores the result of the
(iv) R1  Loc, R2  Loc  R2  Loc
operation performed on the second and the
third registers. This sequence of In which of the following options, will the
instructions is to be executed in a pipelined result of executing the RHS be the same as
instruction processor with the following 4 executing the LHS irrespective of the
stages: instructions that follow?
(1) Instruction Fetch and Decode (IF), (A) i and iii (B) i and iv
(2) Operand Fetch (OF), (C) ii and iii (D) ii and iv
(3) Perform Operation (PO) and [GATE 2007 : IIT Kanpur]
(4) Write back the result (WB).
The IF, OF and WB stages take 1 clock
cycle each for any instruction. The PO stage
takes 1 clock cycle for ADD or SUB
instruction, 3 clock cycles for MUL
instruction and 5 clock cycles for DIV
instruction. The pipelined processor uses
operand forwarding from the PO stage to
the OF stage. The number of clock cycles
taken for the execution of the above
sequence of instructions is ________.
[GATE 2015 : IIT Kanpur]
Answer Keys

Classroom Practice Questions

1. 1.6 2. A 3. B 4. 28 5. 3.2
6. 33.33 7. 4 8. 219 9. B 10. D
11. C 12. C 13. C 14. B 15. A
16. 1.50 17. B 18. 1.87 19. B 20. C
21. B 22. D 23. C 24. B 25. B
26. 4 27. 2.16 28. 1.54 29. A 30. D
Self - Practice Questions
1. B 2. A 3. C 4. C 5. D
6. D 7. D 8. C 9. B 10. D
11. D 12. D 13. 17160 14. C 15. B
16. C 17. B 18. 13 19. B


 IO Interface
6
Classroom Practice Questions
(Interrupt & DMA Mode)
Q.4 The storage area of a disk has the innermost
diameter of 10 cm and outermost diameter
Q.1 A device with data transfer rate 10 KB/sec
of 20 cm . The maximum storage density of
is connected to a CPU. Data is transferred
byte wise. Let the interrupt overhead be the disk is 1400 bits/cm. The disk rotates at
4  sec . The byte transfer time between the a speed of 4200 RPM. The main memory of
a computer has 64-bit word length and 1 s
device interface register and CPU or
memory is negligible. What is the cycle time. If cycle stealing is used for data
minimum performance gain of operating transfer from the disk, the percentage of
the device under interrupt mode over memory cycles stolen for transferring one
operating it under program-controlled word is
mode? (A) 0.5 % (B) 1 %

(A) 15 (B) 25 (C) 5 % (D) 10 %

[GATE 2004 : IIT Delhi]
(C) 35 (D) 45
Q.5 A hard disk with a transfer rate of 10 MB/s
[GATE 2005 : IIT Bombay] is constantly transferring data to memory
Q.2 The size of the data count register of a using DMA. The processor runs at 600
DMA controller is 16 bits. The processor MHz, and takes 300 and 900 clock cycles
needs to transfer a file of 29, 154 kilobytes to initiate and complete DMA transfer
from disk to main memory. The memory is respectively. If the size of the transfer is 20
byte addressable. The minimum number of Kbytes, what is the percentage of processor
times the DMA controller needs to get the time consumed for the transfer operation?
control of the system bus from the (A) 5.0 % (B) 1.0 %
processor to transfer the file from the disk (C) 0.5 % (D) 0.1 %
to main memory is ____.
[GATE 2004 : IIT Delhi]
[GATE 2016 : IISc Bangalore] Q.6 Consider a disk drive with the following
Q.3 Consider a computer system with DMA specifications:
support. The DMA module is transferring 16 surfaces, 512 tracks/surface, 512
one 8-bit character in one CPU cycle from sectors/track, 1 KB/sector, rotation speed
a device to memory through cycle stealing 3000 rpm. The disk is operated in cycle
at regular intervals. Consider a 2 MHz stealing mode whereby whenever one 4
processor. If 0.5% processor cycles are byte word is ready it is sent to memory;
used for DMA, the data transfer rate of the similarly, for writing, the disk interface
device is __________ bits per second. reads a 4 byte word from the memory in
each DMA cycle. Memory cycle time is 40
[GATE 2021 : IIT Bombay]
nsec.
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Computer Organization & Architecture [Work Book]38 GATE ACADEMY®
The maximum percentage of time that the Q.8 Which of the following DMA transfer
CPU gets blocked during DMA operation modes and interrupt handling mechanisms
is: will enable the highest I/O band-width?
(A) 10 (B) 25 (A) Transparent DMA and Polling
interrupts
(C) 40 (D) 50
(B) Cycle- stealing and Vectored
[GATE 2005 : IIT Bombay] interrupts
Q.7 On a non-pipelined sequential processor, a (C) Block transfer and Vectored interrupts
program segment, which is a part of the
(D) Block transfer and polling interrupts
interrupt service routine, is given to transfer
500 bytes from an I/O device to memory. [GATE 2006 : IIT Kharagpur]

Initialize the address register Self - Practice Questions

Q.1 Normally user programs are prevented
Initialize the count to 500
from handling I/O directly by I/O
LOOP: instructions in them. For CPUs having
Load a byte from device explicit I/O instructions, such I/O
protection is ensured by having the I/O
Store in memory at address
instruction privileged. In a CPU with
given by address register memory mapped I/O, there is no explicit
Increment the address register I/O instruction. Which one of the following
is true for a CPU with memory mapped
Decrement the count I/O?
If count !  0 go to LOOP (A) I/O protection is ensured by operating
Assume that each statement in this program system routine(s).
is equivalent to machine instruction which (B) I/O protection is ensured by a
takes one clock cycle to execute if it is a hardware trap.
non-load/store instruction. The load-store (C) I/O protection is ensured during
instructions take two clock cycles to system configuration.
execute.
(D) I/O protection is not possible
The designer of the system also has an [GATE 2005 : IIT Bombay]
alternate approach of using DMA controller
Q.2 The correct matching for the following
to implement the same transfer. The DMA
pairs is:
controller requires 20 clock cycles for
initialization and other overheads. Each (a) DMA I/O (1) High speed RAM
DMA transfer cycle takes two clock cycles (b) Cache (2) Disk
to transfer one byte of data from the device (c) Interrupt I/O (3) Printer
to the memory.
(d) Condition (4) ALU
What is the approximate speedup when the
Code Register
DMA controller based design is used in
place of the interrupt driven program based (A) A  4, B  3, C  1, D  2
input-output? (B) A  2, B  1, C  3, D  4
(A) 3.4 (B) 4.4 (C) A  4, B  3, C  2, D  1
(C) 5.1 (D) 6.7 (D) A  2, B  3, C  4, D  1
[GATE 2011 : IIT Madras] [GATE 1997 : IIT Madras]
GATE ACADEMY® 39 IO Interface (Interrupt & DMA Mode)

Q.3 Consider the following statements. Q.6 Which of the following is false?
I. Daisy chaining is used to assign (A) Interrupts which are initially by an
priorities in attending interrupts. instruction are software interrupts
II. When a device raises a vectored (B) When a subordinate is called, the
interrupt, the CPU does polling to address of the instruction following the
identify the source of interrupt. CALL instruction is stored in the stack
III. In polling, the CPU periodically pointer
checks the status bits to know if any (C) A micro program which is written as
device needs its attention. 0’s and 1’s is a binary micro program
IV. During DMA, both the CPU and DMA (D) None of the above
controller can be bus masters at the Q.7 During DMA transfer, DMA controller
same time. transfers data _____
Which of the above statements are TRUE? (A) Directly from CPU to memory
(A) I and II only (B) I and II only (B) Directly from memory to CPU
(C) III only (D) I and III only (C) Directly between memory and
[GATE 2020 : IIT Delhi] registers

Q.4 Match the items in List-I and List-II : (D) Directly between the I/O module and
main memory
List - I
Q.8 Consider the disk which has average seek
(a) Interrupt which can be delayed when a
time of 32 ns and rotational rate of 360 rpm
much highest
(round per minute), each track of the disk
(b) Unplanned interrupts which occur has 512 sectors, each of size 512 bytes.
while executing
What is the time taken to read four
(c) Source of interrupt is in phase with the continuous sectors? And what is the data
system clock transfer rate?
List - II (A) 0.0443s and 936 kbps
(i) Normal priority interrupt has occurred (B) 0.0843s and 1536 kbps
(ii) Synchronous a program (C) 0.1043s and 1736 kbps
(iii) Maskable (D) 0.0943s and 1636 kbps
(iv) Exception Q.9 The term cycle stealing is used in context
(A) (a)-(ii), b-(i), c-(iv) of:

(B) (a)-(ii), b-(iv), c-(iii) (A) Interrupt bases data transfer

(B) Polling mode data transfer
(C) (a)-(iii), b-(i), c-(ii)
(C) DMA based data transfer
(D) (a)-(iii), b-(iv), c-(ii)
(D) Clock cycle overriding
Q.5 What is the average access time for a Drum
rotating at 4000 revolutions per minute? Q.10 A magnetic disk has 100 cylinders, each
with 10 tracks of 10 sector. If each sector
(A) 2.5 milliseconds
contains 128 bytes, what is the maximum
(B) 5.0 milliseconds capacity of the disk in kilobytes?
(C) 7.5 milliseconds (A) 1,280,000 (B) 1280
(D) 4.0 milliseconds (C) 1250 (D) 128,000
Computer Organization & Architecture [Work Book]40 GATE ACADEMY®
Q.11 Of the following, which best characterizes
computers that use memory-mapped I/O?
(A) The computer provides special
instructions for manipulating I/O ports
(B) I/O ports are placed at addresses on the
bus and are accessed just like other
memory locations
(C) To perform I/O operations. It is
sufficient to place the data in an
address register and call channel to
perform the operation
(D) I/O can be performed only when
memory management hardware is
turned on

Answer Keys

Classroom Practice Questions

1. B 2. 456 3. 80000 4. C 5. D

6. B 7. A 8. C

Self - Practice Questions

1. D 2. B 3. D 4. D 5. C

6. D 7. D 8. C 9. C 10. C

11. B


 7
Classroom Practice Questions
Miscellaneous
Q.4 A device employing INTR line for device
interrupt puts the CALL instruction on the
Q.1 The main difference(s) between a CISC and
data bus while
a RISC processor is/are that a RISC
processor typically: (A) INTA is active
(A) has fewer instructions (B) HOLD is active

(B) has fewer addressing modes (C) READY is active

(D) None of these
(C) has more registers
[GATE 2002 : IISc Bangalore]
(D) is easier to implement using hardwired
Q.5 Which of the following must be true for the
control logic
RFE (Return from Exception) instruction
[GATE 1999 : IIT Bombay] on a general-purpose processor?
Q.2 The use of multiple register windows with I. It must be a trap instruction
overlap causes a reduction in the number of II. It must be a privileged instruction
memory accesses for
III. An exception cannot be allowed to
I. Function locals and parameters occur during execution of an RFE
II. Register saves and restores instruction
(A) I only (B) II only
III. Instruction fetches
(C) I and II only (D) I, II and III only
(A) I only
[GATE 2008 : IISc Bangalore]
(B) II only
Q.6 Which one of the following is true for a
(C) III only CPU having a single interrupt request
(D) I, II and III line and single interrupt grant line?
(A) Neither vectored interrupt nor multiple
[GATE 2008 : IISc Bangalore]
interrupting devices are possible
Q.3 A processor needs software interrupt to
(B) Vectored interrupts are not possible
(A) Test the interrupt system of the but multiple interrupting devices are
processor possible
(B) Implement co-routines (C) Vectored interrupts and multiple
interrupting devices are both possible
(C) Obtain system services which need
execution of privileged instructions (D) Vectored interrupt is possible but
multiple interrupting devices are not
(D) Return from subroutine possible
[GATE 2001 : IIT Kanpur] [GATE 2005 : IIT Bombay]
Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
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Computer Organization & Architecture [Work Book]42 GATE ACADEMY®
Q.7 A CPU generally handles an interrupt by performing the memory read/write
executing an interrupt service routine operations in the main memory unit
(A) As soon as an interrupt is raised is_____.
(B) By checking the interrupt register at [GATE 2018 : IIT Guwahati]
the end of fetch cycle
Q.11 The amount of ROM needed to implement
(C) By checking the interrupt register after a 4 bit multiplier is
finishing the execution of the current
instruction (A) 64 bits (B) 128 bits
(D) By checking the interrupt register at (C) 1 Kbits (D) 2 Kbits
fixed time intervals.
[GATE 2012 : IIT Delhi]
[GATE 2009 : IIT Roorkee]
Q.12 What is the minimum size of ROM required
Q.8 For the daisy chain scheme of connecting
to store the complete truth table of an
I/O devices, which of the following
statements is true? 8- bit  8- bit multiplier?

(A) It gives non-uniform priority to (A) 32 K×16 bits (B) 64 K×16 bits
various devices
(C) 16 K×32 bits (D) 64 K×32 bits
(B) It gives uniform priority to all devices
[GATE 2004 : IIT Delhi]
(C) It is only useful for connecting slow
devices to a processor device Q.13 Consider the following reservation table for
(D) It requires a separate interrupt pin on a pipeline having three stages S1 , S2 and
the processor for each device S3 .
[GATE 1996 : IISc Bangalore]
Time 
Q.9 A main memory unit with a capacity of 4
megabytes is built using 1M 1- bit DRAM 1 2 3 4 5
chips. Each DRAM chip has 1K rows of
S1 X X
cells with 1K cells in each row. The time
taken for a single refresh operation is 100 S2 X X
nanoseconds. The time required to perform
one refresh operation on all the cells in the S3 X
memory unit is
(A) 100 nanoseconds
(B) 100  210 nanoseconds The minimum average latency (MAL) is
_________.
(C) 100  220 nanoseconds
(D) 3200  220 nanoseconds [GATE 2015 : IIT Kanpur]
[GATE 2010 : IIT Guwahati] Q.14 Booth’s algorithm for integer
Q.10 A 32-bit wide main memory unit with a multiplication gives worst
capacity of 1GB is built using performance when the multiplier
256  M  4  bit DRAM chips. The pattern is
number of rows of memory cells in the (A) 101010………1010
DRAM chip is 214 . The time taken to (B) 100000………0001
perform one refresh operation is 50 (C) 111111………1111
nanoseconds. The refresh period is 2 (D) 011111 ………1110
milliseconds. The percentage (rounded to
[GATE 1996 : IISc Bangalore]
the closest integer) of the time available for
GATE ACADEMY® 43 Miscellaneous

Q.15 Booth's coding in 8 bits for the decimal Self - Practice Questions
number − 57 is:
Q.1 CMOS is a Computer Chip on the
(A) 0 – 100 + 1000 motherboard, which is :
(B) 0 – 100 + 100 – 1 (A) RAM
(C) 0 – 1 + 100 – 10 + 1
(B) ROM
(D) 00 – 10 + 100 – 1
(C) EPROM
[GATE 1999 : IIT Bombay]
(D) Auxiliary storage
Q.16 When multiplicand Y is multiplied by
multiplier X  xn1 xn2 , , x0 using bit-pair Q.2 Which of the following is/are not features
of RISC processor?
recoding in Booth’s algorithm, partial
products are generated according to the (i) Large number of addressing modes
following table. (ii) Uniform instruction set
Partial (A) (i) only
Row X i 1 Xi X i 1
Product (B) (ii) only
1 0 0 0 0
(C) Both (i) and (ii)
2 0 0 1 Y
(D) None of the options
3 0 1 0 Y
Q.3 The Reduced Instruction Set Computer
4 0 1 1 2Y (RISC) characteristics are :
5 1 0 0 ?
(a) Single cycle instruction execution
6 1 0 1 –Y
(b) Variable length instruction formats
7 1 1 0 –Y
(c) Instructions that manipulates operands
8 1 1 1 ?
in memory
The partial products for rows 5 and 8 are (d) Efficient instruction pipeline
(A) 2Y and Y Choose the correct characteristics from the
(B) –2Y and 2Y options given below :
(C) –2Y and 0 (A) (a) and (b) (B) (b) and (c)
(D) 0 and Y (C) (a) and (d) (D) (c) and (d)
[GATE 2006 : IIT Kharagpur]
Q.4 Which of the following affects the
Q.17 The two numbers given below are processing power assuming they do not
multiplied using the Booth’s algorithm, influence each other.
Multiplicand: 0101 1010 1110 1110 Data bus capability
Multiplier: 0111 0111 1011 1101 Addressing scheme
How many additions/subtractions are
Clock speed
required for the multiplication of the above
two numbers? (A) 3 only (B) 1 and 3 only
(A) 6 (C) 2 and 3 only (D) 1, 2 and 3
(B) 8 Q.5 How many 128×8 bit RAMs are required to
(C) 10 design 32K×32 bit RAM?
(D) 12 (A) 512 (B) 1024
[GATE 2008 : IISc Bangalore] (C) 128 (D) 32
Computer Organization & Architecture [Work Book]44 GATE ACADEMY®
Q.6 A dynamic RAM has a memory cycle time
of 64 nsec. It has to be refreshed 100 times
per msec and each refresh takes 100 nsec .
What percentage of the memory cycle time
is used for refreshing?
(A) 10 (B) 6.4
(C) 1 (D) 0.64
[GATE 2005 : IIT Bombay]

Answer Keys

Classroom Practice Questions

1. A,B,C,D 2. A 3. C 4. A 5. D

6. C 7. C 8. A 9. B 10. 59

11. D 12. B 13. 3 14. A 15. B

16. C 17. B

Self - Practice Questions

1. A 2. A 3. C 4. B 5. B

6. C

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