PrimeTime PX Recommended

Methodology for Power Analysis

Version 1-0, Dec 2013
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Contents
Introduction ............................................................................................................ 2
Power Analysis Flow in PrimeTime PX .................................................................. 2
Leakage Power Analysis for Threshold Voltage Groups .................................... 6
Averaged Power Analysis ...................................................................................... 7
Vector-Free Flow ................................................................................................ 7
VCD Flow for Averaged Power Analysis ............................................................ 9
SAIF Flow for Averaged Power Analysis .......................................................... 10
Time-Based Power Analysis ................................................................................ 11
Peak Power Analysis ........................................................................................ 12
Cycle Accurate Peak Power Analysis .............................................................. 13
Multivoltage Power Analysis ................................................................................ 15
Power Analysis of UPF Designs ....................................................................... 16
Power Analysis of Non-UPF Designs ............................................................... 20
References........................................................................................................... 21

iii
1
Introduction
Power management is one of the main design challenges for nanometer-scale
technologies. To maximize power savings, designers today are employing various
advanced power management techniques such as multivoltage designing, frequency
scaling, power gating and so on. Calculation of the power dissipation of the design is an
essential part of the design flow. Accurate power analysis is required not only at the
sign-off stage but also in the earlier stages in the design flow.

PrimeTime PX is the sign-off quality power analysis tool in the Synopsys Galaxy design
platform. PrimeTime PX provides capabilities to perform power analysis accurately in
both the averaged and time-based modes. Beginning with the A-2007.12 release version
of PrimeTime PX, the ultra-low-power designs employing advanced power management
techniques using IEEE 1801 (UPF) support power analysis

The purpose of this document is to describe the recommended methodology to perform

power analysis using the H-2013.06 release of PrimeTime PX. The subsequent sections
describe the recommended methodology for various power analysis flows. Additionally,
users can download the full reference methodology(RM) scripts from Solvnet.
[References doc.ref.1]

Power Analysis Flow in PrimeTime PX

The primary power analysis techniques in PrimeTime PX are averaged power analysis
and time-based power analysis. Depending on the type of switching activity information
available and the user selection, several sub-flows can be derived.

In addition to these standard flows, PrimeTime PX also supports the power analysis
requirements for the modern designs. Such special flows include multivoltage power
analysis, distributed power analysis, etc. Multivoltage power analysis flow is explained in
detail in the subsequent sections.

Figure-1 represents the steps to follow for a typical power analysis flow using PrimeTime
PX.

2
Figure 1: Power Analysis Flow in PrimeTime PX

Step 1: Set the power analysis variables such as power_enable_analysis and

power_analysis_mode. These variables are required to enable PrimeTime PX in
the primetime shell and to specify the power analysis mode- averaged or time-based
respectively as follows:

## ENABLE POWER ANALYSIS

set power_enable_analysis TRUE
set power_analysis_mode time_based

Step 2: Read in the design data, including the netlist, SDC constraints and parasitic as
shown in Example 1.

Example 1 Script Example for Reading Design Data

## SET LIBRARY PATHS
set search_path "../src/hdl/gate ../src/lib "
set link_library " * core_typ.db"
3
## READ NETLIST
read_verilog mac.vg
current_design mac
link

## READ SDC & SPEF

read_sdc ../src/hdl/gate/mac.sdc
read_parasitics ../src/annotate/mac.spef.gz

Step 3: Before, specifying the switching activity for power, perform timing analysis using
the update_timing command. This maximizes the performance by preventing any
additional timing updates triggered by the activity annotation commands.

## RUN TIMING ANALYSIS

update_timing

Step 4: Specify the switching activity to annotate activity information. The switching
activity can come from either a gate-level VCD file, RTL VCD file, SAIF file, or it can be
specified using the set_switching_activity, infer_switching_activity,
and the set_case_analysis commands. Starting with H-2013.06 release, use the
infer_switching_activity command on high-fanout pins such as preset and
clear.
If the switching activity is obtained from an RTL simulation, you need to provide a name-
mapping file to match the RTL activity file names to the corresponding gate-level objects.
The default name mapping performed in Design Compiler is correctly matched using the
built-in name-mapping capability in PrimeTime PX. However, for non-standard
permutations, you should generate a PrimeTime PX map-file in Design Compiler during
synthesis.
The E-2010.12 version of Design Compiler uses a new convention for naming registers
and hierarchical blocks synthesized from RTL generate statements with a
hdlin_enable_hier_naming variable set to true during synthesis. You should also
generate a correct PrimeTime PX map-file in Design Compiler regardless of whether
you have synthesized the netlist with hierarchical naming or not. The name-mapping file
consists of the set_rtl_to_gate_name command, and it must be sourced prior to
reading the activity file.
For more information, see “Name Mapping” on page 2-5 of PrimeTime PX User Guide.
[Referencesdoc.ref.2]

## READ SWITCHING ACTIVITY

source ptpx_map.tcl # for RTL activity only
read_vcd -strip_path tb/macinst ../sim/vcd.dump.gz

Note:

4
 For SystemVerilog, provide the activity in the form of VPD or FSDB activity from the
simulator. The conversion utilities fsdb2vcd and vpd2vcd retain the enumerated
SystemVerilog structures for correct matching of the RTL VCD names with those in
the gate-level netlist. Do not use SystemVerilog VCD files created directly from the
simulator.

Apply the –format systemverilog option of the read_vcd command regardless

of the naming convention. This option informs PrimeTime PX that the VCD file
contains $scope begin statements to denote hierarchy for generate and named
block statements. If you do not apply this option, PrimeTime PX ignores the
$scope begin statements in the VCD file and the tool does not annotate the VCD
signals .

After applying the switching activity, it is recommended that you verify that the switching
activity has been correctly annotated onto the design, with the
report_switching_activity command; especially when providing RTL activity
files.

## VERIFY ACTIVITY ANNOTATION

report_switching_activity –rtl –list_not_annotated

This command categorizes the nets in the design based on the cell type, so that you can
verify that all the primary inputs, sequential outputs, memories etc are annotated. When
providing RTL activity, you should apply the –rtl –list_not_annotated option to
report only the percentage of annotation and nets without annotation, for the synthesis
invariants. To debug the annotation issues, use the report_activity_file_check
command.

Step 5: Before performing power analysis, use the set_power_analysis_options

commandto allow theoptions such as waveform format, waveform output file, cell list for
power calculation etc.

## SET POWER ANALYSIS OPTIONS

set_power_analysis_options –waveform_output mac.fsdb

Use the check_power command to check for any possible power violations. This
command reports the cells that are missing power data in the library, and verifies that
the transition times and output loads are within the power table range.

5
## CHECK FOR POSSIBLE POWER VIOLATIONS
check_power

Step 6: Perform power analysis using the update_power command and generate the
reports using the report_power command.

## RUN POWER ANALYSIS

update_power

## GENERATE REPORTS
report_power

By default, PrimeTime PX uses the CCS power models. When both the CCS and NLPM
power models are available, the CCS power model has a higher priority for a cell. To
use the NLPM power models, specify the nlpm argument with the
power_model_preference variable.
PrimeTime PX requires a complete set of power information for a cell from a single
power model, and not a mix and match of power information from CCS and NLPM power
models.

Leakage Power Analysis for Threshold Voltage Groups

Beginning with the G-2012.06 release, PrimeTime PX can analyze and report leakage at
varying threshold voltage groups.

Use the -threshold_voltage_group option of the report_power command to

check the leakage powerfor each threshold voltage group, By default, PrimeTime PX
identifies the threshold voltage group to which cells belong, by threshold voltage
attributes. To set the attributes in the library, use the set_user_attribute command
as shown in the following example:

set_user_attribute [get_libs agl90g_od_svt_ss] default_threshold_voltage_group SVT

set_user_attribute [get_lib_cells -of_object[get_cells U25]] threshold_voltage_group SVT

## Check Leakage Per Low Threshold Voltage Groups

## For either default_threshold_voltage_group: “LVT”
## Or threshold_voltage_group: “LVT”
report_power –threshold_voltage_group –lvth_groups LVT

6
 PrimeTime PX also supports threshold group identification with the –
pattern_priority option which is compatible with the mechanism used by
PrimeTime ECO swapping capability.

For more information, see “Reporting Leakage Power Based on Threshold Voltage
Group” on page 8-7 of PrimeTime PX User Guide. [Referencesdoc.ref.2]

Averaged Power Analysis

The averaged power analysis in PrimeTime PX supports the analysis of the following
activities: default switching activity, user-defined switching activity, switching activity from
RTL or gate-level simulation in the form of VCD, FSDB VPD or SAIF. Use the –format
SystemVerilog option of the read_vcd command to provide SystemVerilog activity
files.

To perform the analysis, the tool first checks for annotation of switching activity, static
probability, and toggle rate on all the nodes. If they are not available, the tool assigns the
default toggle rate and static probability to the primary inputs and black box outputs. For
nonannotated nets, you can derive the switching activity by using random vectors in a
simulation cycle with zero-delays.

The primary flows in the averaged power analysis are:

 The vector-free flow with no switching activity; for quick and early analysis
 The VCD Flow with switching activity from RTL or gate-levl simulations
 The SAIF Flow with switching activity from SAIF file

Use the set_case_analysis command to annotate the primary inputs which do not
exist in the VCD file such as the test enable signals. This avoids the default toggle rate
from being applied.

Vector-Free Flow

Vector-free flow provides for quick power analysis data when there is no simulation data
available. In this flow, the tool processes the switching activity defined using the
set_switching_activity and set_case_analysis commands. If no switching
activity is defined, the tool assigns a default toggle rate and static probability on primary
inputs, tristates and black-box outputs, and propagates the activity with random vector
simulation.

PrimeTime PX uses a value of 0.1 for the default toggle rate and 0.5 for the default static
probability. The toggle rate is relative to the associated clock. For accurate results, it is
recommended to set the values for these parameters that are well suited for your design.
7
 The guidelines for annotating the switching activity are:

Purpose Command
 Annotate a suitable default toggle set power_default_toggle_rate 0.2
rate value, for example, 0.2 to all
the starting points. It is
recommended that you provide a
value which will produce
pessimistic power value when
compared with the gate-level VCD
results.

 Annotate the toggle rates based set_switching_activity –type registers

on the related clocks using the –toggle_rate <value> –clock_domains
-clock_domains option to the {all_clocks} -hierarchy
register outputs. You should do
this because propagation through
sequential elements can result in
loss of activity.

 Annotate clock-gating cells with a set_switching_activity –clock_domains

factor that is a multiple of the clk2 –clock_derate <value> –type
toggle rate of the related clock. clock_gating_cells -hierarchy
When the –clock_domains
option is specified, you can apply
either the -clock_derate or the
-toggle_rate option. This
guarantees that the clockgate
output is toggling at the expected
rate.

Example 2 Script Example for Vector Free Averaged Power Analysis Flow

## ENABLE POWER ANALYSIS

set power_enable_analysis TRUE
set power_analysis_mode averaged

## SET LIBRARY PATHS

set search_path "../src/hdl/gate ../src/lib ."
set link_library " * core_typ.db"

## READ NETLIST
read_verilog mac.vg
8
 current_design mac
link

## READ SDC & SPEF

read_sdc ../src/hdl/gate/mac.sdc
read_parasitics ../src/annotate/mac.spef.gz

## RUN TIMING ANALYSIS

update_timing

## SPECIFY SWITCHING ACTIVITY

set power_default_toggle_rate 0.2
set power_default_static_probability 0.3
## Infer and apply switching activity on preset and clear pins
infer_switching_activity -apply

report_switching_activity

## RUN POWER ANALYSIS

check_power
update_power

## GENERATE REPORTS
report_power
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

VCD Flow for Averaged Power Analysis

Using the VCD or SAIF from RTL or gate-level simulations can provide more accurate
power analysis results compared to the vector-free flow. Apply the VCD activity using
the read_vcd command.

Example 3 Script Example for VCD-Based Average Power Analysis Flow

## ENABLE POWER ANALYSIS

set power_enable_analysis TRUE
set power_analysis_mode averaged

## SET LIBRARY PATHS

set search_path "../src/hdl/gate ../src/lib ."
set link_library " * core_typ.db"

9
 ## READ NETLIST
read_verilog mac.vg
current_design mac
link

## READ SDC & SPEF

read_sdc ../src/hdl/gate/mac.sdc
read_parasitics ../src/annotate/mac.spef.gz

## RUN TIMING ANALYSIS

update_timing

## SPECIFY SWITCHING ACTIVITY

set_case_analysis 0 test_enable
read_vcd "../sim/vcd.dump.gz" -strip_path "tb/macinst"
report_switching_activity -list_not_annotated -rtl

## RUN POWER ANALYSIS

check_power
update_power

## GENERATE REPORTS
report_power
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

Ensure that you specify the strip_path to the top-level design instance correctly.
Otherwise, it results in less accurate power analysis due to an incomplete switching
activity being annotated. In Example 3, the VCD activity file vcd.dump.gz is applied to
the top instance macinst in a test bench tb.

SAIF Flow for Averaged Power Analysis

Prime Time PX also supports SAIF file format, a compact ASCII file that you can create
directly from HDL simulation or by using the vcd2saif UNIX utility that is shipped with
the tool. PrimeTime PX annotates the static probability and toggle rates directly from
SAIF.

Example 4 Script Example for SAIF-Based Averaged Power Analysis Flow

## ENABLE POWER ANALYSIS
set power_enable_analysis TRUE
set power_analysis_mode averaged
10
 ## SET LIBRARY PATHS
set search_path "../src/hdl/gate ../src/lib ."
set link_library " * core_typ.db"

## READ NETLIST
read_verilog mac.vg
current_design mac
link

## READ SDC & SPEF

read_sdc ../src/hdl/gate/mac.sdc
read_parasitics ../src/annotate/mac.spef.gz

## RUN TIMING ANALYSIS

update_timing

## SPECIFY SWITCHING ACTIVITY

read_saif "../sim/mac.saif" -strip_path "tb/macinst"
report_switching_activity -list_not_annotated

## RUN POWER ANALYSIS

check_power
update_power

## GENERATE REPORTS
report_power
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

Time-Based Power Analysis

Time-based power analysis is the most detailed and accurate analysis flow in PrimeTime
PX. This flow applies the VCD events directly to the design and generates a power
waveform over time. In this flow, PrimeTime PX also supports the SystemVerilog activity.
See Section 3.2.
To enable time-based power analysis mode, set the power_analysis_mode variable
to time_based.

In the traditional peak power analysis flow, Prime Time PX reads a gate-level VCD file,
calculates the energy per event, and generates detailed time-based power waveforms
which display the power based on the VCD resolution. This flow reports both the
averaged and peak power results.

11
 Another time-based analysis technique, is the cycle-accurate peak power analysis,
which allows you to use RTL or gate-level zero-delay VCD files to perform cycle-
accurate power analysis. In this flow, PrimeTime PX propagates the VCD events to
derive the switching activity on nonannotated nets, and generates a power waveform
displaying the power per clock cycle. This technique reports both the average power and
the peak cycle power.

Peak Power Analysis

All the options required for peak power analysis are set using the
set_power_analysis_options command.
For more information on the command options, see the command man page.

The update_power command performs power analysis and also generates the power
waveforms. The report_power command generates reports for both peak power and
averaged power analyses.

Example 5 Script Example for Peak Power Analysis with Gate-Level VCD
## ENABLE POWER ANALYSIS
set power_enable_analysis TRUE
set power_analysis_mode time_based

## SET LIBRARY PATHS

set search_path "../src/hdl/gate ../src/lib ."
set link_library " * core_typ.db"

## READ NETLIST
read_verilog mac.vg
current_design mac
link

## READ SDC & SPEF

read_sdc ../src/hdl/gate/mac.sdc
read_parasitics ../src/annotate/mac.spef.gz

## RUN TIMING ANALYSIS

update_timing

## SPECIFY SWITCHING ACTIVITY

read_vcd "../sim/vcd.dump.gz" -strip_path "tb/macinst”
report_switching_activity -list_not_annotated

## SET POWER ANALYSIS OPTIONS: WAVEFORM OUTPUT NAME & FORMAT

set_power_analysis_options -waveform_format fsdb \
-waveform_output wave
12
 ## RUN POWER ANALYSIS
check_power
update_power

## GENERATE REPORTS
report_power
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

In this flow, PrimeTime PX calculates the transition time and loads for every leaf pin, and
processes each event in the simulation activity file. The power waveform and peak
power is calculated by superpositioning the distributed power.

Note:
In this flow, propagation and name mapping are not performed. PrimeTime PX
assumes that the VCD is obtained from SDF based gate-level simulation, and that all
the nets are therefore annotated.

Cycle Accurate Peak Power Analysis

Cycle-accurate peak power analysis is enabled by using –rtl option of the read_vcd
command. The –rtl option causes PrimeTime PX to perform name mapping and
propagation of VCD events, per clock cycle. The default clock cycle is the fastest clock
defined with the create_clock command. It is recommended that you generate a
PrimeTime PX map-file when synthesizing RTL designs in Design Compiler.

Use the set_case_analysis command to annotate the primary inputs such as

test_enable signals which are not in the RTL VCD. In this flow, no default annotation is
assigned, so these signals will remain uninitialized unless you annotate their activity.
PrimeTime PX will propagate the case analysis during cycle-accurate analysis.
Example 6 Script Example for Cycle Accurate Peak Power Analysis
## ENABLE POWER ANALYSIS
set power_enable_analysis TRUE
set power_analysis_mode time_based

## SET LIBRARY PATHS

set search_path "../src/hdl/gate ../src/lib ."
set link_library " * core_typ.db"

13
## READ NETLIST
read_verilog mac.vg
current_design mac
link

## READ SDC & SPEF

read_sdc ../src/hdl/gate/mac.sdc
read_parasitics ../src/annotate/mac.spef.gz

## RUN TIMING ANALYSIS

update_timing

## Apply case analysis to primary inputs not in the VCD

set_case_analysis 0 test_enable

## READ NAME MAPPING FILE

source "../src/hdl/gate/mac_ptpxmap.tcl"

## SPECIFY SWITCHING ACTIVITY

read_vcd –rtl "../sim/rtl.vcd" -strip_path "tb/macinst”
report_switching_activity -list_not_annotated

## SET POWER ANALYSIS OPTIONS: WAVEFORM OUTPUT NAME & FORMAT

set_power_analysis_options -waveform_format fasb \
-waveform_output wave

## RUN POWER ANALYSIS

check_power
update_power

## GENERATE REPORTS
report_power
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

In this flow, PrimeTime PX calculates the transition time and loads for every leaf pin,
performs name-mapping to match RTL signals to gate-level objects, propagates the
VCD events and the case_analysis constants to calculate the energy per clock cycle.
The power waveform is obtained by distributing the energy per cycle over the clock
cycle. The maximum power per cycle is calculated by superpositioning the distributed
power.

14
Multivoltage Power Analysis
PrimeTime PX supports power analysis for designs employing advanced power
management techniques. The multivoltage power analysis can be performed both in the
IEEE 1801 (UPF) mode and in the non-UPF mode.

PrimeTime PX complies with the multivoltage library requirements of the other tools in
the Galaxy design platform. In the multivoltage library setup and multiple logic libraries,
either CCS or NLPM for multiple voltages correspond to a single physical view. Logic
libraries in power and ground (PG)-pin format provide the power pin hookup information.
If the logic libraries are not PG pin complaint, user needs to provide a Tcl sidefile
containing PG pin information. The tool uses the sidefile to update the logic libraries with
PG pins automatically. Note that power analysis in non-UPF mode does not require the
PG pin libraries.
For more information about library setup, see page 5.13 “ Library Support for
Multivoltage Analysis” of the PrimeTime and PrimeTime SI User Guide [Referencesdoc.
ref. 3].

15
Power Analysis of UPF Designs

PrimeTime PX supports UPF format. The tool can read and apply the power intent and
constraints mentioned in the UPF file. Use the load_upf command to read the UPF
into the tool. Alternately, you can read the individual UPF commands sequentially from
the command prompt.

The power domains, power nets, and the power net connections are created
automatically from the UPF commands. The tool allows hierarchical cells, macro cells
and iopads as elements to the power domains. The tool also understands the strategies
defined in the UPF for the special cells including the switch cells.

A power switch-cell is defined in UPF using the create_power_switch command.

PrimeTime PX uses this command to identify the switch control signal associated with
the power domain and the UPF compliant Boolean expression that defines the “on” state
of the power domain. Thus the logic state of switch control signal determines the power
on and off states of the power domain.

Beginning with the E-2010.12 release, PrimeTime is capable of supporting fine grain
switch cells. The fine-grain switch cells are termed so only when the cell is defined with
the cell-level switch_cell_type attribute with the value fine-grain. PrimeTime PX
derives the “on” and “off” states of a fine-grain switch cell from the library specification of
internal PG pin. Beginning with the F-2011.06 release, users can connect to internal PG
pins.

For more information about deriving the on and off states of a fine-grain switch cell,
please refer to “Support for Fine-Grained Switch cells for Power Analysis” in the
PrimeTime PX User Guide . [Referencesdoc. ref. 2].

During peak power analysis, when the switch control signal in the VCD file is in the off
state, the tool identifies this with the shutdown state of the power domain. Because there
is no power consumption during shutdown, the power analysis assigns zero power for
the cells inside the power domain. When the switch control signal returns to on state,
power analysis is performed as usual.

Beginning the D-2010.06 release, PrimeTime PX is capable of performing power

analysis for multiple power rails simultaneously. A single update_power command
analyzes all the rails in the design. Subsequently, the report_power command can be
used in either of the analysis modes, to report the average power per rail or for all the
rails

The tool also can perform multirail scaling for multi-rail cells. Note that this capability is
available for UPF as well as non-UPF designs in both time-based and averaged
analyses.

16
Example 7 Script Example for Peak Power Analysis in the UPF Mode

## ENABLE POWER ANALYSIS

set power_enable_analysis true
set power_analysis_mode time_based

#ENABLE CONCURRENT POWER ANALYSIS

set power_enable_multi_rail_analysis true

## SET LIBRARY PATHS

set search_path "../src/hdl/gate ../src/lib ."
set link_library “ typ_0.7.db \
ls_0709.db \
special_cells.db”

## READ NETLIST
read_verilog design.v
current_design design_top
link

## DEFINE SCALING GROUPS

define_scaling_lib_group -name grp1 {typ_0.7.db typ_0.9.db}
define_scaling_lib_group -name grp2 {ls_0709.db ls_0707.db \
ls_0907.db}
report_lib_groups -scaling -show {voltage temperature}

## LOAD UPF
load_upf design.upf

## SET VOLTAGE
set_voltage 0.7 –object_list {VDDG}
set_voltage 0.9 –object_list {VDDX}
set_voltage 0 –object_list {VSS}

## RUN TIMING ANALYSIS

update_timing

## SPECIFY SWITCHING ACTIVITY

read_vcd "../sim/vcd.dump.gz" -strip_path "tb/macinst”
report_switching_activity -list_not_annotated

## SET POWER ANALYSIS OPTIONS: WAVEFORM OUTPUT NAME & FORMAT

set_power_analysis_options -waveform_format fsdb \
-waveform_output wave

## RUN POWER ANALYSIS

check_power
update_power

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 ## GENERATE REPORTS
report_power
report_power –rails “VDDG VDDX”
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

For averaged power analysis, PrimeTime PX uses the switching activity information of
the switch control signal to scale the leakage and dynamic power values. You can derive
the switching activity information either from a SAIF file or define using the
set_switching_activity command.

Example 8 Script Example for Average Power Analysis in UPF Mode

## ENABLE POWER ANALYSIS
set power_enable_analysis true
set power_analysis_mode averaged

#ENABLE CONCURRENT POWER ANALYSIS

set power_enable_multi_rail_analysis true

## SET LIBRARY PATHS

set search_path "../src/hdl/gate ../src/lib ."
set link_library “ typ_0.7.db \
ls_0709.db \
special_cells.db”

## READ NETLIST
read_verilog design.v
current_design design_top
link

## DEFINE SCALING GROUPS

define_scaling_lib_group -name grp1 {typ_0.7.db typ_0.9.db}
define_scaling_lib_group -name grp2 {ls_0709.db ls_0707.db \
ls_0907.db}
report_lib_groups -scaling -show {voltage temperature}

## LOAD UPF
load_upf design.upf

## SET VOLTAGE
set_voltage 0.7 –object_list {VDDG}

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set_voltage 0.9 –object_list {VDDX}
set_voltage 0 –object_list {VSS}

## RUN TIMING ANALYSIS

update_timing

## SPECIFY SWITCHING ACTIVITY

read_saif "../sim/mac.saif" -strip_path "tb/macinst”
report_switching_activity -list_not_annotated

#alternatively, switch control activity can be defined using

#set_switching_activity -toggle_count 0.004 - static_probability
0.1 PwrCtrl/gprs_sd

## RUN POWER ANALYSIS

check_power
update_power

## GENERATE REPORTS
report_power
report_power –rails “VDDG VDDX”
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

By default, the report_power command reports power for all the power domains and
all the power nets in the design. PrimeTime PX provides additional reporting capabilities
to generate power reports for selected power domains and power nets.
For more information on reporting features in multivoltage flow, see chapter 6 of
PrimeTime PX User Guide. [Referencesdoc.ref.2]

Note:
In the averaged power analysis mode, PrimeTime PX by default, does not scale the
dynamic power based on the state of the power down control signal. The tool however,
scales leakage power based on the state of the control signal. For PrimeTime PX to
scale the dynamic power also, set the
power_scale_dynamic_power_at_power_off variable to true.

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 Power Analysis of Non-UPF Designs

The non-UPF power domain and rail mapping modes are not enabled by default in
PrimeTime PX. To invoke the non-UPF mode, set the
power_domains_compatibility variable to true.

In the non-UPF mode, the power intent specification is controlled by power domain and
power-net-info objects. The voltage specification is done by using the
set_operating_conditions command in rail mapping mode and the
set_voltage command in power domain mode.

Example 9 Script Example for for Average Power Analysis in nonUPF Mode
## ENABLE POWER ANALYSIS
set power_enable_analysis true
set power_analysis_mode averaged
set power_domains_compatibility true

## ENABLE CONCURRENT POWER ANALYSIS

set power_enable_multi_rail_analysis true

## SET LIBRARY PATHS

set search_path "../src/hdl/gate ../src/lib ."
set link_library “ typ_0.7.db \
ls_0709.db \
special_cells.db”
set link_path_per_instance \
[list [list {PD0_inst typ_0.9.db ls_0907.db}]]

## READ NETLIST
read_verilog design.v
current_design design_top
link

## CREATE POWER DOMAINS & POWER NET INFO OBJECTS

create_power_domain t
create_power_domain a -object_list[get_cells PD0_inst]\
-power_down -power_down_ctrl[get_nets a] \
-power_down_ctrl_sense 0

create_power_net_info t_vdd -power -switchable \

-nominal_voltages{1.2} -voltage_ranges{1.1 1.3}
create_power_net_info a_vdd -power
create_power_net_info t_vss –gnd
create_power_net_info a_vss -gnd

connect_power_domain t -primary_power_net t_vdd \

-primary_ground_net t_vss

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 connect_power_domain a -primary_power_net a_vdd \
-primary_ground_net a_vss \
-backup_power_net vdd_backup \
-backup_ground_net vss_backup

# SET VOLTAGE
set_voltage 1.15 -object_list{t_vdd a_vdd}

## RUN TIMING ANALYSIS

update_timing

## SPECIFY SWITCHING ACTIVITY

set_switching_activity ...
set_switching_activity ...

## RUN POWER ANALYSIS

check_power
update_power

## GENERATE REPORTS
report_power
report_power –rails {“t_vdd a_vdd vss” “t_vdd” “a_vdd”}
## GENERATE THRESHOLD VOLTAGE GROUPS LEAKAGE REPORTS
## for default_thrshold_voltage_group: “LVT”
## or threshold_voltage_group: “LVT”
## if defined either in the library or by the user
report_power –threshold_voltage_group –lvth_groups LVT

References
Links to all references and supporting documentation is provided below:

[doc. ref. 1] Reference Methodology Scripts in SolvNet

https://solvnet.synopsys.com/rmgen

[doc. ref. 2] PrimeTime PX User Guide. H-2013.06

https://solvnet.synopsys.com/dow_retrieve/H-2013.06/ptpx/ptpx.html

[doc. ref. 3] PrimeTime and PrimeTime SI User Guide Version H-2013.06

https://solvnet.synopsys.com/dow_retrieve/H-2013.06/ptug/ptug.html

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