B.

Tech 5th Semester, Solved papers, Dec -2018 89

MICROPROCESSING & INTERFACING

Dec - 2018
Paper Code:-EE-309-F

Note : Attempt five questions in all, selecting one question from each Section.
Question No. 1 is compulsory. All questions carry equal marks.

Q.1.(a) What is BSR Mode ? Discuss. (5)

Ans. BSR Mode : The BSR mode is a port C bit set/reset mode. The individual bit of
port C can be set or reset by writing control word in the control register. The control word format
of BSR mode is shown in fig.

Fig. : BSR control word format

The pin of port C is selected using bit select bits [b b b] and set or reset is decided by bit
S/R. The BSR mode affects only one bit of port C at a time. The bit set using BSR mode remains
set unless and until you change the bit. So to set any bit of port C, bit pattern is loaded in control
register. If a BSR mode is selected it will not affect I/O mode.
Q.1.(b) What do you mean by memory segmentation ? (5)
Ans. Segmentation : Segmentation is the process in which the main memory of the
computer is divided into different segments and each segment has its own base address. It is
basically used to enhance the speed of execution of the computer system, so that processor is
able to fetch and execute the data from the memory easily and fast.
Need for Segmentation : The Bus Interface Unit (BIU) contains four 16 bit special
purpose registers (mentioned below) called as Segment Registers.
(i) Code segment register (CS) : is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
(ii) Data segment register (DS) : points to the data segment of the memory where the
data is stored.
(iii) Extra Segment Register (ES) : also refers to a segment in the memory which is
another data segment in the memory.
90 Microprocessing & Interfacing

(iv) Stack Segment Register (SS) : is used for addressing stack segment of the memory.
The stack segment is that segment of memory which is used to store stack data.
Types Of Segmentation :
(i) Overlapping Segment : A segment starts at a particular address and its maximum
size can go up to 64kilobytes. But if another segment starts along this 64kilobytes location of the
first segment, then the two are said to be Overlapping Segment.
(ii) Non-Overlapped Segment : A segment starts at a particular address and its maximum
size can go up to 64kilobytes. But if another segment starts before this 64kilobytes location of the
first segment, then the two segments are said to be Non-Overlapped Segment.
Advantages of the Segmentation : The main advantages of segmentation are as
follows:
(i) It provides a powerful memory management mechanism.
(ii) Data related or stack related operations can be performed in different segments.
(iii) Code related operation can be done in separate code segments.
(iv) It allows to processes to easily share data.
(v) It allows to extend the address ability of the processor, i.e. segmentation allows the
use of 16 bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it
would require 20 bit registers.
(vi) It is possible to enhance the memory size of code data or stack segments beyond 64
KB by allotting more than one segment for each area.

Q.1.(c) How the instructions NOP & HLT work ? Explain. (5)
Ans. NOP instruction :
Mnemonic NOP Flags : It does not affect any flag.
NOP : No operation
Algorithm Do nothing
Addr. Mode Implied addressing mode
Operation The execution of this instruction causes the CPU to do nothing.
(i) This instruction causes the CPU to do nothing.This instruction
uses three clock cycles and increments the instruction pointer to
point to the next instruction.
(ii) It can be used to increase the delay of a delay loop.
Example :
MOV AL, 00011011b
NOT AL ; AL = 11100100b
RET
Flags : all unchanged.
HLT (Halt until interrupt or reset) Instruction :
Mnemonic Halt processing Flags : No flags are affected..
Operation (i) The HLT instruction will cause the 8086 to stop fetching and
executing instructions. The 8086 enters into a half state. To
come out of the halt state, there are 3 ways given below.
(a) Interrupt signal on INTR pin, (b) Interrupt signal on NMI pin
B.Tech 5th Semester, Solved papers, Dec -2018 91

(c) Reset signal on reset pin.

(ii) It may be used as an alternative to an endless software loop in
situations where a program must wait for an interrupt.

Q.1.(d) Explain direct memory access. (5)

Ans. Direct memory access (DMA) is a feature of modern computers that allows
certain hardware subsystems within the computer to access system memory independently of
the central processing unit (CPU).
Without DMA, when the CPU is using programmed input/output, it is typically fully
occupied for the entire duration of the read or write operation, and is thus unavailable to perform
other work. With DMA, the CPU initiates the transfer, does other operations while the transfer
is in progress, and receives an interrupt from the DMA controller when the operation is done.
This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where
the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer.
Many hardware systems use DMA, including disk drive controllers, graphics cards, network
cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors.
Computers that have DMA channels can transfer data to and from devices with much less CPU
overhead than computers without a DMA channel. Similarly, a processing element inside a multi-
core processor can transfer data to and from its local memory without occupying its processor
time, allowing computation and data transfer to proceed in parallel.

Section – A

Q.2.(a) Explain the working of 8085 microprocessor with the help of block
diagram and also explain about the function of each block. (10)
Ans. Architecture of 8085 microprocessor: Fig. shows the architecture of 8085.
We divide the architecture in different groups as follows :
(i) Arithmetic and Logical Group : This group consists of ALU, accumulator,
temporary register and flag register.
ALU : The ALU performs arithmetic and logical operations such as addition, subtraction
ANDing, ORing, EXORing, etc.
Accumulator : The accumulator is a 8 bit general purpose register connected to internal
data bus and to ALU.
Temporary Register : The other input to ALU is given by temporary register. This
register is not available for user. It is only used internally by microprocessor, so the name given
temporary register.
Flag Register : The flag is nothing but a group of flip-flops used to give status of
different operations result.
(ii) Register Group : This group consists of 3 types of registers :
(a) Temporary registers (W and Z) : These are not available for user and are used only
for internal operations such as to store operand immediately operand or address of memory.
These are used internally by microprocessor only to store 8 bit data/information required for
execution of certain instructions.
92 Microprocessing & Interfacing

(b) General Purpose Registers : The 8085 contains 6 general purpose registers of 8
bits each named as B, C, D, E, H and L. These can be used to store 8 bits or can be used to form
a register pair to store 16 bits. The register pairs available are BC, DE and HL. These register
are programmable by user. User can store any data in these registers and use it to perform
different operations.
(c) Special purpose registers : The 8085 contains 3 special purpose registers such as
program counter incrementer/decrementer latch and stack pointer.

Fig : The 8085A Microprcessor : Functional Block Diagram.

(iii) Interrupt Control : This block accepts different interrupt request inputs such as
TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR and informs control logic to take action in response
to each signal. The response for TRAP, RST 7.5, RST 6.5 and RST 5.5 is CALL at restart
address. But for INTR it generates a signal INTA and excepts external device should insert a
RST code or CALL instruction.
(iv) Serial I/O Control Group : The data transferred on D0 to D7 lines is parallel data,
but under certain condition it is advantageous to use serial data transfer. 8085 implements this by
using SID and SOD signals and the data on these lines is accepted or transferred under software
control by serial I/O control block, by using special instructions RIM and SIM.
B.Tech 5th Semester, Solved papers, Dec -2018 93

(v) Instruction Register, Decoder and Control Group :

(a) Instruction Register : When an instruction is fetched from memory it is loaded in
instruction register from there it is provided to decoder for decoding. This register is only activated
when a instruction code or OPcode is available on internal data bus. It is non-programmable
register, i.e., not available for programmers use. Remember it accepts only OPcode of instruction,
operands are not accepted by this instead they are stored in registers.
(b) Instruction Decoder : This accepts a bit pattern from instruction register decodes
it and gives the decoded information to control logic. The information includes what operation is
to be performed, who is going to perform it, how many operand bytes the instruction contains
etc.
(c) Timing and Control : This is a control section of 8085. This accept information
from instruction decoder and generates microsteps to perform it, so 8085 is called as
microprogrammed. In addition to this the block accepts clock inputs and performs sequencing
and synchronising operations required for communication between microprocessor and peripheral
devices.

Q.2.(b) Write an assembly level program for multiplication of two 8 bit

numbers. (10)
Ans. LXI H, 0000 H
MVI B, 00 H
MVI C, 1st number
MVI A, 2nd number
MVI D, 08 H
L2: DAD H
RLC
JNC L1
DAD B
L1 : DCR D
JNZ L2
SHLD 2100 H
HLT.

Q.3.(a) How many addressing modes are there in 8085 ? Explain each with the
help of suitable examples. (10)
Ans. Various addressing modes of 8085 are as follows :
1. Immediate Addressing Mode : In immediate addressing mode the data (8/16 bit)
is specified in the instruction itself. The immediate addressing instructions are either 2 byte or 3
byte long. In 2 byte instruction first byte is OPCODE and second byte is the 8 bit data.

Fig. (a) :Immediate addressing mode instruction format

94 Microprocessing & Interfacing

In 3 byte instructions first byte is OPCODE, second and third bytes are the 16 bit data.
The instructions containing the letter “I” indicate immediate addressing mode. Fig. (a) shows the
location of operand.
Examples :
(i) MVI A, A0 H : This instruction transfers immediate data (A0 H) to A register.
(ii) LXI H, C200H : This instruction transfers 16 bit immediate data C200 to HL register
pair. Lower order data (00 H) to L register and high order data (C2H) to H register.
2. Register Addressing Mode : In register addressing mode the source and destination
operands are general purpose registers. The register addressing instructions are generally of 1
byte i.e. OPCODE only. The OPCODE specifies the operation and registers to be used to
perform the operation. Fig. (b) shows the location of operand.

Fig. (b) : Register addressing mode instruction format

Examples :
(i) MOV D, B : This instruction copies the contents of register B to the D register. The
source and destination operands are both registers.
(ii) ADD B : This instruction adds the contents of B register and A register. The data is
present in both B and A registers. The result is stored in the accumulator.
(iii) PCHL : This instruction will transfer the contents of register pair HL to the PC.

3. Direct Addressing Mode : In direct addressing mode the 16 bit address of the
operand is given within the instruction itself. The instrucctions in the direct addressing mode are
3 byte instruction. First byte is a OPCODE, second is lower order address byte and third is
higher order address byte. For I/O instruction that use direct addressing mode are 2 byte as the
address of I/O is one byte. Fig. (c) shows the location of operand.

Fig.( c) : Direct addressing mode instruction format

B.Tech 5th Semester, Solved papers, Dec -2018 95

Examples :
(i) LDA C200H : Load accumulator directly from memory location. In this instruction
the contents of C200 memory location are transferred to accumulator.
(ii) STA C200 H : Store accumulator directly to memory location. In this instruction the
contents of accumulator are stored at memory location C200 H.
4. Indirect Addressing Mode : In indirect addressing mode the instructions reference
the memory through a register pair i.e. the memory address where the operand is located is
specified by the contents of a register pair. Fig. (d) shows the location of operand.

Fig.(d) Indirect addressing mode instruction format

Examples
(i) MOV A,M : In this case M is a memory pointer specifying HL register pair where the
address is stored. The contents of HL pair are used as address and the contents of that memory
location are transferred to accumulator.
(ii) LDAX B : In this case BC register pair is used as address and the contents of the
memory location specified by BC register pair are copied to accumulator.

5. Implied Addressing or Implicit Addressing Mode : The implied mode of

addressing does not require any operand. The data is specified within the OPCODE itself.
Generally, the implied addressing mode instruction is a 1 byte instruction. The data is supposed
to be present generally in accumulator.
Example :
(i) RAL : Rotate accumulator left, it operates on the data in accumulator only. So whenever
RAL is used it is implied that the data to be operated on is available in the accumulator only.
(ii) CMC : Complement carry flag.

Q.3.(b) What do you mean by interrupts ? How many types of interrupts are
there in 8085 ? Explain each. (10)
Ans. Interrupts : The interrupt driven I/O is one of the data transfer techniques used
in the microprocessor systems. By using this techniques, the external device or a peripheral can
inform the processor that it is ready for communication.
8085 microprocessor provides hardware and software interrupts.
Hardware Interrupts : 8085 microprocessor provides five hardware interrupt viz.
TRAP, RST 7.5, RST 6.5, RST5.5 and INTR. The interrupt structure is a five level structure.
96 Microprocessing & Interfacing

(i) TRAP : It is non-maskable edge and level triggered interrupt, request input line. It is
used for emergency purpose like power failure, parity error checker, smoke detector etc. The
microprocessor does not execute any interrupt acknowledge cycle to read interrupt information
from the interrupting device. The interrupt information is provided by control section of
microprocessor internally. But microprocessor executes ideal machine cycle to acknowledge
this interrupt. To generate starting address of TRAP interrupt service routine. The TRAP signal
must make low to high transition and remain high until acknowledged that means this interrupt is
triggered only at the rising edge of the signal. The avoids false trigerring due to noise or glitches.
It is not affected by any instruction. It has the highest priority among all interrupt. It is always
enabled. This interrupt transfers microprocessors control to location 0024 H. User cannot rest
TRAP flip-flops that means we cannot cancel this interrupt.
(ii) RST 7.5 : It is maskable edge triggered interrupt request input line. The microprocessor
does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting
device. The interrupt information is provided by control selection of microprocessor internally.
Instead of interrupt acknowledge cycle, the microprocessor executes ideal machine cycle (6T)
to acknowledge this interrupt. During this cycle it executes RST 7.5. Instruction to generate
starting address of interrupt service routine. This interrupt is triggered at the rising edge of the
signal. It priority among all maskable interrupt. This interrupt to location 003CH. User can reset
R 7.5 flip-flop that means we can cancel this interrupt by SIM instruction.
(iii) RST 6.5 and RST 5.5 : These are level triggered maskable interrupt request input
lines. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt
information from the interrupting device. The microprocessor executes idle machine cycle (6T)
to acknowledge these interrupts. Durring this cycle it executes RST 6.5 and RST 5.5 instructions
to generate address of ISR 6.5 and ISR 5.5 respectively. They can be disabled by executing SIM
or EI instruction. RST 6.5 transfers microprocessor’s control to location 0034 H while RST 5.5
transfers microprocessor’s control to location 002 CH.
(iv) INTR : It is level triggered, maskable interrupt request input line. The microprocessor
executes interrupt acknowledge cycle to read interrupt information from interrupting device.
The microprocessor executes one interrupt acknowledge cycle (6T) and three interrupt
acknowledge cycles (6T + 3T + 3T) for RST N and CALL instructions respectively.
The starting address of ISR depends upon interrupt information. This interrupt is not
affected by SIM instruction. It is enabled by executing EI instruction while disabled by DI
instruction.
Software interrupts : (i) In case of software interrupts the cause of the interrupt is the
execution of the instruction.
(ii) The microprocessor 8085 has eight instructions. These eight instructions are RST 0
to RST 7. Such interrupts are called as software interrupts.
(iii) They allow the microprocessor to transfer program control from the main program
to the subroutine program (i.e. predefined service routine addresses).
(iv) After completing the subroutine program, the program control returns back to the
main program.
B.Tech 5th Semester, Solved papers, Dec -2018 97

Section – B

Q.4.(a) Explain the block diagram of 8086 microprocessor in detail. (14)

Ans. Block Diagr am of 8086 : The block diagram of 8086 microprocessor is shown in
figure. As shown in block diagram, the 8086 is divided into two independent functional units. The
Bus interface Unit (BIU) and the Execution.

Fig. : Block diagram of 8086 microprocessor

(i) The Bus Interface Unit : The Bus Interface unit fetches instructions from memory,
reads data from ports and memory and writes data to ports and memory. It handles all transfers
of data and addresses on the buses for the execution unit. The Bus interface Unit consists of the
following :
(a) Instruction Queue
(b) Segment Registers
(c) Instruction Pointer
(a) Instruction Queue : The instruction queue is a first-in-first-out group of registers.
To speed up program execution, the Bus Interface Unit fetches as many as six instruction bytes
98 Microprocessing & Interfacing

are held for the Execution Unit in a Instruction Queue. The BIU can be fetching instruction
bytes while the Execution Unit (EU) is decoding the instruction or executing an instruction which
does not require use of the buses. When the Execution Unit is ready for its next instruction, it
simply reads the instruction from the Instruction Queue in the BIU. This scheme is much faster
than sending out an address to memory and then waiting for memory to send sack the next
instruction byte. The prefetch instruction and queue scheme greatly speeds up processing. The
arrangement of fetching the next instruction while the current instruction executes is called pipe
lining.
(b) Segment Registers : The Big Interface Unit (BIU) contains four 16 bit segment
registers. They are :
– Code Segment Register (CS)
– Stock Segment Register (SS)
– Extra Segment Register (ES)
– Data Segment Register (DS)
(c) Instruction Pointer : The instruction pointer register is a 16 bit register which holds
the address of the next code byte that is to be fetched within the code segment. This register
contains the address value which is an offset, because this value must be added to the segment
base address contained in CS register to produce the required 20 bit physical address.
(ii) The Execution Unit : The execution unit of 8086 performs the following major
operations :
– It tells the BIU, from where to fetch instructions or data.
– It decodes and executes instructions.
To perform the above operations, the execution unit consists of the following sections :
(a) Instruction Decoder, ALU and control circuitry.
(b) Flag Register
(c) General Purpose Registers
(d) Stack Pointer Register
(e) Other Pointer and Index Registers
(a) Instruction decoder, ALU and control circuitry : The instruction decoder in the
EU translate instructions fetched from memory into a series of actions which are further carried
out. The Arithmetic and Logic Unit (ALU) of 8086 is of 16 bits which can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift the binary numbers. All internal operations
of EU are controlled by control circuitry.
(b) Flag register : 8086 microprocessor contains one 16 bit flag register (status register).
A flag register is a flip flop which indicates the status of some conditions produced by the
execution of an instruction or controls certain operations of the Execution Unit. In a 16 bit flag
register, there are nine active flags. Six of the nine flag bits are used to indicate some conditions
produced by an instructions. These six flags are called status flag (conditional flags). The remaining
three flag bits in the flag register are used to control certain operations of the processor and are
called control flags.
(c) General purpose registers : The execution unit 8086 contains eight general purpose
registers labelled as AH, AL, BH, BL, CH, CL, DH and DL in the fig. below.
B.Tech 5th Semester, Solved papers, Dec -2018 99

Fig. : 8086 general purpose register

(d) Stack pointer register : The stack pointer register SP is a 16 bit register which
contains the 16 bit offset address from the start of the stack segment to the memory location
where a word was most recently stored on the stack. The stack memory location where a word
was most recently stored is called top of the stack.
(e) Other pointer and index registers : In addition to the stack pointer register SP, the
EU of the 8086 also contains a 16 bit base pointer register BR The base pointer register BP
contains the 16 bit offset address relative to the stack segment register SS but it is employed in
the based addressing mode of 8086.

Q.4.(b) What is pipelining ? (6)

Ans. Pipelining : The process of fetching the next instruction, when the present
instruction is being executed is called as pipelining. Pipelining has become possible due to the use
of queue. BIU fills in the queue, until the entire queue is full. BIU restarts filling in the queue
when atleast two locations of queue are vacant.
Advantage of Pipelining :
(i) The EU always reads the next instruction byte from the queue in BIU. This is much
faster than sending out an address to the memory and waiting for the next instruction byte to
come.
(ii) In short pipelining eliminates the waiting time of EU and speeds up the processing.
(iii) The 8086 BIU will not initiate a fetch unless and until there are two empty bytes in
its queue. 8086 BIU normally obtains two instruction bytes per fetch.

Q.5.(a) How many addressing modes are there in 8086 microprocessor ? Explain
each in detail. (10)
Ans. The 8086 microprocessor is provided with various addressing techniques called
addressing modes of 8086 are :
(i) Register Addressing
(ii) Immediate Addressing
(iii) Direct Addressing
(iv) Resister Indirect Addressing
(v) Direct Relative Addressing
(vi) Based Index Address
(vii) Relative Based Index Addressing.
The various modes have been discussed below alongwith examples.
(i) Register Addressing : In this type of addressing, the operand to be accessed is
specified as residing on one of the internal register of 8086.
100 Microprocessing & Interfacing

The contents of CX (16 bit word), the source operand is moved to BX, the destination of
operand. In this instruction, both the source and destination operand have been specified as the
consents of external registers of 8086, i.e., CX and BX respective.
The datum is in the register that is specified by the instruction for a 16 bit operand, a
register may be AX, BX, CX, DX, SI, DI, SP or BP and for an 8 bit operand a register may be
AL, AH, BL, BH,CL,CH,DL, or DH.
Instruction Register
Register  Operand
(ii) Immediate Addressing : In this type of addressing the source operand is the part
of the instruction itself instead of the contents of any internal register or memory location. The
immediate operand can be either a byte or word of data.
Example : MOV BL, 10 H
The source operand is 10H and is an example of byte wide immediate source operand.
MOV BX, 1234 H
The source is 1234H and is an example of word wide immediate source operand.
Instruction
Operand
(iii) Direct Addressing : In this type of addressing the bit effective memory address of
the operand follows the instruction opcode. This effective address (EA) is actually an offset of
the storage location of the operand from the location specified by the current value of the DS
register. The EA is combined with the current content of DS in the 8086 to produce the actual
physical address (PA) of the operand. As an example, in the following instruction. The source
operand follows the direct addressing mode.
MOV CX, [1234]
It means “Move the contents of the memory location which is at an offset 1234 from the
current data segment, into the internal register CX”. When the instruction is executed, the 8086
combines 1234 H with the current contents of DATA segment to get the physical address of the
source operand. Let DS = 0400H. Then, PA = 04000 + 1234 = 05234 H. So the contents of the
physical address 05234 H its copied into the internal register CX of 8086.
(iv) Register Indirect Addressing : In this mode, the effective address of the operand
is not the direct part of the instruction, but resides in either a base register or an index register
within the 8086. The base register can either be BX or base pointer register BP, and the enclose
register can either be SI or DI, i.e., source index register a destination index register.
Example : MOV. CX [SI] The EA is in the source index register.
“Move the contents of the memory location when is at on offset equal to the contents of
source index register from the current data segment, into the internal response CX”.
Let, DS = 0400H, SI = 1002H
PA = 0400 + 1002 = 05002 H
and then the contents of 05002H memory location is stored into internal register CX of
8086.

(v) Direct- Relative Addressing : In this type of addressing, the EA of the operand in
the sum of an 8 bit displacement and the contents of either a base register or an index register.
B.Tech 5th Semester, Solved papers, Dec -2018 101

The base register can be either BX or BP and index register can be either SI or DI. As
an example, in the following instruction the EA is the sum of source indirect displacement.
MOV AH, [SI] + DISP
i.e., EA = DI + EA + DISP
PA = DS + EA
Let, [DS] = 0400H
[SI] = 2000H and
DISP = 1234 H
PA = 04000 + 2000 + 1234 = 007234H
04000
2000
+ 1234
_ __ __ __ __ _ __ __ __ _ __ __ __ __ _

07234
Then as a result of the indirect on given above the contents of 07234H is copied in the
AH register, i.e., higher-byte part of register AX of 8086.
 (BX) 
 (BP) 
  + 8 bit or 16 - bit displacement
EA =  (SI) 
 
 (DI) 
Based-Index Addressing : The EA in this type of addressing mode is calculated as
the sum of the contents of any base register and the contents of an array index register. The base
register can be either BX or BP and the index register can be either SI or DI. Both of the base
register and index register contents are specified in the instruction itself. As an example, the EA
on the following instruction is the sum of contents of BX and is register.
MOV AH, [BX] [SI]
Then, EA = [BX] + [SI]
Let [DS] = 0400H, [BX] = 2000H, [SI] = 1000 H
PA = 0400 + 2000 + 1000 = 07000H
and as a result of above mentioned instruction, the consents of 07000H is opend on the
AH register of register.
 (BX)   (SI) 
EA =  + 
 (BP)  (DI) 
Relative Based Indexed : In this more powerful mode of addressing, the EA is given
as the sum of an 8 bit or 16 bit displacement and a based indirect address, i.e.,
(BX)   (SI) 
 or  +  or   8 bit displacement or 16-bit displacement
EA =    
 (BP)   (DI) 
As an example, the EA in the following instruction to the sum of contents 01 BX, SI and
actual given direct displacement “DISP”.
MOV [BX] [SI] + DISP, AH
ED = [BX] + [SI] + DISP
102 Microprocessing & Interfacing

Let, [DS] = 0400H, [BX] = 2000H, [SI] = 1000H AND DISP = 1234H
PA = 04000 + 2000 + 1000 + 1234H = 08234H.
and as a result of the above proportional instruction, the contents of register ‘AH’ to
copied onto the memory location having address = 08234H.

Q.5.(b) What do you mean by Instruction format ? How many types of

instructions format are being used in 8086 microprocessor ? Explain. (10)
Ans. In 8086 all instruction will not be of same size. The instruction vary from 1 to 6
bytes in length. The length of instruction bytes is dependent upon addressing mode used by
programmer i.e. immediate, register register relative, based indexed, relative based indexed and
so on.
Basically instruction bytes will contain information of :
(i) OPCODE
(ii) Addressing mode designations :
(a) 2 byte Effective Address.
(b) 1 or 2 byte displacement.
(c) 1 or 2 byte immediate operand.
From Fig.1.(a) normally first byte is OPCODE byte, second byte normally specifies
addrssing mode. Sometime it may also contain OPCODE part. After OPCODE and addressing
mode bytes, we have following different cases :
(a) No additional bytes [fig.1(a), fig.1(b), fig.1(c), fig.1(d)]
(b) A 2 byte EA (for direct addressing mode [fig.1(e)].
(c) A 1 or 2 byte immediate operand [fig.1(f)]
(d) A 1 or 2 byte displacement followed by 1 or 2 byte immediate operand [fig.1.(g)]
One - byte instruction - implied operand(s) REG - Register
(a) OPCODE MOD - Mode
R/M - Register or memory
One - byte instruction - register mode DISP - Displacement
DATA - Immediate data
(b) OPCODE REG
Register to register
( c ) OPCODE 11 REG R/M
Register to/from memory with no displacement
(d) OPCODE MOD REG R/M
Register to/from memory with displacement
(e) OPCODE MOD REG R/M Low-order DISP High-order DISP
(If 16-bit displacement is used)
Immediate operand to register
(f) OPCODE 11 OP CODE R/M Low-order DATA High-order DATA
(If 16-bit data are used)
Immediate operand to memory with 16-bit displacement
(g) OPCODE MOD OP CODE R/M Low-order DISP High-order DISP Low-order DATA
(If 16-bit data are used)
Fig.(1) : Summary of 8086 instruction format
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If a displacement or immediate operand is 2 bytes long, the low order byte always
appears first, this is Intel standard.
BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
LOW HIGH
LOW DISP/DATA HIGH DISP/DATA
OPCODE D W MOD REG R/M DATA DATA

Register operand/register to
use in EA calculation

Register operand/extention of OPCODE

Register mode/memory mode
with displacement length
Word/byte operation
Direction is to register/direction
is form register
Operation(instruction) code

Fig.(2) : instruction format

As shown in fig.(2) the first six bits of multibyte instruction generally contains an opcode
that identifies the basic instruction type i.e. ADD, XOR etc. The following bit, called the D field,
generally specifies the direction of the operation.
D = 1 means instruction source is specified in REG field.
D = 0 means instruction destination is specified in REG field.
The next following bit is W. This bit identifies between byte and word operation.
W = 0 Instruction operates on byte data
= 1 Instruction operates on word data
In this we have three single bit fields S, V, Z.
S bit : S bit is used in conjunction with W to indicate sign extension of Immediate fields
in arithmetic instructions.
S = 0 No sign extension
= 1 Sign extended 8 bit immediate data to 16 bits if W = 1.
Therefore for 8 bit operation : S = W = 0
16 bit operation with a 16 bit immediate operand : S = 0, W = 1
16 bit operation with a sign externded 8 bit immediate operand : S = W = 1
V bit : Used by shift and rotate, to determine single and variable – bit shifts and rotate.
V = 0 shift/rotate count is one
= 1 shift/rotate count is specified in CL register.
Z bit : This bit is used as a compare bit with zero flag in conditional repeat (REP) and
loop instructions.
Z = 0 Repeat/loop while zero flag is clear
= 1 Repeat/loop while zero flag is set.
MOD : The mode (MOD) field indicates whether one of the operands is in memory or
whether both operands are register.
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REG : The Register (REG) field identifies a register that is one of the instruction operands
REG field depends upon W bit.
R/M (Register or memory) : This field is of 3 bits. The meaning of R/M bits changes
depending upon mode (MOD) field.
Section – C
Q.6. Explain the following :
(a) Data Transfer Instructions (6)
(b) Shift and Rotate Instructions (7)
(c) Branch Instructions (7)
Ans. (a) Data Transfer Instructions :
data  data
source Destination
The instructions which are used to transfer 8/16 bit data from source to destination are
called as data transfer instructions. The previous data of source is not lost, but the previous data
of destination will be lost.
(i) MOV Rd, Rs
(Move data of Source register Rs into Destination register Rd)
Rs Rd
data  data
Source Destination
(Register direct addressing mode)
(Single byte instruction)
(ii) MVI Rd, Data (8 bit) : (Move immediate data into Destination register Rd)
data  data
Rd
Rd can be A, B, C, D, E, H, L
Addressing mode of this instruction is immediate, and it is double byte instruction.
(iii) LXI Rp data (16 bit)
(Load register pair Rp with immediate data)
data  data
Rp
Rp  B D H
| | |
BC DE HL
pair pair pair
(Immediate addressing mode)
(Triple byte instruction)
(iv) MOV M, Rs (Move Source register Rs data into memory location)
data data Address
Rs M HL pair
(Register indirect addressing mode) (Single byte instruction).
B.Tech 5th Semester, Solved papers, Dec -2018 105

Ans.(b) Shift Instructions : Shift instructions are used to position or move binary data
to the left or right by shifting them within the register or memory location. They also perform
multiplication by powers of 2+ n (left shift) and division by power of 2n (right shift). The shift
operations can be classified as logical shifts and arithmetic shifts.
The following are main shift instructions :
(i) SHL/SAL : (Shift logical/arithmetic left byte or word)
(ii) SHR : (Shift logical right byte or word)
(ii) SAR : (Shift arithmetic right byte or word)
Rotate instructions : Rotate instructions move binary data by rotating the information
in a register or memory location, either from one end to another or through the carry flag.
The following are main rotate instructions :
(i) ROL : (Rotate left byte or word)
(ii) ROR : (Rotate right byte or word)
(iii) RCL : (Rotate through carry left byte or word)
(iv) RCR : (Rotate through carry right byte or word)

Ans.(c) Branching Instructions : The programmer will prepare all the program using
instructions in the form of mnemonics. These mnemonics are translated in to Hex Codes. These
Hex Codes are stored in sequence in successive memory locations.
When microprocessor executes the program, then it will transfer instruction opcode
from memory to instruction register (Opcode fetch operation) and this instruction opcode is
decoded. One circuit is execute which all perform the operation of corresponding instruction.
When microprocessor performs opcode fetch or second byte reading or third byte reading
from memory, then for selecting memory location microprocessor will transfer 16 bit number
from program counter to address pins. After each opcode fetch, second byte reading, third byte
reading, the address in PC is auto incremented by one. So microprocessor will normally read
instruction codes in sequence from successive memory locations.
But if a new 16 bit address is transferred into PC, then old address of PC is lost. Hence,
when microprocessor will read next instruction code, then it will transfer this new address from
PC to address pins, so microprocessor will branch from one location to another. These instructions
which are used to transfer new 16 bit address into PC are called as Branching instruction.
(i) PCHL (Transfer HL pair data into PC)
X X
HL PC
(ii) JMP address (16 bit) (Unconditional Jump)
address  address
PC
For example, JMP 5000 H ; 5000 H 
PC
With JMP 5000 H, PC is loaded with 5000 H.

Q.7. What do you mean by directives ? Describe the different types of directives
used in 8086 microprocessor. (20)
106 Microprocessing & Interfacing

Ans. Assembler directives : Assembler directives are statements which give direction
to the assembler to perform the task of assembly process. These are not translated into machine
code.
Commonly used assembler directive in 8086 assembly language programming are explained
below :
(i) ASSUME : The assume directive is used to tell the assembler the name of the logical
segment it should used for a specified segment. The statement ASSUME CS:CODE for example
tells the assembler that the instructions for a program are in a logical segment named CODE.
The statement ASSUME DS: DATA tells the assembler that for any program instruction which
refers to the data segment, it should use the logical segment called DATA. If, for example, the
assembler reads the statement MOV AX, [BX] after it reads this ASSUME, it will know that the
memory location referred to by [BX] is in the logical segment DATA.
(ii) ALIGN : The align directive is used to align the next segment at an address divisible
by specified number. The general syntax for this directive is as shown below :
ALIGN n
where n can be 2, 4, 8 or 16
(iii) CODE : The code directive is used to provide shortcut in definition of the code
segment. General syntax for this directive is as shown below :
.code [name]
The name is optional.
(iv) DATA : The data directive is used to provide shortcut in definition of the data
segment.
(v) GROUPS : A program may contain several segments of the same type i.e. code,
data, or stack. The purpose of the GROUP is to collect them all under one hut, so that they reside
within one segment, usually a data segment.
Format : Name GROUP Seg–name,......., Seg–name.
(vi) LENGTH : It is an operator which tells the assembler to determine the number of
elements in some named data item such as a string or array.
(vii)MACRO and ENDM : The macros in the program can be defined by MACRO
directive. ENDM directive is used along with the MACRO directive. ENDM defines the end of
the macro.
(viii) NAME : The name directive is used at the start of a source program to give
specific names, to each assembly module.
(ix) OFFSET : It is an operator which tells the assembler to determine the offset or
displacement of a named data item (variable) from the start of the segment which contains.
(x) ORG : It is an assembler that uses a location counter to account for its relative
position in a data or code segment.
Format : ORG expression
(xi) PAGE : The PAGE directive help to control the format of a listing of an assembled
program. At the start of a program the PAGE directive specifies the maximum number of lines
to list on a page and the maximum number of characters on a line.
Format : PAGE [length], [width]
(xii) ENDP : ENDP directive is used along with the PROC directive. ENDP defines
the end of the procedure.
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(xiii) TYPE : It is an operator which tells assembler to determine the type of specified
variable. Assembler determines the type of specified variable in number of bytes. For byte type
variable the assembler gives a value of 1. For word type variable the assembler gives a value of
2 and for double word type variable the assembler gives a value of 4.
Section – D
Q.8. Explain the following in detail :
(a) Programmable Interval Time (10)
(b) DMA Controller (10)
Ans.(a) Programmable Interval Time : Intel 8255 is a programmable Interval Timer/
Counter which can generate accurate time delays and waveforms ranging from 0 Hz to 2 MHz
using software control. 8254 is its upgraded version which can operate with higher clock frequency
range (DC – 8 MHz) and it is pin to pin compatible with 8253.
Intel 8253 is a 24 Pin IC which requires a single + 5 V power supply. It consists of three
identical but independent 16 bit down counters. Each counter can be used either as 16-bit binary
counter or as 16 bit BCD counter. For binary counter the maximum data is FFFF H whereas for
BCD counter the maximum data that can be loaded in the counter is 10000 D.
Each counter will decrement by one at each negative edge of clock input. Each counter
can be used in six different modes, Mode 0 to Mode 5. In different modes different types of
waveforms are obtained on OUT Pin.
The block diagram of 8253 Programmable interval timer (PIT)/counter is as shown in
Fig.(1).

Fig.(1) : 8253 Functional block diagram

108 Microprocessing & Interfacing

It has three independent 16 bit down counters (Counter 0, Counter 1, Counter 2), a data
bus buffer, read/write control logic and a control word register. Each counter has two input
signals (CLK and GATE) and output signal (OUT).

Ans.(b) Direct memory access (DMA) is a feature of modern computers that allows
certain hardware subsystems within the computer to access system memory independently of
the central processing unit (CPU).
Without DMA, when the CPU is using programmed input/output, it is typically fully
occupied for the entire duration of the read or write operation, and is thus unavailable to perform
other work. With DMA, the CPU initiates the transfer, does other operations while the transfer
is in progress, and receives an interrupt from the DMA controller when the operation is done.
This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where
the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer.
Many hardware systems use DMA, including disk drive controllers, graphics cards, network
cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors.
Computers that have DMA channels can transfer data to and from devices with much less CPU
overhead than computers without a DMA channel. Similarly, a processing element inside a multi-
core processor can transfer data to and from its local memory without occupying its processor
time, allowing computation and data transfer to proceed in parallel.
The device which supervises, data transfer is named as DMA controller. Now let’s have
diagrammatic representation of the scheme, which depicts microprocessor, DMA controller,
memory and I/O device.

Fig. : DMA controller scheme

B.Tech 5th Semester, Solved papers, Dec -2018 109

Let’s understand the concept clearly.

(1) Initially, switches S1, S2 and S3 are at position A.
(2) No direct access to memory by I/O.
(3) Microprocessor is MASTER of all three buses; address, data and control.
(4) Microprocessor treats DMA controller, as I/O device ONLY.
(5) Using IN/OUT instruction, you can program DMA controller chip, for various modes.
(6) Whenever, peripheral device is ready to transfer data, DIRECTLY to memory, it
will generate REQUEST (DRQ  DMA REQUEST), to DMA controller, asking
for direct access.
(7) In response to DRQ, DMA controller will activate, HRQ (HOLD request); connected
to HOLD pin of microprocessor. By activating HOLD line, DMA controller request
microprocessor, to HOLD for sometime and allow him to become a master of all
three buses.
(8) Moment HOLD pin is HIGH, microprocessor will complete the present job and also
activate HLDA (HOLD acknowledge) signal; informing, DMA controller to become
master.
(9) Microprocessor tristates, all its buses, so total cutoff from memory and I/O device.
Thus microprocessor relinquishes the buses and provides control to DMA controller.
(10) Now DMA controller is master. It will position all three switches to position B.
(11)DMA controller will also generate DACK (DMA acknowledge) signal to peripheral
device; informing that, direct access is allowed.
(12) Now it will generate address and control signal. Data will flow from memory to
I/O or vice-versa.
(13) After completing data transfer, DMA controller will deactivate HOLD line. It also
positions, switches back to position A.
(14) Now microprocessor will regain the control over the three buses.
(15) Microprocessor will start executing instructions from main program. Till DMA is
inactive or not master of the bus, is referred as DMA IDLE Cycle. When DMA
controller gains the control, it is referred as DMA Active Cycle.

Q.9. What do you mean by PPI ? Explain the following with the help of :
(a) Block Diagram and (10)
(b) Pin Diagram (10)
Ans. Introduction : 8255 is a programmable IC and it consists of input/output ports.
These input/output ports can be used for connecting input/output devices (Peripherals) with
microprocessor. As it is programmable hence any port can be defined either as input port or as
output port using software without changing any hardware connection. Hence it is called
programmable peripherals interface (PPI). It is used for parallel data transfer. It consists of :
(1) Two 8-bit ports Port A and Port B.
(2) Two 4-bit ports Port C upper and Port C lower. These two 4-bit ports can be used
independently or it can be used together as one 8-bit port.
(3) 8-bit Control Word Register (CWR).
110 Microprocessing & Interfacing

When data transfer is performed using handshake signals then for Port A handshake
signals are generated on Port Cupper pins, hence Port A and Port C upper are called Group A.
Similarly handshake signals for Port B are generated on Port Clower, so Port B and Port Clower
together are called Group B.
Internal block diagram : 8255 is used as a general purpose device to interface peripheral
devices to the microcomputer system bus. The block diagram of 8255 is shown in Fig.(1).

Fig.(1) : Block diagram of 8255

Data bus buffer : This 8 bit tristate bidirectional buffer is used to interface the 8255 to
the system data bus. Input or Output instructions executed from CPU to the ports or control
register and input data to the CPU from the ports or status register are all passed through the
buffer.
Read/Write Control Logic : The control logic block accepts control bus signals as
well as inputs from the address bus, and issues commands to the individual group control blocks.
Explanation of the signals of this block is given below :
 
Chip Select CS : This is an active low input which must be enabled for data transfer
operation between the CPU and 8255.
WR  (Write) : When this pin is made low, the CPU can write the data on to the ports
through the data bus buffer.
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RD (Read) : When this pin is made low, the CPU, can read the data in the ports
through the data buffer.
A0 and A1 : These input signals alongwith RD and WR inputs control the selection of
the control/status word register or one of the three ports.
8255 also contains signal lines to connect the device to the microprocessor buses. The
data lines are used to write data byte to a port or to the control register and to read bytes from a
port or the status register under the control of RD and WR lines.
The address input A0 and A1 are used to select or access one of the three ports or the
control word register. ‘00’ port A, ‘01’ port B, ‘10’ port C and ‘11’ control register. The chip
select signal CS enables it for or reading or writing. Fig.(2) shows a expanded version of internal
structure, including a control register.

Fig.(2) : Expanded version of Control logic and I/O ports

Reset : The RESET input of the 8255 is connected to the system reset line. When the
microprocessor or the system is reset all the ports are initialized as input lines. When this input is
made high, the control register is cleared and all the ports are set to the input mode.
112 Microprocessing & Interfacing

Pin diagram of 8255 is as shown in Fig.(3).

Fig.(3) : Pin diagram of 8255