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ECE3004
Microprocessors & Microcontrollers
Dr. M Suresh
School of Electrical & Electronics Engineering
Module5: ARM Microcontroller
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1. Necessity of RISC Processor
2. ARM processor fundamentals
3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5 stage Pipeline
8. Pipeline Hazards
VIT BHOPAL UNIVERSITY ARM – Advanced RISC Machine
John Cocke and his team,
IBM researcher designed
in 1974
1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
Necessity of RISC Processor
➢ RISC provides high performance per watt for battery
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operated devices where energy efficiency is key. A
RISC processor executes one action per instruction.
By taking just one cycle to complete, operation
execution time is optimized.
➢ To make hardware simpler with simple instruction set
so that it can process faster
➢ Uniform instruction length
➢ RISC operate on Load- Store architecture. Memory
can be accessed only for load and store and all rest
instructions should be used the registers only. This
reduces the memory access time!
1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
ARM Processor Fundamentals
One of the most common electronic architectural designs
in the market is Advanced RISC Machine Architecture, even
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better than x86, which is very common in the server
market. ARM Architecture is widely used in smartphones,
normal phones, and also in laptops. Though x86
processors have optimized performance ARM Processor
gives cost-effective processors with small size, takes less
power to run, and also gives better battery life.
ARM Processor is not only limited to mobile phones but is
also used in Fugaku, the world’s fastest supercomputer.
ARM Processor also gives more feasibility to designs of
hardware designers and also gives control to designer’s
supply chains
VIT BHOPAL UNIVERSITY ARM Processor Fundamentals
WIC: Wakeup
Interrupt
Controller
NVIC: Nested
Vector Interrupt
Controller
ETM:
Embedded
Trace Macrocell
DAP: Debug
and Access Port
ARM Processor Fundamentals
1. Multiprocessing Systems: ARM processors are designed to be used in cases of multiprocessing
systems where more than one processor is used to process information. The First AMP processor
introduced by the name of ARMv6K could support 4 CPUs along with its hardware.
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2. Tightly Coupled Memory: The memory of ARM processors is tightly coupled. This has a very fast
response time. It has low latency (quick response) that can also be used in cases of cache memory
being unpredictable.
3. Memory Management: ARM processor has a management section. This includes Memory
Management Unit and Memory Protection Unit. These management systems become very important
in managing memory efficiently.
4. Thumb-2 Technology: Thumb-2 Technology was introduced in 2003 and was used to create
variable-length instruction sets. It extends the 16-bit instructions of initial Thumb technology to 32-bit
instructions. It has better performance than previously used Thumb technology.
5. One-Cycle Execution Time: ARM processor is optimized for each instruction on the CPU. Each
instruction is of a fixed length that allows time for fetching future instructions before executing the
present instructions. ARM has CPI (Clock Per Instruction) of one cycle.
6. Pipelining: Processing of instructions is done in parallel using pipelines. Instructions are broken
down and decoded in one pipeline stage. The channel advances one step at a time to increase
throughput (rate of processing).
7. A large number of Registers: A large number of registers are used in ARM processors to prevent
large amounts of memory interactions. Records contain data and addresses. These act as a local
memory store for all operations.
ARM Processor Advantages
➢ ARM processors deal with a single processor at
a time, which makes it faster and it also
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consumes lesser power.
➢ ARM processors work in the case of a
multiprogramming system, where more than one
processor is used to process information.
➢ ARM processors are cheaper than other
processors, which makes them usable in mobile
phones.
➢ ARM processors are scalable, and this feature
helps it in using a variety of devices.
ARM Processor Disadvantages
➢ ARM processors are not stable with x86
processors, and due to this, they cannot
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be used in Windows Systems.
➢ ARM processors are not capable of very
high performance, which limits them to a
variety of applications.
➢ ARM processor execution is a little hard,
which requires skilled programmers to
use it.
➢ ARM processor is inefficient in handling
Scheduling instructions.
1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
VIT BHOPAL UNIVERSITY ARM7TDMI Features
1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
Register Set
general purpose and special purpose [total 37 registers]
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Register count:
R0 to R15 : 16
CPSR : 1 [Current Processor Status Register]
SPSR : 5 [Saved Processor Status Register]
LR : 5 [Link Register]
SP : 5 [Stack Pointer]
R8 to R12 in FIQ :5
Register Set
general
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purpose and
special purpose
[total 37
registers]
FIQ: high priority / Fast Interrupt Request
IRQ: low priority / Normal Interrupt Request
SVC: entered on reset and when software interrupt is executed
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Abort: to handle memory access violations
Undef: used to handle undefined instructions
System: privileged modes using the same registers of user mode
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Observe that, there is no SPSR in user mode – SPSR is
used to save the value of CPSR when mode is changed
from user to some other!
Register Set
When mode is changed from one mode to other: let us say USER
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to FIQ: then
1. CPSR [current] is loaded into SPSR [saved]
2. PC is loaded into LR
Let us assume that a jump occurs at address “N”: then
• PC is loaded with N+4
• LR is loaded with PC+4
• On return, PC is loaded with LR-4
VIT BHOPAL UNIVERSITY Register Set: SP
SP (Stack Pointer)
• The stack pointer, often known as the SP
register, is located in register r13.
• Each exception mode has its own version
of r13, pointing to a stack specialised to
that mode.
• Temporary values are stored in the stack.
Register Set: LR
LR (The link register)
The Link register, also known as register
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r14, is used to store the subroutine’s return
address.
• When an exception occurs, the version of
r14 in the exception mode is set to the
address after the instruction is executed.
• SPSR is a copy of the CPSR just before an
exception has occurred.
Register Set: PC
• The Program Counter, sometimes known as the PC, is located in
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register r15.
• The Program Counter is automatically incremented by the size of
the instruction executed. This size is always 4 bytes in ARM state
and 2 bytes in THUMB mode. When a branch instruction is being
executed, the PC holds the destination address.
• It’s used to determine which instruction will be executed next.
• The PC is referred to as an instruction pointer because it stores
the address of the next instruction
When a branch instruction is being executed, the PC holds the
destination address. During execution, PC stores the address of the
current instruction plus 8 (two ARM instructions) in ARM state, and
the current instruction plus 4 (two Thumb instructions) in Thumb(v1)
state. This is different from x86 where PC always points to the next
instruction to be executed.
Register Set: CPSR
•Current Processor Status Register (CPSR) contains
the current status of the processor.
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•This includes various conditional code flags,
Interrupt Status Processor mode and other status
and control information.
•The exception modes also have a saved processor
status register (SPSR), that is used to preserve the
value of CPSR when the associated exception
occurs.
•Because the User and System modes are not
exception modes, there is no SPSR available.
Register Set: SPSR
In the exception modes there is an
additional Saved Processor Status
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register (SPSR) which holds information
on the processor’s state before the
system changed into this mode i.e., the
processor status just before an
exception.
1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
VIT BHOPAL UNIVERSITY ARM Operating Modes
VIT BHOPAL UNIVERSITY ARM Operating Modes
https://www.youtube.com/watch?v=Usjax7H0xuA
VIT BHOPAL UNIVERSITY ARM Operating Modes
VIT BHOPAL UNIVERSITY ARM Operating Modes
1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
ARM Core Dataflow Model
1. 32 bit processor implemented
either Von Neumann or Harvard
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architecture
2. Instructions have two source
registers [Rn, Rm] and one
destination register [Rd]
3. Rm is used to shift data before
processing by ALU. It is the need
in many ARM instructions
4. MAC will do basic summation
operations
https://www.youtube.com/watch?v=lZMLdyIiIZs
1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
https://www.youtube.com/watch?v=HFNJ967S7cg
VIT BHOPAL UNIVERSITY ARM7 uses 3 stage pipeline
VIT BHOPAL UNIVERSITY 3 stage pipeline
VIT BHOPAL UNIVERSITY 5 stage pipeline
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1. Necessity of RISC Processor
2. ARM processor fundamentals
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3. ARM7TDMI features
4. Register set
5. Operational Mode
6. ARM Core Data Flow Model
7. Pipelining: ARM 3 stage Pipeline, ARM 5
stage Pipeline
8. Pipeline Hazards
https://www.youtube.com/watch?v=HFNJ967S7cg
VIT BHOPAL UNIVERSITY Pipeline Hazards
VIT BHOPAL UNIVERSITY Pipeline Hazards: Data Hazards
1. RAW [Actual / True dependency]
2. WAW [Output dependency]
3. WAR [Anti dependency]
4. RAR
Pipeline Hazards: Data Hazards
1. Read after Write (RAW): True dependency or Flow
dependency are other terms for RAW. It happens
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when a value generated by one instruction is
required by another instruction.
For example:
These hazards need the use of stalls.
ADD R1, — , — ;
SUB — , R1, — ;
Pipeline Hazards: Data Hazards
2. Write after Write (WAW): Output dependency is
sometimes known as WAW. These hazards arise when
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an instruction’s output register is used for writing after
it has been written by a previous instruction.
For example:
ADD R1, — , — ;
SUB R1, — , — ;
Pipeline Hazards: Data Hazards
3. Write after Read (WAR): Anti-dependency is often
known as WAR. These hazards arise when an
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instruction’s output register is used after it has been
read by a previous instruction.
For example:
ADD — , R1, — ;
SUB R1, — , — ;
Pipeline Hazards: Data Hazards
4. Read after Read (RAR): Read after Read (RAR): When
two instructions read from the same register, RAR
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occurs.
For example:
ADD — , R1, — ;
SUB — , R1, — ;
Handling Data Hazards
1) Forwarding: It modifies the pipeline by adding special
circuitry. This method works because the required values
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take less time to go via a wire than a pipeline segment does
to compute its result.
[https://www.youtube.com/watch?v=3bkgwvfQSNQ]
2) Code Reordering: Reordering code necessitates the
use of specialized software. A hardware-dependent compiler
is the name for this type of software.
3) Stall Insertion: This method inserts one or more
installs (no-op instructions) into the pipeline, delaying
execution of the current instruction until the required
operand is written to the register file. However, this method
reduces pipeline efficiency and throughput.
VIT BHOPAL UNIVERSITY Handling Data Hazards – Data Forwarding
VIT BHOPAL UNIVERSITY Handling Data Hazards – Data Forwarding
Pipeline Hazards: Control Hazards
Just an example
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https://www.youtube.com/watch?v=OTvi_NCQw2Y
VIT BHOPAL UNIVERSITY Pipeline Hazards: Control Hazards
VIT BHOPAL UNIVERSITY Handling Control Hazards
• Stall – the moment branch instruction occurs then no
more further instruction fetch wont be there
• Prediction – in counter type examples
• Dynamic branch prediction – use of branch table
buffer
Pipeline Hazards: Structural Hazards
Attempt to use same hardware by different stages at
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the same time slot
VIT BHOPAL UNIVERSITY Handling Structural Hazards
• Stall
• Pipeline hardware resource
• Replicate resources
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