eB Half adder i=nal te 4 1 i ee A half adder is a loqigah Jogic./circult +thak | performs binary addition of +wo single - bit * | binary numberg. ee +dt has +o Inputs Avond B and two outputs, — SUM and CARRY. / | «The Sum output Is the least Significant bi} | (tS8) of the result, while -thes CARRY. outpuk is _the, most significant: bit CMSB) of. the result. | js the halfs adder can be implemented using | bosie gates such as XOR aod AND. gases. Je Half adder is the simplest of all adder Circuits . | HalR adder is a Combinational arithmetic circuit thot adds +wo pumbens and produces 4 Sum bit (8) and carry bit CO) both as output. |ethe addition of 2 bits is done using @ |eombination circuit called a Half adder. | Truth Table : « Here ,we can use the k- Map (ka rnaugh Map), a method for simplifying Boolean algebra , to determine equatong of the sum bit (s)and the ouput carry bit (¢') OF the half adder circuit. The k-map for half adder circuit is chownT { T. SSA'R +H AB’ AAS | [mR Block Diagram: 29): fesreh ar fs Hane iB -4 [sland m Bott ‘Ad aon ai aioe é = (. Block” Biagina) # ceil Ep ioa echt = 4 Circuit Diagram) r * Application of Hath Adder :- jt. Counters 3» Half atders ate utilized in counters +e augment the count by one - ~__|asMultiplexerc ond sdemultiplexers : Halk addecs y. vare atilized in multiplesecs and fnbos demultiplexers +© Choose and course EE information . 8.Encoder and Decoder circuits : Half adders ane o utilreed ain’ encoder and decoderarr an have a convey “input ,whith restricha ie Value _ ip more mind Pegaliog expansion +o taske A convey input impoctant to per Porm | OF ‘route bit pines and ‘to’ chal pu Laddes -together« {| id 14 ‘ $ [the balt-adder is used to add only +wo numbers , 10 overcome) this problem, 4be full adder was developed « J a z the fail adden is used +o add! Phreeli=bin (binan] numbers A+s® and Carry C'e - “5 «the full adder bas +bree input iafals and +30 __ output Stakes’ J.e+) sum and. 200 0H * Block Ologram: - sot | | on 4— | Cin’ | Talock Diagram, teen ly truth Table: \ / Tapas Output 5 Cin Som Carr is 7 0 a Ca vied VE oem! ean 6 Geece ° \ 0 0 fig c0 ‘os J fs. 0 6 l oO 1 o ! oO | ——=oo eee Tr ETT ¢ f — CA tatse f hone eoitoul | s e bill ah NCEP = | nha or Loum of proaues) Forwiean bar ovie- “Tined with the help OF Ketnap age conce \ Sa asC-In AU I ig 2g Halr-adder Tor HalF - add er Implementaron oF full Adderiusing NAND gates : Advantages of Full Adder = 1 -Flesei bility i 4 fullesnake can add three Fi informant on -blks » Making, i+ more + Fleslble than-q half vipers 2+ can likewise be utilized to add mulh’- bit numbers by binding different full adders +together. 2. Speed : the ful) snake works at an extrem) Fast» Making i+ reasonable for use in ropid computerized circuits.SA Carny! info : The Aull viper bas a convey input, ind which permtts I+ to perRorm exponsion of multi-bit numb ers and +0 chain different adders a re “together. = # Disadvantage oF “full Adder : ‘the fall snalee is more Mind | 1 Complesuty : boggling than _a half \viperiand requires <1 _palvomore! spants. jike x0R,AND OF poten _ Hally entrywaye Jt is like wise more aaa ae plomeetacun a and flan. S + } * Applicaton oF _full Adder + arate 1. Aciinmedic Teindaree-H Fah adders! are u Airc =i math circuits to add_ twofold numbers. At | the alata diF Fer:s A_rmultiplescer is a combinational pl binatto elreatt that hay 20 input lines and single ouspas ine, 2 Simply, the multiplexer if Q_MplH = input and le- ouypuk eombinaHonal’ circuit « athe bina’ apy information ig received from the of topat fines and ditected to the output ine, 00 | the basis of the values of the selection Atnes, one of qese data. foputs witl be connected to the Output. moulsiplester is also Heated ae Mus.” 2x! mur igleer, d=3 real iinM 1%PAGE No ome | 7 7 = So's hot GO. AV . Logica) Ctreal+ LO ENA mAyT or Bl risscala edo the 4xb mutiplesten » the four inputs, Te AOA Vy, Am Hon tines , i.e. So and 61 and. they Yon the basis of thence: inpats +hat are presente Truth Table : Input Output 8) So iY 3 oO 0 Ao 4 ia oO | Al ! 0 Ar I “sa “As | [the logica} erepression of the term ¥ Is as: oy 2S1'So' Ag + Si'SoAr +81 80'A24 S180 As. |e Logica) Circult ¢ $i 80 ese H# Ox) Multiplexer :— eIn the 8 to! multiplexer, there are tota) eight inputs ,t-ey AoiA! sA2 ,AS,A4,A5, Ac and Az, B SelecHop lines, le Gor Si and 82 and gingle ouiput fe» On the bashes of the combination oF input that! are ‘presents ab the Selection lines 6S! and S* , one of these ibpae are connected +6 the souls 4 BA cs? bh -bdo! dtoste Circuit: OF 8tol Moxy) >PSS SSRIS pS a De- multiplexer oA De muldiplescer (9 @ Combinatonal ‘clrcuty that has only 4 input Ifpe and 24 oulpuk tines. ir je Gimply scthe multpleser i¢ a Single -input and multi output eombinarional Circuit « * ‘the information is feceived from the single input lines \and (directed te the oudrpur line. «De- mult’ plener is opposite to the multi-plesepr, « De - multipleser-/s algo treated a3 Dé~imux. He 1 xX2~De -Multpleaer :— en the 16 bed martiplesrer, there are vonly two outpuis , ey Yo and yi sf res So pang! ¢ ingle output Selection Jines, ett © Block Diggrarn eeCireui+ Diagram : ne j = #ixd De= mulhHpleserz= | jeZp t +0 Bo \De= muHiplescer y there are total of eight outputs’, te» ‘fo. Wye ys. Yrs .Je and 2.3 Selection tines, ive» Go Siand ¢1 and single input: fe. A» On de basis oF +he combi- nation of inputs which ate present at the selection fines 69,9! and 32 the inpuk wil be tonnected to ond of these. outpuy. 2 Block Diagram: x <Inpotg oo) So: 8 i Sime RI rossi ) Ot) ae, ae 0 090 04909 Or of boa. Ong Bi aOitn Ois19 Pai 0 suo ah 90» MOI Fe poi Otyabig Oodl0.2¢ ashe : © Locsin Oat OiaO4 3 s+ oan dstiad) s910140 9A - O96 A! 9096 Ode O19 100)Saactmeath Encoder ?— gidar dtny v the ‘combinaHiona) cireushs Jhat change tbe. bin ary |ethe binary information is passed in the form Information [nto .N output tines are kno Encoder. * weer O é 6 of ON input Itnes..The output Iines define the N-bit code for +he binary toformation : Je 3h Simple words, +he Encoder performs’ thé reverse | operation of) the Decoder. ————t 2h inpud [nes | N output [ines | as cat Encoder 3 = + : ee fi rer #* 440 2 i'ne Encoder : +12 a ailamialalad + In 4402 Iine encoder ,there are total -of Four inputs , te. Yor! sa and ya, and #wo Outputs, Hew Ao and Ai. 3n 4- input Ines 5002 input - line is ses to 4rue aba Hme to get the Pespechi< | binary code jin the output aide, © Block Diagram + j lal ¥i—— >] a Re | fa ANE ] cam Ao 6. je Truth “table $ Topurs M0[[abe logical expression oF the term Ao one AP] Al =Ys + Yo . J | Fb aa ya : : i 2 E ! |e Logica) Clecuit - a | Yeo snail - J Al Toys . —_—— ) é 9 #8 +o Zi line Encoder :— ~ the 8408 lines Encoder isxat80 Known os Octal 4o Binary Fncoder.sn.3 te 3 ile encoder, there is a total of eight. inputs» ces Yo.Y) oN2278,V45 YesYe and yx and three outpais, i.e Ao, A1 and Az. In 8 input lines ,one input -line is vse} dotrue at a Hime +o ger the cespecHve = binary -code vin the outpur_ cide . Lt pi « Block Diogram ¢ sicale Truth Table: > Inpurs Ve Ye Ys Ya Ys Ya Yi You Ae = Ar Ao o 8 eo 6 f OF Mis deg of 6 6 0:80) oe A200 16 Oe Wo) oOo AA [ap £10 ho. et o Oe OM Oly peeaomembom BY OE HPO: Way MED FO sien o i 6 0) oe 05 0 | 8 ! o A» oO 0 0 ON ets fa 8 ost ota so gt ia} expression: of the term fos Mi end As) sabAatb apy RYE 8 SHYESHEPBIGT pinais ewe, aXe = Wadsye P¥schygiipis 32 lots pape ® Mi es ft “ye Circuit «piagram> asYrwVS > Vs LYN Ys > 2 a| IL | I 1 ASS ya tye b An- Ay y, {i Year yes Yow y> SOSig SyE ae ete Yat ian we EI) Sy gece) Sey Sty ae a ; je Clrewit ofagromt- = Yo yi Ya Ws Wa We yc Vo Yeas | a+ Tol P.these systems: are digital systems . 2s aa - Encoders are ‘Oumber into JS 40 Pperforr very easy +o use i Used) to. conve the binary num <0 binary | | addition, Subtraction 2 UP t 6__# De~coder:- E |e The combinattonal circuit that change +he binary Information ints 2% ouput tine iS known ag L Decoders. é ethe binary information is passed in the form oF N input fines. the output fines defines 4he 2N- |b code “forthe binary information. | -Tn simple words, the Decoder perform’ the reverce |-operation of the Encoder. t | Reto2? 7 | Decader: 2N oudpuls HK 2+ Feline Decoder :- é «Ip the 2 te 4 Sine decoder.+there is a total of +hree inputs, tery Ao, and-Avand © ard four outpuss » TOeryo, Yrs¥ao and ys .fer-each eomb- ination of inputs, when the» enable »'B».18 set to 4, 6ne of these four) output Will bet , is Block Scr 2 S ON es Soh tugiwo eTraib table * — Enable Input © 1 42 i Output iE Ai © Ao as $e Yi Ve | a eo ° a) ete Ope ne a ane i FS c Cas cana ni Sanam seem 1 be fi y ! 0 qLap HE» Weed wat | Logica) Circoit = # gto bi =, the 24ers Wine vdecoder “he Othal Decoder. 4 + in a 340 8 line decoder, +here total oF oukpude » [eos JosYo¥e ve, Ya as 96 and V4 and Aree oulpule «128>-KOWAT and Uae meatal pos op enable Input ‘2’. » ‘41 | Truth -4able i= . : Enable || Input j output E AS FA WO ys Ye Ys wa ler ye 2% To o. ot oe, 0 0 0 << en) » 20, 0 Hiv] On 0 Ope Oe Ore reed” 7 Of ol A 1 UNPPORRER Ga tee plet oer Guede Tac 0 1 Wt Ws) Oi 0 “e000! Ob Ar bof ticd i ° l t Ontos Oregabee--ParAn-20~40 0 t ev aomearreth toe one oaAn.t0 cl 0) lol 0 1 a me G0 Oe ode | 0, 0 ! ! WR sf =0j 0+ 0-7 0 a ea med) oy - be feo) Yo = AoA Ae’ 1 ye Apc a's Aa = ye = Ab wite AZ? Yale AsmAiuA2! Y= Aowtar Ae YS = Ap. Avi Aa Ye = AO’. by he Na = Ao Ars Aa. Az Ai Ao| SR Flip= Flop : ' \ othe SR filp Flop! is_gi 4- bit heriay bistable device having +wo Inputs 5 fey SET and RESET. ie The SET inpus 's’se+ theidevice an Ate the ouspud 45'and he! RESET vinpar #R» reseb the device or produce) +he ourpuy! ox 2 «the Setiiand RESET foput “are lobeled. eee and R tespectively 1 agh 105 “and. fe BR Flip-Flop aittoar te "ser - Reset Pui Flop. «the teget inpur is used +o get back ‘the lip - flop to its origina) gtate from the current State with an oudpur @), this outpub depends tons the wseh reser condiHons , wabihs ts efther at the logre vevef "0". or M1. p 10k O)..21.¢ * Block Blog carnzh pando oi +si4ined.as —State $ R Q = *@told — ail) a Ser 1 0 0 e ' \ © l { | Reser: SOV ey abe ly bly 1/0} ° ) J Lk palt@d Iovalid 0 0 I { 14 from +the above ‘truth cable ,we cam gee that when iseh's) and: Reset 'p’ Inpuds are set to 4sthe outpaks @ and @) will ettber4 oF 0. LThese outputs. depends on the inpar state Sor LR before the tnput eondiHon epu'tS So ;wben the JOP uss - Ane 4, »the States, oF ihe suiper sremajn unchanged sop o ho2085) augainderss sdf. TK Fii = Elop- = the enable input, ts acon oecurg. [Pqbe Ik Aip- Flop | 4wo drawbacks of SR FP FOP] oe The TkKFIIP-flop {8 One oF the most Flops In digita) ¢ircuits . ethe ak Flip - flop fsa:+ e the D Aip) Flop is ithe most important Hip fop From other clocked +ypesi 7 Lethe Delay flip - Flop wHh am Wer is designed usino a gated OR Fip- Flop with an inverter connected between the jnpuss allowing For a single input Dd Cdata) . NOW OG HW AVD « This single data input, which is labeled as “>” useds in place oF the "set". inpUt and for the = = Te 7S o complementy “Reset” input sthe’ inverter is used. | © Block Siagcam :e || Truth Table : A * clock ) 0. Q le Va, 2) kas Q a | ea a “9 is a 1 mh >>S I 1 oD etn 7 Allp~Ftop , "1" defines sthe term Toggle’. -Ip aR Flip Flop swe. provides only -a-single input called "Toggle "or "Trigger". input -1 avoid an intermediate size /state ociurrence. _sWe can Construct the "7 Pip-Aop' by making changes in the "3k lip Hop’. the."1 Flip Flop” hag) only one input , whichis tonstruced by connecting the input of I Ftip flop . the single input {stalled T~tn-simple word , We coh consttud the "1 Flip Flop” by converting "sk Aip Hop”. BomeHmes the “\t flip: Flap” is | referred $9 as single input 3K Filp Flop’. TeBlock oi sarem ‘[ence / 7 Saar E e Circuit Diagram + we eee L C L 1 a ee 2 0) 2 d to =a alll ie J © te O / Oo ! ) Oo 1 ; ara 5 JinaRegetibostoni pdt taiipainnom ode bd bu 1A register is a tiny, Fast storage memory within he. _céntral ‘pincecsing unit’ (cpu/)” or -the ‘arithmetic toqiic below’ on, 249% | toaccummator Register 91% (2. Program Counter (pc) Regisier +” 3: Genera) «Purpose Registen. yh de 4 instruction Register (iA) i lg Memary Address RegisteriCMAaR) > 1) . San important role in the’ operation ¢- 1 | “There ate different’ -types oF Regicters feted i "¢. Memory Sota! Reqister (Mnr ois 7. Stack Poipter (sp) 2 fi vb $. Floating-Point Register. a fetch ¢ 1 ' a | When we talk about “fetch” in computers, i} ts tike 4 computer going on fetching Pest instruc- dion which has to be ‘followed. The first stage ig where computer, picks his nesck operat loo from, ite memory ~+his allows It to knew what dask hos 46 come a4 the pext moment and provides. Smooth exec uaton . m Decode ¢ When we talk about "decode! tn compaters, users, compuser gebs IngtrucHan eUb OF ond decode fH by Figuring owe WhatWouldi be #he meaning of the instruction shak Was fetched. After getting the InstrucKon [the computen has to decode. i+ 80 as to. know what willbe 143 Qesek course oF acHon as per phat inctrucHon. this,-is on important Siep sdce th Shows: bow. best al. computer cap perforin .a Cente Teer aed piteat onions : : B Execube +The term." executon'! as used .i0 compurers refers. to..an actions or task the» _ computer actually undertakes as specified in | the InstrucHon that .hag - been Fetehed and E decoded - Once “tts hag. under Stood whakis required oF tf , the compumker: carries) out a eéttain _ operaHon. This could sinvolve performing. eaicularions , #ransferring data from 06 focak 4p another ,om accomplishing ony orer stOSk _ defined by the instruction Orovidedinis * aul at =rt Je Actumulator Register : JL 1 oe Memory Hierarchy and the Role oF Registers: [Le Computer systems have asmemory. hierarchy , that includes multiple levels of eee with varying access” gpeeds and eames. =the accumulator acts as a tepital points for arithmetic and Hoqical operations ‘within the cPU. Thi fetthes data from femory and “stores — sintermediate resetlig during talcwlahon se °* e Arithmetic operation: sith as addition ; subtfacHon, mutt pligahions aod division ofien +ake ploce. 'p the accumulator . ethe final result may be- stoted in: the accumulator or trans Ferned to othen registers -or memory Jocations» i 2 ZJProgcam Counter italy Register = the Program Counter is .a special register thak keeps track df the memory address of the oeret ingdruchion to be fetched and executed. AS the Jéepu escecuties each instruction in> seqdence the progam counter is updated: to. inditake ‘the peott . instructions: address in smemory . This | Process Continues: until. the) programs. erc4ecetion jg complet. 4 IpsteucHon | Register CIR)+ the InskrocHion register as the currently Ferched TNstruchioo From memory «2h allows the PU to decode and execute the instruchon “on ~its Opcode andi operandsMemory. Address Register (MAR)? 1 ¥ hei memorg “address regibier Stores the a bs or address oF data -or inotructons +6 be acc CSS t written in memeny . I+ playse a eracial role vin Memon} operations by indicating the location oF cei dalgae Gminoisuction ote. cP to beads to RCesr. i pemony Data Register Cpr) ¢ ithe (Memory Davo Register holds +he actual daiq: Perched From or written toomemony i. When he. CPL retrieves \daka from memory > itis | 4emporarily etored in the /mpR before) peing processed further ‘si paka Register (DR)? | ' | the spate Register fs anierample of actast GHorege place in +he computer wihere ipPornaHon rests whilevall. +bese processes take place of ha same machine. t's a location where j ‘ltransient amounts oF data ane'keph within the SYslens for tempory Usagie tike! pik stops :withio_ shen -performing |calewaHoos er tases or other we Applications of Regsters ister at i]. Arithmeric and Logic ‘Operations the registers av? eottensively used during ‘arithmette dnd (09!¢ il operations in the CPU . they temporarily store 4 aperands 5 Intermedicle results rand flaqs PacihsoH04 quide and. eFR cient calquiations - y | g\-tostruction Pxecudion 2 the Registers play 4 erecta} pole iP the execution of machine insiuD tHons. They hold instructions and deo meedaeitor — immedicale processing ensurin f g_amooth program erecuHon: = aot ;. eo a gj. Memory Addressing i The.tnemony add ress beg iste» (MAR) and memory date reqisten C(MDR)ana involved in memory operations. MAR holds the memory i address being actessed. While MDR Yemporan'ly ‘etores data fetched -from or writer +o memory. _ * Advabtages of Registers ¢ Speed The regrstenrs offer fast access Hmec due +o their proximity to the cPUs erhancing overall sysiero Performance - 2. Dota Processing EFficteney s they enable quick rr data manipulation, reducing the need +o access slower main memory Frequenty . % DisaWantage oF Registers : 1. Limited Capacity + the Registers have _o srnaJ! Sires Pestricting -+the annount oF data they can hold ab qa _tHme- 2. Cost ithe Registers are made from Ffilp- Flops and reguirs more hardware, coptybutirg 4o tbe Overall cost oF the processor: