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 Semiconductor Science and Technology

Semicond. Sci. Technol. 32 (2017) 123004 (20pp) https://doi.org/10.1088/1361-6641/aa9145

Topical Review

Review on analog/radio frequency

performance of advanced silicon MOSFETs
Vikram Passi1,3 and Jean-Pierre Raskin2
1
University of Siegen, School of Science and Technology, Graphene based Nanotechnology, Hölderlinstr.
3, D—57076, Siegen, Germany
2
Université catholique de Louvain, Institute of Information and Communication Technologies Electronics
and Applied Mathematics (ICTEAM), Place du Levant, 3, B-1348, Louvain-la-Neuve, Belgium

E-mail: [email protected]

Received 18 July 2016, revised 26 September 2017

Accepted for publication 5 October 2017
Published 16 November 2017

Abstract
Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor
(MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This
downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for
improved circuit performance and cost reduction and has resulted in tremendous reduction of the
carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is
only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect
transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this
review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is
presented. State-of-the-art devices with very good performance showing low values of drain-
induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early
voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise
characteristic values are reported. The dependence of these FoM on the device gate length is also
shown, helping the readers to understand the trends and challenges faced by shorter CMOS
nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate
architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D
materials are discussed, highlighting the transistor characteristics that are influenced by these
boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin
body buried-oxide and fin field-effect transistors are also presented. The authors would like to
mention that despite extensive research carried out in the semiconductor industry, silicon-based
MOSFET will continue to be the driving force in the foreseeable future.
Keywords: analog and radio-frequency figures of merit, digital figures of merit, multiple gate
field effect transistor, ultra-thin body buried-oxide, III-V and two-dimensional channel field
effect transistor
(Some figures may appear in colour only in the online journal)

1. Introduction

The patent of the concept of field-effect transistor (FET) in

1930 by Lilienfeld [1] and practical implementation on sili-
3 con/silicon-dioxide in 1960 by Kahng and Atalla [2], have
Present address: AMO GmbH, Otto-Blumenthal-Str., 2552074 Aachen,
Germany led to the growth of FET to be the most important device of

0268-1242/17/123004+20$33.00 1 © 2017 IOP Publishing Ltd Printed in the UK

Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

essentially governed by the scaling criteria proposed by

Dennard [12]. Scaling or ‘downscaling’ is the process of
reducing device dimensions, while trying to maintain constant
electrical characteristics. By simply following the scaling
rules proposed by Dennard, led to a significant reduction of
the gate length from the 100 μm down to the 100 nm regime
without much difficulty. However, below 100 nm, maintain-
ing the electrostatic integrity of the device became a major
challenge leading to major problems, some including the
short-channel effects (SCE), drain-induced barrier lowering
and increased gate leakage [13]. The main problem associated
with MOSFET downscaling is the direct and indirect
dependence of electrical characteristics on controllable phy-
sical parameters, which cause non-ideal effects that hinder the
performance and power consumption characteristics of the
device. It has been observed that various scaling methods are
Figure 1. International Technology Roadmap for Semiconduc-
required to replicate long-channel behavior in a short-channel
tors (ITRS). device and hence no single scaling method provides an exact
solution. Consequently, designing a device requires much
the semiconductor industry. For the past seven decades, iteration and experience on the part of the designer.
progress in this field has followed an exponential behavior The observation made by Gordon Moore back in the
that we all know today as Moore’s law [3]. Although today’s 1960s was a forecast on the number of transistors that can be
metal-oxide-semiconductor field-effect transistor (MOSFET) integrated into a microchip, which has remained almost
has seen so many changes in its life cycle, from single-gate unchanged until now [3]. The increase in the number of
planar to multiple-gate non-planar MOSFET, it has continued transistors from a mere 2300 in 1971 to 7.2 billion in 2016,
and will continue to be the driving force in the semiconductor attributed to the aggressive downscaling, is the most impor-
industry in the foreseeable future. tant feature of Moore’s law. Indeed, the doubling of the
Complementary metal-oxide-semiconductor (CMOS) is number of components per chip now follows a deviated path;
one of the most suitable technologies to integrate radio fre- 18 months instead of the 12 months first observed by Gordon
quency (RF) circuits with analog and base-band digital cir- Moore. The other two key features associated with Moore’s
cuits. Tremendous research effort has been dedicated to RF law are cost (minimizing production costs and maximizing
CMOS, driven by system-on-chip (SoC), using inexpensive profits) and performance factor (increasing speed and tran-
single-chip transceivers, including both at the base-band and sistor density per chip) [14].
the RF front ends. Will these exponential projections be The ITRS is the assessment of the semiconductor
available in real-time environment or will physical limits wipe industry’s future technology requirements and presents a
them out? Many reviews have been written about the current guideline that helps the semiconductor industry to transform
state and future prospects of MOSFETs [4–7], but mainly the observation made by Gordon Moore into reality. The
focussing on digital applications. In this review paper, we try objective of the ITRS is to ensure cost-effective advance-
to address some of the most important digital, analog and RF ments in the performance of the integrated circuit (IC) and
figures of merit (FoM) showing their dependence on the gate products and applications that employ such MOSFETs,
length and highlighting the state-of-the-art values of different thereby ensuring the continued health and success of the
FoM that have been reported so far, based on silicon semiconductor industry [15]. The race to follow Moore’s law
technology. of scaling, and to benefit from the functional density and
Figure 1 shows the downscaling of the most important power management together with high performance comes at
physical (gate length; Lg and gate oxide; Tox) and electrical a cost; increased leakage current, difficulty in increasing on-
parameters (supply voltage; Vdd) taken from the International current to off-current ratio (ION/IOFF), variation of different
Technology Roadmap for Semiconductors (ITRS) for the parameters, reliability, yield, increase in manufacturing costs,
time period from 2005–2020. The values shown in the to name a few [16].
graph are summarized from ITRS 2007, 2009, 2011 and In this article, the authors try to address some of the main
2013, respectively [8–11]. FoM such as drain-induced barrier lowering, sub-threshold
swing, gate transconductance, Early voltage, minimum noise
figure, low-frequency noise, current gain cut-off frequency
and maximum oscillation frequency, as guided by the ITRS.
2. Scaling overview A brief introduction to the above-mentioned FoM followed
by graphs showing their dependence on the gate length with
The growth of the CMOS industry has been triggered largely equations and schematics is presented. The values shown in
by the technological innovations that have enabled steady the graphs are taken from the literature for MOSFETs with
downscaling of MOSFET dimensions, which has been gate length less than 1 μm, and state-of-the-art points are

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Table 1. Predicted values of RF mixed signal FoM of merit from

ITRS [8]. The peak cut-off frequency (Peak Ft*) extrapolated from
40 GHz with a slope of 20 dB dec–1, peak maximum oscillation
frequency (Peak Fmax # ) measured from unilateral gain extrapolated
from 40 GHz with a slope of 20 dB dec–1 and minimum noise figure
(NFmin) values.

Year Frequency (GHz) NFmin (dB)

Peak Ft* Peak Fmax #
2005 120 200 0.33
2006 140 220 0.3
2007 170 200 0.25
2008 200 240 0.22
2009 240 290 0.2
2010 240 290 <0.2
Figure 2. Schematic showing the increase in the depletion width 2011 280 340 <0.2
below the drain (encroachment under the gate), which is a result of 2012 310 380 <0.2
increasing drain voltage in the case of n-type MOSFET. Dotted line 2013 340 420 <0.2
represents the penetration of the depletion width below the gate. 2014 400 510 <0.2
2015 480 610 <0.2
highlighted (by encircling them) giving a brief insight into 2016 520 670 <0.2
their fabrication technology, device architecture and physical 2017 570 740 <0.2
parameters. The graphs show four different families of points; 2018 630 820 <0.2
black squares which represent planar MOSFETs fabricated 2019 680 900 <0.2
on bulk or silicon-on-insulator (SOI) substrates, green dia- 2020 750 990 <0.2
monds which represent non-planar MOSFETs (double, tri,
fin field-effect transistors (FinFET), Pi-gate, Omega-gate,
gate-all-around) fabricated on bulk or SOI substrates, blue threshold voltage with drain voltage at constant normalized
triangles which represent both planar and non-planar MOS- drain current [20, 21] usually taken at 0.1 μA.
FETs fabricated on either bulk or SOI substrates but are based The expression to calculate the DIBL is given by,
on high-k dielectric and metal gates, and red circles which
DVTH (V - VTH2)
represent MOSFETs implemented with strain/stressor DIBL = = TH1 , (1 )
technologies; respectively. Where applicable, a line is drawn DVD (VD1 - VD2 )
which shows the theoretical relationship between the FoM
where VTH1 and VTH2 are the threshold voltages at drain
and gate length.
voltages VD1 and VD2, respectively.
The main FoM discussed in the ITRS for RF and analog/
Figure 3 shows the plot of the DIBL versus gate length
mixed signal technologies have been summarized in table 1.
for n- and p-channel MOSFETs, respectively. The lowest
DIBL value of 11 mV V−1 for deep-submicron n-channel
MOSFET is obtained for a device with gate length 25 nm
3. Digital FOM [22], presenting an omega gate (which has the closest
resemblance to the gate-all-around structure) with a gate-
oxide thickness of 1.7 nm. This device architecture is scal-
3.1. Drain-induced barrier lowering
able, based on the FinFET manufacturing process and the
Drain-induced barrier lowering (DIBL) was a term introduced omega shape of the gate results in better channel control.
by Ronald R. Troutman [17], which primarily defines the For p-channel MOSFET, the lowest value of DIBL is
reduction of the threshold voltage of a transistor at higher 14 mV V−1 for a gate length of 5 nm [23]. The device
drain voltages. The origin of the threshold voltage decrease architecture demonstrated here is FinFET with an additional
can be understood as a consequence of charge neutrality [18]. hydrogen annealing step to form a truncated cylinder-shaped
For a long-channel device, the application of a drain bias nanowire body.
does not modify the potential barrier of the source junction. Lower values of the DIBL indicate better control of the
However, in a short-channel device, the potential barrier at channel by the applied gate bias, which can be achieved by
the source can be reduced by a value depending on the optimization techniques such as increased channel doping
applied drain bias. This reduction of the potential barrier [24], elevated source-drain [25], thin silicon-body [26] and
reduces the threshold voltage [19]. As the gate length reduces, thin buried-oxide [27] of the SOI film, together with the
the gate loses control of the depletion region underneath due implementation of multiple-gate architecture [28, 29]. An
to the encroachment from the drain junction, represented by increase in DIBL occurs in devices where the gate length is
the dotted line below the drain in figure 2. scaled without proper scaling of other dimensions. The plots
The most commonly used method to extract the DIBL is shown in figure 3 present DIBL values limited to
the constant-current method based on the shift of the 300 mV V−1 (arbitrary limit) in order to have clarity in the

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 3. DIBL variation with gate length for (a) n-channel and (b) p-channel MOSFETs, respectively. Black square symbols are values for
planar devices on bulk or SOI substrates, green diamond symbols are values for non-planar devices on bulk or SOI substrates, blue triangle
symbols are devices based on high-k dielectric and metal gates, and red circles represent values of devices fabricated using strain/stressor
technologies, respectively.

Figure 4. Sub-threshold swing variation with gate length for (a) n-channel and (b) p-channel MOSFET, respectively. Black square symbols
are values for planar devices on bulk or SOI substrates, green diamond symbols are values for non-planar devices on bulk or SOI substrates,
blue triangle symbols are devices based on high-k dielectric and metal gates, and red circles represent values of devices fabricated using
strain/stressor technologies, respectively.

graphs. The values beyond that arbitrary limit indicate that given by
either the device architecture or the fabrication process or
dVG
both were not adequately optimized. S= (2 )
d log (ID )

The theoretical best value of sub-threshold swing (S) is

3.2. Sub-threshold swing
60 mV/dec at a temperature of 300 K, calculated from the
The drain current depends exponentially on the gate and drain equation
voltages in weak inversion mode or the sub-threshold regime. kB T
In simple terms, it is the change in gate voltage (VG) required S= ln (10) (3 )
q
to produce a decade change in drain current (ID) [30] and is
Typical bulk MOS transistors have sub-threshold swing value

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 5. Transconductance variation with gate length for (a) n-channel and (b) p-channel MOSFET, respectively. Black square symbols are
values for planar devices on bulk or SOI substrates, green diamond symbols are values for non-planar devices on bulk or SOI substrates, blue
triangle symbols are devices based on high-k dielectric and metal gates, and red circles represent values of devices fabricated using strain/
stressor technologies, respectively.

around 80 mV/dec [7]. The smaller the value, the more considered as strategic technologies to boost transistor
efficient and rapid is the switching of the device. performances.
Figure 4 shows the variation of sub-threshold swing
versus gate length for n- and p-channel MOSFETs, respec-
4. Analog FOM
tively. A dashed line drawn at 60 mV/dec represents the
theoretical value of the minimum sub-threshold swing for
For analog applications, MOSFET working usually in the
silicon MOSFETs at room temperature. For the shortest gate
saturation region is considered. The drain current versus gate
length of 10 nm, a sub-threshold swing value of 67 mV/dec is
voltage characteristics are measured at various drain voltages
obtained for an n-channel MOSFET [31] and a value of
from linear to saturation regime, followed by the drain current
63 mV/dec is obtained for a p-channel MOSFET with a gate
versus drain voltage characteristics, which are measured at
length of 5 nm [23].
varying gate voltages to cover all the possible operation
The devices which exhibit such low values of sub-
regimes i.e. weak, moderate and strong inversion.
threshold swing are ultra-thin body devices fabricated on SOI
substrate incorporating strain engineering in the form of
4.1. Gate transconductance
strained SOI substrate together with high-k dielectric and
metal gates for the n-channel MOSFET [31]. For the The gate transconductance (Gm) hereafter referred to as
p-channel device a FinFET architecture is implemented transconductance of a transistor is the current drive of the
together with hydrogen annealing to obtain a truncated transistor, which is a measure of the effective control of the
cylinder-shaped nanowire body [23]. A combination of ultra- drain current by the gate voltage. It is usually measured at the
thin body (2.5 nm), nanowire channel together with high-k maximum operational drain voltage (VD) of the node and gate
dielectric/metal gates and non-planar gate architecture overdrive VGs−VTH=0.2 V [35]. At this overdrive, the
resulted in the lowest values of swing and good transistor transistor is in strong inversion with Gm/ID around 10 V−1
performances, the best reported so far, to the authors’ and as a result a good compromise between speed and power
knowledge. consumption can be obtained around this bias point.
It is well acknowledged that the main advantage of the A simple expression to measure Gm in saturation region,
fully depleted SOI (FD-SOI) MOSFET when compared with is given by
other technologies is the steep sub-threshold swing. However,
Gm = WmC OX (VG - VTH ) Lg, (4 )
the value of the swing tends to increase with the reduction of
gate length, which can be controlled by key parameters such where W is the width of the transistor, μ is the mobility of the
as thickness of the active SOI layer [32], reducing the charge carriers, Cox is the oxide capacitance, and VG and VTH
thickness of the buried-oxide [33] and by fabricating a buried are the gate and the threshold voltages, respectively.
layer [34]. Most of the above-mentioned technology The maximum transconductance (Gm_max) can be trans-
enhancement techniques have been implemented in the lated into how fast the transistor operates and how much gain
devices highlighted in figure 4. These techniques are it can provide.

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 5 shows the variation of the transconductance as a a lot of literature data on VEA for the analog performance of
function of gate length for n- and p-channel devices, MOSFETs.
respectively. The highest value of transconductance for Very high values of VEA have been reported for devices
n-channel MOSFET with gate length of 29 nm is implementing FinFET architecture [39], which is attributed to
1840 mS mm−1 and for a p-channel MOSFET with gate improved control of the gate and a strong indication of
length of 31 nm is 1600 mS mm−1, respectively [36]. Both the volume inversion condition in narrow fins [40].
devices are fabricated on 45 nm SOI CMOS technology fea- It can be seen from figure 6(b) that an increase in VEA is
turing 1.16 nm gate oxide together with the integration of observed in devices that are fabricated with no-HALO
multiple advanced strain and activation techniques including implantation [40–42]. The pocket implant results in a barrier
enhanced dual-stress liner (DSL), advanced epitaxial silicon- at both ends of the channel and these barriers inhibit current
germanium, stress memorization and advanced metal flow. Increase of the drain voltage results in reducing the
annealing. Further details on the fabrication can be found barrier at the drain end of the transistor and an increase in the
in [36]. drain-source current. The VEA is limited, not by the channel
The inset in figure 5 shows a trend line drawn high- length modulation as in the case of traditional MOSFETs, but
lighting the dependence of gate transconductance on the gate by the modulation of the barrier near the drain [43]. The
length. From equation (4), the gate transconductance is benefits of implementing FinFET architecture also include
inversely proportional to the gate length, but in reality, slight improved gate control and the manifestation of volume
degradation is observed. The gate transconductance is inver- inversion for narrow FinFETs [40]. Here, it has to be pointed
sely proportional to (gate length)0.8, i.e. Gm α 1 /Lg 0.8. This out that FinFET architecture has not only shown improved
degradation is attributed to the scattering in the data points of analog but improved digital performance. The lowest value of
not optimized devices and/or processes, impact of source/ drain-induced barrier lowering and sub-threshold swing
drain resistances and velocity saturation. reported in the above section is obtained for FinFET
Much of the improvement in transconductance is architecture.
obtained by scaling the gate length and the gate-oxide
thickness, although there are other problems encountered. In
4.3. Low-frequency noise
the case of devices with smaller gate lengths, SCE deteriorate
the transconductance and the use of an ultra-thin gate-oxide Electrical noise can be defined as a randomly time-fluctuating
results in a tunneling problem and as a consequence larger electrical signal. The origin of noise can be categorized as (i)
gate-current leakage. external noise from adjacent circuits, AC power lines, radio
transmitters or (ii) internal random fluctuations governing
4.2. Early voltage electron transport [44]. Being random in nature, noise cannot
be completely eliminated and limits the accuracy of mea-
The Early voltage (VEA), named after James Early (who
surements and sets a lower limit on how small a signal can be
pioneered the bipolar transistor), was initially used to model
detected and processed [12, 45]. Although external noise can
the small-signal emitter-collector resistance in bipolar tran-
often be eliminated by appropriate shielding, filtering and
sistors [37]. In MOSFETs, it is the voltage at which the
choosing optimized layout designs, true noise can only be
tangent to the ID-VD characteristics in saturation crosses the
reduced by the proper design of devices and circuits [44]. A
horizontal axis [37, 38].
schematic diagram of the power spectral density (PSD) for the
There are two methods used to calculate the VEA; (i)
excess noise at low frequency is shown in figure 7.
extrapolate the drain current until it intersects the VD, or (ii)
Extremely scaled CMOS devices suffer from time-
dividing the ID by the output conductance (Gd) at a specific
dependent variability that exists due to the presence of a few
VG or VD, as shown in equation (5) [37].
stochastically behaving defects or traps in the gate
ID dVD oxide [47, 48].
VEA » » . ID (5 ) The noise associated with the capture (or emission) of
Gd dID
charge carriers from (or into) the channel by defects is mainly
The latter is the most preferred method to extract VEA since it dominated by the drain current and is called random
relates to the output conductance and highlights its depend- telegraph noise (RTN). The total drain current of a MOSFET
ence on the gate length. is the sum of both the deterministic DC component and the
Typical values of VEA in MOSFET’s range from randomly time-fluctuating quantity, both of which depend on
10–200 V depending on the gate length of the device. Since the applied bias. In mathematical terms, this can be expressed
MOSFETs with larger gate lengths are less affected by gate as
length modulation, VEA values are larger.
Figure 6(a) shows the variation of VEA as a function of IDS (VGS, VDS, t ) = ID,ref (VGS, VDS) + D IDS (VGS, VDS, t ) ,
gate length for single-gate (filled symbols) and multi-gate (6 )
technologies (unfilled symbols), respectively. Figure 6(b)
shows the VEA variation for MOSFETs with halo implantation where D IDS (t ) is the randomly fluctuating drain-source cur-
(filled symbols) and without halo implantation (unfilled rent, VGS and VDS are the gate-source and drain-source vol-
symbols), respectively. It must be noted here that there is not tages, respectively. The fluctuating current depends on carrier

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 6. Early voltage variation with gate length for different technologies. (a) Early voltage for single-gate (black square symbols) and
multi-gate transistors (green diamond symbols), respectively. (b) Filled symbols represent Early voltage values where ‘HALO’ implantation
was used during the fabrication and unfilled symbols represent values where ‘no-HALO’ implantation was implemented. Black squares are
for bulk, red diamonds for partially depleted and green triangles are for fully depleted technologies, respectively.

observed by J. B. Johnson [49] and theoretically explained by

H. Nyquist [50].
The second class of noise is called shot noise and is
generated when charge carriers cross the barrier indepen-
dently and at random. It is a Poisson process and was first
discovered by Walter Schottky [51].
The third class of noise is called the G-R noise. As the
name suggests, it originates from traps that randomly capture
and emit charge carriers, thereby causing fluctuations in the
number of carriers that are available for the transport of
electric current. If charges are trapped, these can also cause
fluctuations in carrier mobility, diffusion coefficient, electric
field, barrier height, etc [44].
A special type of G-R noise is the random-telegraph-
signal noise, also called burst or popcorn noise. This is dis-
played as discrete switching events in the time domain, as
shown in figures 1–4 in [44].
The 1/f noise, also called flicker noise is the name
assigned to fluctuations with a PSD proportional to 1/f γ with
γ close to 1. It is generally expressed as
Figure 7. PSD for low-frequency noise and white noise plotted
versus frequency. Excess noise above the white noise floor is called SI = KI b f g (8 )
low-frequency noise and may consist of either 1/f noise or
generation-recombination (G-R) noise or a combination of both. where K is a constant, and β is a current exponent.
Redrawn with permission from [46]. The origin of the 1/f noise and the fluctuations arising
due to either carrier number or mobility has been long debated
and so far the dominating factor is not evident. It is very likely
number and carrier velocity and can be generally expressed as that both factors contribute and which source dominates
would depend on the material, type of device and operating
DIDS = fn (DN ) + fn (DV ) , (7 )
conditions, and for an in-depth reading [44, 46, 52, 53] are
where, DN is the carrier number and DV is the carrier highly recommended.
velocity component, respectively, and the velocity component Low-frequency noise measurements can be used as a
can be rewritten as V = m. E [44]. non-destructive diagnostic tool that leads to the identification
The first type of noise called thermal noise stems from of traps in the channel and the gate oxide, thus giving
the random thermal motion of electrons in a material and is information on the quality of the transistors fabrication. Low-
also called Nyquist–Johnson noise. It was experimentally frequency noise characterization has been intensively used to

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 8. Small-signal equivalent FET circuit comprising an intrinsic transistor with the gate-source capacitance Cgs, the charging resistance
Ri,, the gate-drain capacitance Cgd, the transconductance Gm, and the drain conductance Gds, as well as of the extrinsic parasitic gate, source,
and drain resistances, RG, RS, and RD. Adapted from [63].

investigate the quality of novel gate-channel interface when resistances, Gds and Gm are the drain-source conductance and
high-k dielectrics and metal gates for MOSFETs were intro- gate transconductance, respectively.
duced more than a decade ago [54, 55] and more recently By substituting the capacitances with the physical
with the eventual replacement of the silicon channel by III-V dimensions of the device, it is observed that Ft is independent
materials [56, 57]. Today, with the device channel length of of the channel width, but inversely proportional to the square
20 nm and below, the channel volume and gate interface are of the gate length.
extremely small and thus low-frequency noise is really Figure 9 shows the dependence of the cut-off frequency
dominated by single trapping events [58], making RTN on the gate length, for n- and p-channel devices, respectively.
measurements of advanced MOSFETs a very interesting topic The highest cut-off frequency value for the n-channel device
for research [59–61]. is 485, and 345 GHz for the p-channel device, with both
devices presenting a gate length of approximately 30 nm [36].
Both devices were fabricated based on 45 nm SOI CMOS
5. RF FOM technology featuring gate oxide of 1.16 nm, DSLs, advanced
activation annealing and stress memorization techniques, as
The high-frequency performance of a transistor is mainly reported in [64].
described by its capability to amplify AC input signals up to a The maximum oscillation frequency is the frequency at
certain frequency and to provide that power gain with a which the power gain is equal to unity. It can be expressed as
minimum of additional noise. Hereafter, the cut-off fre- the relation between maximum available gain (MAG) and the
quencies of the most advanced MOSFETS as well as their RF S-parameter, from [62, 65, 66]
noise performance are presented.
∣ S21∣
MAG = (k R - kR2 - 1 ) , (10)
5.1. Current gain cut-off frequency (Ft) and maximum ∣ S22 ∣
oscillation (Fmax) frequency
where kR is the Rollet stability factor which is expressed as
The cut-off frequency (Ft) is the frequency at which the small- 1- ∣ S11 ∣2 - ∣ S22 ∣2 + ∣ S12 S21 - S11 S22 ∣2
signal current gain of the transistor becomes unity. The cut- kR = 2 ∣ S12 S21 ∣
, (11)
off frequency is extracted from the x-axis interception of an
extrapolated −20 dB dec–1 line on the current gain |H21| and is only valid when the device is unconditionally stable i.e.
versus frequency curve [62]. kR > 1 for all possible source and drain impedances [67].
By two-port analysis, from the equivalent circuit shown Another approach to obtain Fmax is from the maximum
in figure 8 [63], an approximate expression for Ft can be unilateral gain (ULG ) by Mason [68, 69], which is the gain
expressed as when the lossless feedback network cancels the reverse
Gm 1
transmission of power from the output to the input, i.e.
Ft = 2p (Cgs + Cgd )
´ Cgd Gm (RS + R D ) (9 ) ∣ S12 ∣ = 0.
1 + Gds (R S + RD) +
Cgs + Cgd
1 1
ULG = 1- ∣ S11 ∣2
∣ S21∣2 1- ∣ S ∣2
. (12)
where Cgs and Cgd are the gate-source and gate-drain capa- 22

citances, RS and RD are the extrinsic parasitic source and drain Based on small-signal equivalent circuit, as shown in figure 8,

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 9. Current gain cut-off frequency versus gate length for (a) n-channel and (b) p-channel MOSFET, respectively. Black square symbols
are values for planar devices on bulk or SOI substrates, green diamond symbols are values for non-planar devices on bulk or SOI substrates,
blue triangle symbols are devices based on high-k dielectric and metal gates, and red circles represent values of devices fabricated using
strain/stressor technologies, respectively.

Figure 10. Maximum oscillation frequency variation with gate length for (a) n-channel and (b) p-channel MOSFET, respectively. Black
square symbols are values for planar devices on bulk or SOI substrates, green diamond symbols are values for non-planar devices on bulk or
SOI substrates, and red circles represent values of devices fabricated using strain/stressor technology, respectively.

Fmax can also be expressed as An Fmax value of 295 GHz has been reported for the
Gm 1 p-channel device with a gate length of 29 nm. The device
Fmax = 4pCgs
´ (13)
Gds (Ri + R S + R G ) + Gm R G
Cgd reported here was fabricated based on a 65 nm CMOS tech-
Cgs
nology platform employing uniaxial strain induced by epi-
where RG is the extrinsic parasitic gate resistance and Ri is the taxial silicon-germanium source/drain for enhanced
charging resistance, respectively. mobility [70].
Figure 10 shows the variation of the maximum oscilla- It is interesting to see from figure 9(a) that the best
tion frequency with the gate length, for n- and p-channel multiple-gate device (FinFET) [71] presents an Ft (91 GHz),
devices, respectively. The highest Fmax value of 450 GHz is which is more than three times lower than the best planar
obtained for an n-channel device with gate length 40 nm transistor (349 GHz). The low performance of FinFETs
featuring a gate oxide of 1.06 nm, together with DSLs, with compared with planar MOSFETs is associated mainly to the
the use of nickel-silicide as the gate metal to reduce gate larger parasitic capacitances [72]. The origin of the additional
resistance, as reported in [36]. parasitic capacitance in the case of FinFET (and multiple-gate

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

devices in general) is directly related to the metal or poly-

silicon interconnection between each fin. The parasitic capa-
citance value depends on the proximity between the gate and
source/drain electrodes.
In [73], measurements and numerical 3D simulations
clearly demonstrate the reduction in fringing capacitance is
achieved by reducing the fin spacing, and the source/drain fin
extension as well as by increasing the fin aspect ratio. In [74],
the model showed that triple-gate FinFETs suffer from very
high parasitic gate capacitances that are larger than the
expected projection of the ITRS. This shows that the FinFET
3D geometry optimization, such as the fin spacing reduction
is not sufficient to fulfill the ITRS requirements. A total
fringing gate capacitance with maximum value of
0.18 fF μm−1 for the sub-22 nm technology nodes is targeted,
and therefore the use of new materials and a process such as
an air gap or low-k dielectric spacers is of prime importance.
The trend lines drawn in figure 9 show that the cut-off
frequency is inversely proportional to the gate length and not
to the square of the gate length as was previously observed
from older generations [75, 76]. Reducing the gate length Figure 11. Noise figure variation with gate length. Black square
causes (i) a relative increase in the parasitic parameters out- symbols represent single-gate devices and green diamond symbols
represent FinFET devices, respectively.
side the channel related to series resistances, overlap and
fringing capacitances, and (ii) the charge carriers can reach
the velocity saturation at high drain voltage and thus gate 5.2. Minimum noise figure
transconductance is no longer inversely proportional to the The noise figure NFmin is the signal-to-noise ratio at the input
gate length. port divided by the signal-to-noise ratio at the output port, and
In the case of narrow devices, the device suffers from is widely used as a measure of high-frequency white noise
relatively large fringing field effects, which are created at the performance. In order to consider the effect of gate length on
perimeter of the active device region resulting in non-pro- noise figure, let us consider the saturation current (as
portionality of the gate capacitance with the device width expressed by equation (14)) of the MOSFET [76],
[77]. As a result Ft improvement is less significant in short-
channel compared with long-channel devices. Although there ⎛W ⎞
IDsat = mCox ⎜ ⎟(Vgs - VTH )2 , (14)
has not been a significant gain (as expected) in frequency ⎝ Lg ⎠
values due to aggressive downscaling from the 180 to the
45 nm node [75, 78], the benefits of downscaling nevertheless in scaled CMOS, due to the mobility degradation caused by
prove to be an incentive. The observed increase in Ft in short- both the vertical as well as the lateral field, equation (14)
channel is attributed to the improvement in gate transcon- reduces to
ductance and lower intrinsic capacitances. IDsat » WK (Vgs - VTH) , (15)
In a similar trend, the maximum oscillation frequency
shows inverse proportionality to the gate length, as can be where K is a technology-dependent constant. The transistor
seen in figure 10, but with some degradation, which is width is chosen so as to satisfy the desired impedance level,
attributed to the larger parasitic gate resistance [79]. Other which is determined at Z 0 = 50 W. According to [81], the
influencing factors include the number and width of gate minimum noise figure of a transistor can be expressed as
fingers, silicide gate, and metal T-gate. The gate resistance NFmin = 1 + k1 fCgs (R G + RS ) Gm , (16)
increases with reduction of the gate length, minimizing the
improvement of the maximum oscillation frequency for where k1 is a fitting parameter and f is the frequency. By
shorter gate length. substituting the expression of Gm and Cgs in equation (16), we
Similar to Ft, Fmax for the best multiple-gate device get NFmin aLg. It has to be noted that equation (16), called
(FinFET) [80] presents a much lower value than for the best Fukui’s formula, which was originally proposed for GaAs
planar transistor. The poor value of Fmax for the multiple-gate MOSFET in the 1970s [81], also works well for deep-sub-
device is directly related to its 3D architecture, which leads to micron silicon MOSFET.
larger parasitic gate capacitances as well as gate resistance. Moreover, while the cut-off frequency can be increased
It is therefore clear that a good understanding and by gate length downscaling, the performance factors such as
optimization of internal parameters such as source, drain maximum oscillation frequency and minimum noise figure
resistances, gate access resistance, overlap and fringing depend strongly on the parasitic components [82–84].
capacitances, which influence Ft and Fmax are very important The dependence of the minimum noise figure on the gate
to improve the RF performances of nanoscale devices. length, for data reported in the literature is shown in figure 11.

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

The plot shows the variation of the NFmin for single-gate and results in improved RF performances. The above-discussed
FinFET devices. Large values of NFmin are an indication of FoM are reported for devices implementing a combination of
degraded device performance, which is mainly due to the various different technologies such as the use of SOI sub-
increase in the RS x Gm value from equation (16). The large strate, non-planar or multiple-gate architecture, high-k di-
variation in the values are attributed to the difficulty in de- electric and metal gates and stress-inducing methods. With
embedding S-parameter data at relevant application fre- the advancement in semiconductor technology, each of these
quencies, device to tester impedance mismatch at low fre- methods is optimized to further enhance MOSFET
quency and the effects of layout and bias on noise [85]. performance.
Since the minimum noise figure increases at lower gate
voltages, any improvements with scaling may be offset as 6.1. Transition from single- to multiple-gate architecture
bias currents are reduced [86]. RF noise increases with
downscaling due to increase in gate leakage currents (due to 6.1.1. Bulk planar to bulk FinFET. Since their conception,
the use of thinner gate oxides) [87], increased substrate bulk MOSFETs have been the driving force for the
resistance [88] and higher velocity saturation due to higher- semiconductor industry. However, in the last few
channel electric fields [89]. The NFmin values given in table 1 technological nodes SCE have plagued their performance.
as a guideline by the ITRS are always lower than 0.2 dB. It Fortunately, devices implementing multiple-gate field-effect
has been proposed in [90] that devices with higher values of transistor (MuGFET) architecture, as shown in figure 12, have
Fmax have lower values of NFmin. An increase of Fmax values come to the rescue of their single-gate predecessors. The most
by 10% reduces the NFmin value by almost 80% [90]. promising architecture is the FinFET device, a schematic of
The authors would like to point out that there are not which shown in figure 12. A FinFET device consists of a tall
many references for Early voltage and the minimum noise channel surrounded by gate material on its three sides. The
figure, and hence there is an urgent need for the scientific first report of FinFET architecture dates back to 1999 [91] by
community to systematically extract these FoM in order to Hisamoto et al. Although the first reports demonstrating
deeply analyze their trend with MOSFET downscaling. FinFET architecture were based on the use of SOI substrates,
Intel the leading manufacturer of semiconductor chips has
demonstrated the latest Broadwell micro-architecture also
6. Performance boosters implementing second generation FinFET architecture built on
bulk silicon technology [92]. Key advantages of the FinFET
As device scaling is approaching physical limits, the tech- architecture include excellent compatibility with planar
nology cycle is slowing down due to various technical chal- CMOS process fabrication together with better drive current
lenges including increasing power consumption, process at fixed drain-source bias, immunity to SCE and higher on-
variation and costs. This relentless downscaling has led to the current to off-current ratio [93, 94].
evolution (or should be called a revolution) from planar sin- In contrast to bulk FinFET, when fabricated on SOI
gle-gate transistors fabricated on bulk silicon to multi-gate, substrates, further enhancement in device and circuit-level
multi-channel transistors fabricated on SOI technology. The performance [95] for digital and analog applications [40, 96]
following paragraphs address some of the performance has been observed. IBM has demonstrated the shrinkage of
boosters implemented by both academic research and industry SOI-based FinFETs down to a fin width of 4 nm [97] for the
to keep silicon devices at the forefront of semiconductor 10 nm node.
technology. However, the main disadvantages of the FinFET
As can be seen from the above sections (3–5), most of the architecture include different crystal orientation of the fins
performance boosters developed to improve the digital per- (causing mobility variation) and interface quality [98]. Apart
formance of MOSFETs are contributing to the enhancement from these, FinFET architecture also suffers from process
of the analog/RF performances as well. Indeed, to get a well- variations including gate-oxide non-uniformity on sidewalls,
behaved RF transistor, the very first requirement is to obtain a self-heating [99–102] and more importantly limited RF
good static characteristic of the device. This can be under- performance. Indeed, the current gain cut-off frequency and
stood from the fact that higher gate transconductance is maximum oscillation frequency of FinFET devices are lower
obtained on devices with better gate control on the channel compared with bulk devices and the main reason is attributed
carriers, higher charge carrier mobility and with lower contact to the large fringing gate capacitance which originates from
resistance (source-drain resistance). In a similar trend, higher the 3D architecture and multiple-fin configuration [73, 74].
cut-off and maximum oscillation frequency could be achieved
with larger values of gate transconductance and lower values 6.1.2. Bulk to SOI substrates. The introduction of SOI
of output conductance. Better SCE immunity can only be substrates in both academia and industry has overcome
achieved when the values of sub-threshold swing and drain- several problems related to bulk silicon technology. Some of
induced barrier lowering are lower, which translates to better these problems include reduced off-state current, lower
gate control of the channel. It can be concluded from the source/drain junction capacitances, improved switching
above two statements that devices with poor static/DC per- speed and reduced power consumption. In addition to the
formance cannot show enhanced RF/analog performances. above-mentioned factors, isolation from silicon handle
Hence, focussing on improving the static behavior often substrate provides latch-up free and inter-device leakage

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 12. Schematic of various multiple-gate architectures on SOI and bulk substrate.

free operation. There are two types of SOI transistors, (i) The excellent compatibility with the planar CMOS
when the top-silicon film is thicker than the depletion region process together with better drive current at fixed drain-
depth beneath the gate oxide, then it is termed as partially source bias, immunity to SCE, and higher on-current to off-
depleted (PD-SOI), and (ii) when the top-silicon film is current ratio has placed the FinFET architecture devices in a
thinner than the depletion region or if the doping better position than their double-gate counterparts. Other
concentration of the body is low enough to be fully multiple-gate architectures including triple gate, omega gate,
depleted of charge carriers it is termed FD-SOI [16]. pi-gate, gate-all-around or quadruple gate, have also been
Implementation of FD-SOI transistors results in extremely introduced and widely studied. Much detailed description of
low sub-threshold swing (<65 mV dec–1), does not have the different architectures is provided in [107]. Most of the
floating-body effects and low threshold voltage variation with investigations performed on FinFET architecture have
temperature and hence are superior in terms of performance focussed on technology and perspectives for digital applica-
over the partially depleted counterparts. The main drawback tions [108, 109]. As can be seen from the drain-induced
of the FD-SOI technology is the process variation, which is barrier lowering and sub-threshold swing section of this
mainly due to the variation in the thickness of the silicon film, article, the best values of these FoM are indeed obtained with
resulting in threshold voltage fluctuation. Fully-depleted FinFET architecture.
ultra-thin body SOI devices are considered as the best Despite these incentives, SOI technology suffers from
candidates for downscaling. Devices fabricated on undoped one major drawback, the self-heating effect, which degrades
or lightly doped ultra-thin body minimize impurity scattering charge carrier mobility [110] and causes a shift in threshold
and reduce threshold voltage variation, which arises due to voltages, which worsen in the case of fully depleted structures
random doping fluctuation [16]. In addition to the above due to thin silicon film [111]. However, it is worth noting that
advantages, SOI substrates allow the fabrication of devices for the most advanced CMOS nodes, thanks to the high
with novel architectures such as MuGFETs, which have more number of metal levels in the back-end-of-line (BEOL) that
than one gate (double, trigate, FinFET, gate-all-around), as could be as large as 10–15 metal layers, an efficient thermal
shown in figure 12. Such devices can be realized with path can be engineered via the BEOL and thus drastically
minimum modification in processing technology. The first minimize the importance of thermal path relative to the Si or
theoretical proposal of a double-gate architecture was by SOI substrate [112].
Sekigawa and Hayashi in 1984, where the architecture of the
proposed device resembles the Greek alphabet xi - Î; the
6.2. Strain engineering
silicon channel was sandwiched between a top and bottom
gate [103]. The first fabricated double-gate SOI MOSFET The use of strain engineering to enhance carrier mobility in
called the ‘fully DEpleted Lean-channel TrAnsistor’ or doped Si/SixGe1−x superlattices was reported as early as
DELTA resembled more a FinFET-like structure where the 1985 [113]. This widely adopted method to induce wafer-
silicon film stands vertically between the gates, two side gates based biaxial stress is practiced by growing a silicon film atop
and one top gate, as can be seen in figure 2 in [104]. relaxed silicon-germanium (SiGe) virtual substrate. A tensile
The first multiple-gate architecture device fabricated was biaxial stress is generated in the Si film, due to the lattice
the planar double gate and the concept was proposed by mismatch between Si and Ge atoms [114]. Uniaxial process-
Colinge et al, in the year 1990 [105]. Since the transverse induced stress application methods include strained capping
electric filed induced by the drain-source bias is shared by layers, strained contact-etch-stop-liners [115], embedded
both the top and bottom channel, the double-gate architecture Si1−xGex source/drain [116], DLS [117, 118] and since then
mitigates short-channel effects [106]. However, the main have been an indispensable part of state-of-the-art CMOS
drawback of the planar double-gate architecture is the technology [119, 120].
complexity to fabricate the aligned bottom-gate/channel/ Experimental studies have shown that applying
top-gate stack in a planar silicon technology. mechanical tensile strain on n-channel MOSFETs causes

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

mobility enhancement [121, 122], which is attributed to the transport, they revealed the key factors that affect the hole
sub-band energy splitting between the twofold and fourfold mobility in semiconductors—band splitting and warping,
valleys. The conduction band in bulk silicon is composed of mass change, and consequently the change of density of
six equivalent valleys. In inversion layers, these six valleys states, which alters band occupation and phonon scattering
are split into twofold valleys located at a central position in [127]. There have been a number of reports on the effects of
the 2D k-space and the fourfold valleys located on kx and ky strain on transport in silicon and the readers are directed to
axes, which is due to 2D quantization. 3D electrons have an [129] and the references therein. Although the main focus of
anisotropy in the effective mass, which is composed of light the industry in the late 1980s and early 1990s was on biaxial-
transversal and heavy longitudinal effective mass. This dif- induced stress in devices, the current focus has now shifted to
ference in the effective mass leads to differences in physical uniaxial stress owing to the main advantages it offers. The
properties between the twofold and fourfold valleys [123]. two main benefits of uniaxial stress techniques are, (i)
When tensile strain parallel to the MOS interface or com- mobility enhancement at both low strain and high vertical
pressive strain perpendicular to the MOS interface is applied electric field, which is attributed to the warping of the valence
to MOSFETs, the conduction band edge in the fourfold val- band under strain [130] and (ii) this enhancement in mobility
leys becomes higher than that in the twofold valleys and this provides larger drive current and gate transconductance
splitting energy is added to the sub-band energy difference improvement for nanoscale short-channel devices leading to
caused by the surface quantization. As a result, the sub-band higher cut-off frequencies. As shown in figures 9 and 10, the
energy between the two valleys significantly increases. This best cut-off and maximum oscillation frequency values have
increase in the sub-band energy splitting results in mobility been obtained for strained SOI MOSFETs, reiterating the fact
enhancement through two mechanisms: (i) increase in aver- that strain engineering results in enhanced device perfor-
aged mobility due to the increase in occupancy of electrons in mance, making it an indispensable inclusion in future CMOS
the twofold valleys having higher mobility, and (ii) the sup- devices.
pression of inter-valley scattering between the twofold and
fourfold valleys [123, 124]. This is because, when the split-
6.3. Ultra-thin-body and ultra-thin-buried-oxide
ting energy between the twofold and the fourfold valleys is
higher than the phonon energies associated with inter-valley The main limitations of planar bulk CMOS technology are
scattering, the transition of electrons in the twofold valleys increasing performance variability and off-state leakage cur-
through a phonon absorption process cannot occur, resulting rent. Rather than having an extremely high doping con-
in the reduction in the scattering probability. On the other centration in the channel, reducing the thickness can eliminate
hand, when compressive strain parallel to MOS interfaces or sub-surface leakage paths and reduce the drain-induced bar-
tensile strain perpendicular to MOS interfaces is applied to rier lowering [131]. In the case of an extremely thin body, the
MOSFETs, the electron mobility tends to decrease. This is channel is fully depleted of charge carriers when the transistor
attributable to the increase in the occupancy of the electrons is in the off-state. Such an ultra-thin-body (UTB) fully
in the fourfold valleys having lower mobility [123]. depleted MOSFET structure has already proved its benefits by
On the other hand, in the case of p-channel MOSFETs reduced SCE rather than halo-doped PD-SOI devices down to
strain-enhanced hole mobility presents a more complex pic- a gate length of 30 nm [132, 133]. When an extremely thin
ture. The valence-band structure of silicon comprises three body is implemented on a thin buried-oxide (25 nm or thin-
bands; the heavy-hole, light-hole, and spin–orbit split-off ner), it is termed as ultra-thin-body and ultra-thin-buried-
bands. The heavy-hole and the light-hole bands are degen- oxide (UTBB) architecture.
erated at k=0 and the coupling between them is responsible The use of ultra-thin-buried-oxide (BOX) suppresses
for the warping of the energy surfaces [125]. On the other fringing fields through the BOX, thereby improving SCE,
hand, the spin–orbit split-off band is shifted downward by reducing DIBL and sub-threshold swing [134–136]. The thin
0.044 eV and consequently is widely depopulated compared buried-oxide is also suitable for implementing back-gate
with those of heavy and light holes [126]. Due to this strong biasing for threshold voltage tuning, latch-up free operation,
band warping, strain effects on the valence-band structure reduced device variability and ease of process transfer from
cannot be explained by band shifts using deformation bulk technology [137]. However, the use of thin BOX triggers
potentials [127]. Hasegawa [128] and Hensel and Feher [125] strong coupling from the drain through the substrate resulting
studied the valence-band effective mass and deformation in loss of gate control over the channel (especially when the
potentials in strained silicon and compared them with substrate is depleted) [138], but this problem can be cir-
experiments. Hasegawa reported that under compressive cumvented with the incorporation of a highly doped layer
stress, the light-hole mass becomes larger and it varies underneath the BOX to produce a so-called ground plane
inversely with applied stress due to the mixing with the split- [138], back plane [139] or mirror doping [140]. Simulation
off hole band, and the heavy-hole mass does not change to the studies have also shown that introducing a ground plane
first order with strain. Hensel and Feher showed that under reduces DIBL due to depletion layer suppression under the
compressive stress, the light-hole band shifts up (becomes the BOX [141]. A highly doped layer implanted underneath
top valence band) and the heavy-hole band shifts down in (ground plane) the BOX screens the electric field of lines
energy. Although they are only concentrated on the zone penetrating the substrate. This ground plane also paves the
center (k=0) and did not discuss the strain effects on carrier way for fine tuning the threshold voltage for a digital circuit, a

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

Figure 13. Maximum oscillation frequency variation with gate length for (a) n-channel and (b) p-channel MOSFET, respectively. Black
square symbols are values for planar devices on bulk or SOI substrates, green diamond symbols are values for non-planar devices on bulk or
SOI substrates, and red circles represent values of devices fabricated using strain/stressor technologies, respectively.

higher threshold voltage when the transistor is put in the OFF the fact that an immediate successor to silicon could be a
state (Vgs < VTH ) and the possibility to lower the threshold device configuration such as high-electron mobility transistors
voltage when the transistor is in the ON state (Vgs > VTH ). By or heterojunction bipolar transistors, based on III-V channel
combining a thin BOX/ground plane with variable ground- materials. Owing to the superior properties of III-V materials,
plane doping, a threshold voltage shift can be obtained, which it is not a surprise to observe such high operating frequency
leads to optimization of the devices for both low-power and values in these devices.
high-performance applications [138]. In [142, 143], the high- Devices based on graphene and other 2D materials are
frequency behavior of 28 nm UTBB from ST-M is presented. plagued with problems, some of which include the synthesis
Without any process or architecture optimization for RF, and transfer of large-area material. In addition to this, residual
those transistors have an Ft and Fmax of 280 and 250 GHz, contamination has also largely plagued device performance
respectively. The back-gate contact can also be used to boost and industrial application.
the RF performance of UTBB [144] and to improve the lin- Another weak point of graphene MOSFETs (for RF
earity of the transistor [145]. application) reported so far is the unsatisfactory saturation
behavior (only weak saturation or the second linear regime),
6.4. III-V and 2D materials which has an adverse impact on the cut-off frequency, the
The gradual deceleration in silicon downscaling has driven intrinsic gain and other FoM for RF devices [149].
research activities in the field of alternative channel materials Although devices based on TMD materials can address
that exhibit enhanced performance. Devices based on III-V some of the fundamental issues with graphene-based devices,
materials including BJTs and HEMT have shown superior RF literature reports on TMD material-based devices have much
characteristics, particularly their high speed, low DC power inferior performance, indicating that more effort needs to be
consumption and excellent noise characteristics [146]. Recent put in this direction. Readers are referred to the review paper
reports have confirmed that InGaAs devices have electron from F. Schwierz [149] for further reading on this topic.
mobility in excess of 10 000 cm2 V–1s–1, operating frequency From the above discussions, the two main contenders to
greater than 700 GHz, sub-threshold swing of 70 mV dec–1 help continue Moore’s law (based on silicon technology) in
and gate transconductance greater than 3000 mS mm−1 [147], the near future are, FinFET architecture and UTBB. Despite
thereby realizing n-channel devices. On the other hand, the disadvantages (and advantages), these two technological
compressively strained InGaSb and Ge, are promising mate- blocks possess, they have established their place in main-
rials for p-channel devices [148]. stream industrial processes for different applications. How-
In the search for new channel materials, there has been a ever, the choice between bulk FinFET and SOI UTBB will
recent escalation in research activities related to the applica- depend on the application. It needs to be emphasized here that
tion of 2D materials. Graphene, the first 2D material, has ST-M 28 nm bulk is slightly faster and cheaper than 28 nm
paved the way for the scientific community to explore similar FD-SOI, but the latter consumes less power. FD-SOI will be
materials called transition metal dichalcogenides (TMDs). competitive for the 22 and 14 nm nodes. In fact, for these
As can be observed from figures 13(a) and (b), the nodes the single-gate bulk MOSFET will not only face
highest value of Ft and Fmax for III-V-based MOSFETs is far challenges in terms of predominant SCE but the increase of
higher than state-of-the-art silicon MOSFETs, pointing out to cost and complexity involved in the fabrication process will

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

foresee the move to FinFET architecture. However, the main 7. Conclusion

drawback of the FinFET architecture is the parasitic resistance
and capacitance, which if well suppressed could boost per- Today, PD-SOIs with a channel length of 65, 90 or 130 nm
formance in terms of operating frequency with downscaling. are the mainstream technologies for RF SOI ICs. A new
Thus, at that time, for those nodes, SOI keeping a planar generation of mobile communication systems such as 5G
architecture and thus a classical process flow, models and requires higher cut-off frequency for the system, better line-
process design kit will be quite competitive. arity and lower power consumption. Thus, for transistors to
It is worth noting that the best MOS transistors exhibit operate at higher cut-off frequencies, RF SOI must move
cut-off frequencies Ft and Fmax, which still remain below the towards shorter nodes. However, further reduction of device
ITRS roadmap targets presented in table 1. Besides the dimensions is problematic due to intrinsic physical limitations
mobility boosters, an efficient improvement is achievable by such as SCE, high current leakage through ultra-thin gate
dielectrics, high series resistances, low mobility due to
optimization of the process and architecture targeting reduc-
interface effects, high current density and thus self-heating
tion of parasitic series resistances and capacitances using (i) a
and reliability issues, and so on. Researchers are investigating
silicidation process of the source, drain and gate regions
alternative channel materials such as III-V materials, carbon
[150], (ii) optimization of device layout and dimensions (i.e. nanotubes, graphene and other 2D materials to help continue
gate pitch and width) to reduce the fringing effects at the Moore’s law. Although some of these materials have found
perimeter, (iii) optimization of the underlap length, i.e. when niche applications, they have not yet managed to weaken the
the effective channel length is longer than the physical charm of silicon-based technology that has ruled the semi-
channel length. This provides a trade-off between the gate conductor industry for over five decades. FD-SOI is foreseen
transconductance (which is related to parasitic resistances) as the most promising candidate to fulfill the device
and total gate capacitance [151, 152], (iv) device architecture requirements in terms of high-frequency performance at low
and spacer materials: modification of the device architecture power consumption.
such as introduction of faceted source and drain [153–155], Moreover, it is worth pointing out that the RF perfor-
low-k spacer materials [156, 157] gate capping layer thickness mance of an IC will not only depend on the analog and high-
and gate height [157] can be used to reduce the fringing frequency characteristics of the active devices, i.e. the tran-
parasitic capacitance effect. sistors, but the quality of the BEOL process, which defines
It is also worth mentioning that the RF performance of an the losses along the interconnection line and the quality factor
integrated circuit will not only depend on the analog and of the passive elements such as the inductors and tunable
high-frequency characteristics of the active devices, i.e. the capacitors, as well as the electromagnetic properties of the
transistors, but also the quality of the BEOL process, which substrate on which the RF IC lies. Indeed, the parasitic
defines the losses along the interconnection line and the resistances (metal lines and vias) and capacitances (dielectric
quality factor of the passive elements such as the inductors layers) along the interconnection constitute a low-pass filter,
which drastically limits the operational frequency of ICs. The
and tunable capacitors, as well as the electromagnetic prop-
advanced BEOL process provides a higher number of metal
erties of the substrate on which the RF IC is positioned.
lines, thicker metal layers and low-k dielectric interlayers.
Indeed, the parasitic resistances (metal lines and vias) and
High-resistivity SOI and trap-rich SOI substrates are used
capacitances (dielectric layers) along the interconnection today with PD-SOI ICs in order to minimize the substrate
constitute a low-pass filter, which drastically limits the losses, crosstalk and non-linearities. One of the challenges for
operational frequency of ICs. An advanced BEOL process future RF ICs is the integration of FD-SOI devices with back-
provides a higher number of metal lines, thicker metal layers, gate contact (UTBB) and high-quality trap-rich SOI
low-k dielectric interlayers, and denser vias using carbon substrates.
nanotubes are investigated for diminishing the parasitic The race to follow and continue Moore’s law has slowed
resistances between metal layers [158–162]. down and Gordon Moore himself has reiterated, ‘No expo-
The substrate losses, non-linear behavior and crosstalk nential is forever, but forever can be delayed.’
remain a challenge for designing high-performance ICs in Si-
based technologies for RF applications. The possibility of
creating high-resistivity substrates [163] characterized with an Acknowledgment
effective resistivity as high as 10 kΩ cm–1, extremely low
losses, high-linearity and low crosstalk thanks to the intro- Vikram Passi would like to acknowledge funding from the
duction of traps below the BOX was demonstrated [164–169]. European Regional Development Fund, program EFRE.NRW
Today, Soitec commercializes trap-rich SOI substrates under 2014-2020, grant agreement EFRE-0801002 (HEA2D)
the name of ‘RF-eSI’, which stands for enhanced signal
integrity substrate. These substrates are widely used by all the
major CMOS foundries for building state-of-the-art RF ORCID iDs
switches.
Vikram Passi https://orcid.org/0000-0003-0314-5734

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Semicond. Sci. Technol. 32 (2017) 123004 Topical Review

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