DATA SHEET

SMP1330-085LF: Surface-Mount Limiter Diode

Applications Anode
Anode
(Pin 1) (Pin 3)
• Low-loss, high-power limiters
• Receiver protectors

Features
• Low thermal resistance: 91 °C/W Cathode
(Pin 2, Exposed Paddle)
• Typical threshold level: +9 dBm
• Low capacitance: 0.55 pF Figure 1. SMP1330-085LF Block Diagram

• Low-profile, ultra-miniature QFN (3-pin, 2 x 2 mm) package

(MSL1, 260 °C per JEDEC J-STD-020) Description
The SMP1330-085LF is a surface-mountable, low-capacitance
silicon PIN limiter diode designed as a shunt connected PIN diode
Skyworks GreenTM products are compliant with for high power limiter applications up to 6 GHz.
all applicable legislation and are halogen-free.
Maximum resistance at 10 mA is 2 Ω and maximum capacitance
For additional information, refer to Skyworks
at 0 V is 0.55 pF. The combination of low junction capacitance,
Definition of GreenTM, document number
SQ04–0074. low parasitic inductance, low thermal resistance, and nominal
2 um I-region width, makes the SMP1330-085LF useful in large
signal limiter applications. The threshold level is +9 dBm
at 1 GHz.
A block diagram of the SMP1330-085LF is shown in Figure 1. The
absolute maximum ratings of the SMP1330-085LF are provided in
Table 1. Electrical specifications are provided in Table 2.
Typical performance characteristics of the SMP1330-085LF are
provided in Table 3 and illustrated in Figures 4 and 5

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DATA SHEET • SMP1330-085LF: Surface-Mount Limiter Diode

Table 1. SMP1330-085LF Absolute Maximum Ratings1

Parameter Symbol Minimum Maximum Units
Reverse voltage VR 50 V
Forward current @ 25 °C IF 1.5 A
CW power dissipation @ 25 °C PD 1.1 W
Peak pulse power dissipation @ 25 °C (10% duty cycle) 11 W
Storage temperature TSTG -65 +175 °C
Junction temperature TJ +175 °C
Operating temperature TA -55 +150 °C
Electrostatic discharge: ESD
Human Body Model (HBM), Class 1A 250 500 V
1 Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters
set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.

ESD HANDLING: Although this device is designed to be as robust as possible, electrostatic discharge (ESD) can damage this device.
This device must be protected at all times from ESD when handling or transporting. Static charges may easily produce
potentials of several kilovolts on the human body or equipment, which can discharge without detection.
Industry-standard ESD handling precautions should be used at all times.

Table 2. SMP1330-085LF Electrical Specifications1

(TA = +25 °C Unless Otherwise Noted)
Parameter Symbol Test Condition Min Typ Max Units
Breakdown voltage VB IR = 10 μA 30 50 V
Reverse current IR VR = 24 V 100 nA
Capacitance CT f = 1 MHz:
VR = 0 V 0.55 1.00 pF
VR = 6 V 0.50 0.60 pF
Capacitance ratio CTR CT @ 0 V/CT @ 6 V 1.22 -
Series resistance RS f = 100 MHz, IF = 10 mA 1.6 2.0 Ω
Carrier lifetime TL IF = 10 mA 13 ns
I region width W 2 um
CW thermal resistance θJC Junction-to-case 89 °C/W
Peak thermal resistance θP Single 1 us pulse width, junction-to-
case (10% duty cycle) 9 °C/W
1 Performance is guaranteed only under the conditions listed in this table.

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DATA SHEET • SMP1330-085LF: Surface-Mount Limiter Diode

Table 3. Typical Performance @ 25 °C

Insertion Loss Input Power for Maximum Pulsed Output @ Maximum Maximum CW
@ -10 dBm 1 dB Loss Input Power Pulsed Input Input Power Recovery Time
Part Number (dB) (dBm) (dBm) (dBm) (W) (ns)
SMP1330-085LF 0.1 +9 +48 +22 3 10
Notes:
Limiter power results @ 1 GHz for shunt-connected, single-limiter diode and DC return in 50 Ω line.
Maximum pulsed power for 1 us pulse and 0.1% duty factor with chip @ 25 °C heat sink. Derate linearly to 0 W @ 175 °C.
Maximum CW input power @ 25 °C heat sink. Derate linearly to 0 W @ 175 °C.
Recovery time represents the transition time from the high-loss state to the low-loss state following the removal of a high-power input. It is defined as the time from the end of the
high-power pulse to the time when insertion loss has returned to within 3 dB of the quiescent (low-power) state.

Functional Description
The PIN limiter diode can be described as an incident power The DC block capacitors shown in Figure 2 are optional; they
controlled, RF variable resistor. When there is no large input protect the limiter diode from external DC voltage that may be
signal present, the impedance of the limiter diode is at its present in the source or load circuits.
maximum, which produces minimum insertion loss, typically A cross section of the suggested printed circuit board design is
less than 0.1 dB. The presence of a large input signal shown in Figure 3. The via shown in this view is critical, both for
temporarily forces the impedance of the diode to a much lower electrical performance and for thermal performance. It is
value, which produces an impedance mismatch that reflects the recommended that several vias should be placed under the
majority of the input signal power back towards its source. entire footprint of the exposed paddle (pin 2) to minimize both
During the limiting process, a DC current is generated by the electrical inductance to the system ground and thermal
PIN limiter diode. The current is not the result of rectification, resistance to the system heat sink.
but is the result of charge carriers being forced into the I layer For more information about the operation of limiter diodes, refer
by the forward alternations of the large input signal. A complete to the Skyworks Application Note, PIN Limiter Diodes in
path must be provided for this current or the diode is not Receiver Protectors, document number 200480.
capable of limiting. Therefore, an RF choke or similar structure
must be provided to complete the path for DC current flow.

DC DC
Block Block
Input Output

Limiter RF
PIN Choke

Figure 2. Single Stage Limiter Circuit

SMP1330-085LF

Thermal Via

S1630c

Figure 3. Cross-Sectional View of Suggested Printed Circuit Board

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DATA SHEET • SMP1330-085LF: Surface-Mount Limiter Diode

Typical Performance Characteristics

(TA = 25 °C, Unless Otherwise Noted)

20 0 20 0
-2 18 -2
18
-4 -4
16

Output Power (dBm)

16
Output Power (dBm)

Insertion Loss (dB)

Insertion Loss (dB)
-6 -6
14 14 -8
-8
12 -10 12 -10
-12 10 -12
10
-14 -14
8 8
Output Power -16 Output Power -16
6 6 Insertion Loss -18
Insertion Loss -18
4 -20 4 -20
4 8 12 16 20 24 28 32 36 4 8 12 16 20 24 28 32 36

Input Power (dBm) ts223 Input Power (dBm) ts224

Figure 4. Insertion Loss and Output Power vs Input Power Figure 5. Insertion Loss and Output Power vs Input Power
(f = 1.0 GHz, Board Loss Included) (f = 2.6 GHz, Board Loss Included)

High-Power Limiter Design Application The copper ground paddle minimizes the total thermal resistance
The SMP1330-085LF PIN limiter diode is designed for shunt between the I layer, which is the location where most heat is
applications in receiver protection power limiter circuits. generated under normal operation, and the surface to which the
Compared to other surface mount packages, the design of the package is mounted. Minimal thermal resistance between the
QFN package produces lower thermal resistance and also reduces I layer and the external environment minimizes junction
the effects of the parasitic inductance of the anode bond wires. temperature.

A cross-sectional view of the SMP1330-085LF PIN limiter diode is The electrically equivalent circuit of the SMP1330-085LF PIN
shown in Figure 6. The cathode of the die is soldered directly to limiter diode is shown in Figure 7. The inductances of pins 1 and
the top of the exposed paddle. This paddle is composed of 2, as well as the inductances of the bond wires are in series with
copper, so its thermal resistance is very low. the input and output transmission lines of the external circuit
rather than the portion of the circuit that contains the shunt PIN
limiter diode.

Bond Wire Encapsulated

(2 Places) Epoxy

SMP1330-085LF Die

Anode Cathode Anode

(Pin 1) (Pin 2) (Pin 3)
Not to scale S1628c

Figure 6. Cross-Sectional View of the SMP1330-085LF

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DATA SHEET • SMP1330-085LF: Surface-Mount Limiter Diode

LSERIES LSERIES
Pin 1 Pin 3

CPKG CPKG
SMP1330-085LF
Die

LPADDLE

Pin 2 S1629c

Figure 7. SMP1330-085LF Electrically Equivalent Circuit

Package Dimensions Package and Handling Information

The PCB layout footprint for the SMP1330-085LF is shown in Instructions on the shipping container label regarding exposure to
Figure 8. Typical part markings are shown in Figure 9. Package moisture after the container seal is broken must be followed.
dimensions are provided in Figure 10, and Figure 11 provides the Otherwise, problems related to moisture absorption may occur
tape and reel dimensions. when the part is subjected to high temperature during solder
assembly.
The SMP1330-085LF is rated to Moisture Sensitivity Level 1
(MSL1) at 260 °C. It can be used for lead or lead-free soldering.
For additional information, refer to the Skyworks Application Note,
Solder Reflow Information, document number 200164.
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format.

2X 0.60
Part Outline
2X 0.55

Exposed Soldering
Area Typ.
2X 0.27

Pin 3 2X 0.85
Pin 1
Pin 2

R0.20

2X 0.25 S2923

Figure 8. SMP1330-085LF PCB Layout Footprint

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DATA SHEET • SMP1330-085LF: Surface-Mount Limiter Diode

Skyworks Part #

RQ
3 1

Orientation
Indicator

3 1

Figure 9. Typical Part Markings

(Top View)

0.5 ± 0.15
2 ± 0.2
Exposed Pad

Detail B

2 ± 0.2 1.7 ± 0.15

1 3

Orientation 0.90 ± 0.1

Indicator
Top View Side View Bottom View

1 3
0.4 ± 0.1

2
0.27 ± 0.15

Detail B
All dimensions in millimeters S1632

Figure 10. SMP1330-085LF Package Dimensions

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DATA SHEET • SMP1330-085LF: Surface-Mount Limiter Diode

∅1.50+ 0.10/–0.00

4.00 ± 0.10 4.00 (see Note 4) 2.00 ± 0.05 1.75 ± 0.10

0.30 ± 0.05 (T) Pin #1

3.50 ± 0.05

8.00 +0.30/–0.10
A A
2.30 (Bo)

B
1.00 (Ko) ∅1.00 Min.
R0.30 Typ.
2.30 (Ao)
B
Notes:
1. Carrier tape: black conductive polystyrene.
2. Cover tape material: transparent conductive HSA.
3. Cover tape size: 5.40 mm width.
4. Ten sprocket hole pitch cumulative tolerance = ±0.20 mm.
5. ESD surface resistivity is ≤1 x 108 Ohms/square per EIA, JEDEC
A
tape and reel specification.
6. Ao and Bo measurement point to be 0.30 mm from bottom pocket.
7. All measurements are in millimeters. S1601

Figure 11. SMP1330-085LF Tape and Reel Dimensions

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DATA SHEET • SMP1330-085LF: Surface-Mount Limiter Diode

Ordering Information
Part Number Product Description Evaluation Board Part Number
SMP1330-085LF Surface-Mount Limiter Diode SMP1330-085-EVB

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