Chapter 5.

Gate-Level Modeling
In the earlier chapters, we laid the foundations of Verilog design by discussing design
methodologies, basic conventions and constructs, modules and port interfaces. In this
chapter, we get into modeling actual hardware circuits in Verilog.

We discussed the four levels of abstraction used to describe hardware. In this chapter, we
discuss a design at a low level of abstraction?gate level. Most digital design is now done
at gate level or higher levels of abstraction. At gate level, the circuit is described in terms
of gates (e.g., and, nand). Hardware design at this level is intuitive for a user with a basic
knowledge of digital logic design because it is possible to see a one-to-one
correspondence between the logic circuit diagram and the Verilog description. Hence, in
this book, we chose to start with gate-level modeling and move to higher levels of
abstraction in the succeeding chapters.

Actually, the lowest level of abstraction is switch- (transistor-) level modeling. However,
with designs getting very complex, very few hardware designers work at switch level.
Therefore, we will defer switch-level modeling to Chapter 11, Switch-Level Modeling, in
Part 2 of this book.

Learning Objectives

• Identify logic gate primitives provided in Verilog.

• Understand instantiation of gates, gate symbols, and truth tables for and/or and
buf/not type gates.

• Understand how to construct a Verilog description from the logic diagram of the
circuit.

• Describe rise, fall, and turn-off delays in the gate-level design.

• Explain min, max, and typ delays in the gate-level design.

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5.1 Gate Types

A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates
as predefined primitives. These primitives are instantiated like modules except that they
are predefined in Verilog and do not need a module definition. All logic circuits can be
designed by using basic gates. There are two classes of basic gates: and/or gates and
buf/not gates.

5.1.1 And/Or Gates

And/or gates have one scalar output and multiple scalar inputs. The first terminal in the
list of gate terminals is an output and the other terminals are inputs. The output of a gate
is evaluated as soon as one of the inputs changes. The and/or gates available in Verilog
are shown below.

and or xor
nand nor xnor

The corresponding logic symbols for these gates are shown in Figure 5-1. We consider
gates with two inputs. The output terminal is denoted by out. Input terminals are denoted
by i1 and i2.

Figure 5-1. Basic Gates

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These gates are instantiated to build logic circuits in Verilog. Examples of gate
instantiations are shown below. In Example 5-1, for all instances, OUT is connected to
the output out, and IN1 and IN2 are connected to the two inputs i1 and i2 of the gate
primitives. Note that the instance name does not need to be specified for primitives. This
lets the designer instantiate hundreds of gates without giving them a name.

More than two inputs can be specified in a gate instantiation. Gates with more than two
inputs are instantiated by simply adding more input ports in the gate instantiation (see
Example 5-1). Verilog automatically instantiates the appropriate gate.

Example 5-1 Gate Instantiation of And/Or Gates

wire OUT, IN1, IN2;

// basic gate instantiations.

and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);
or or1(OUT, IN1, IN2);
nor nor1(OUT, IN1, IN2);
xor x1(OUT, IN1, IN2);
xnor nx1(OUT, IN1, IN2);

// More than two inputs; 3 input nand gate

nand na1_3inp(OUT, IN1, IN2, IN3);

// gate instantiation without instance name

and (OUT, IN1, IN2); // legal gate instantiation

The truth tables for these gates define how outputs for the gates are computed from the
inputs. Truth tables are defined assuming two inputs. The truth tables for these gates are
shown in Table 5-1. Outputs of gates with more than two inputs are computed by
applying the truth table iteratively.

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 Table 5-1. Truth Tables for And/Or

Gates

5.1.2 Buf/Not Gates

Buf/not gates have one scalar input and one or more scalar outputs. The last terminal in
the port list is connected to the input. Other terminals are connected to the outputs. We
will discuss gates that have one input and one output.

Two basic buf/not gate primitives are provided in Verilog.

buf not

The symbols for these logic gates are shown in Figure 5-2.

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 Figure 5-2. Buf and Not Gates

These gates are instantiated in Verilog as shown Example 5-2. Notice that these gates can
have multiple outputs but exactly one input, which is the last terminal in the port list.

Example 5-2 Gate Instantiations of Buf/Not Gates

// basic gate instantiations.

buf b1(OUT1, IN);
not n1(OUT1, IN);

// More than two outputs

buf b1_2out(OUT1, OUT2, IN);

// gate instantiation without instance name

not (OUT1, IN); // legal gate instantiation

The truth tables for these gates are very simple. Truth tables for gates with one input and
one output are shown in Table 5-2.

Table 5-2. Truth Tables for Buf/Not Gates

Bufif/notif

Gates with an additional control signal on buf and not gates are also available.

bufif1 notif1
bufif0 notif0

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These gates propagate only if their control signal is asserted. They propagate z if their
control signal is deasserted. Symbols for bufif/notif are shown in Figure 5-3.

Figure 5-3. Gates Bufif and Notif

The truth tables for these gates are shown in Table 5-3.

Table 5-3. Truth Tables for Bufif/Notif Gates

These gates are used when a signal is to be driven only when the control signal is
asserted. Such a situation is applicable when multiple drivers drive the signal.
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These drivers are designed to drive the signal on mutually exclusive control signals.
Example 5-3 shows examples of instantiation of bufif and notif gates.

Example 5-3 Gate Instantiations of Bufif/Notif Gates

//Instantiation of bufif gates.

bufif1 b1 (out, in, ctrl);
bufif0 b0 (out, in, ctrl);

//Instantiation of notif gates

notif1 n1 (out, in, ctrl);
notif0 n0 (out, in, ctrl);

5.1.3 Array of Instances

There are many situations when repetitive instances are required. These instances differ
from each other only by the index of the vector to which they are connected. To simplify
specification of such instances, Verilog HDL allows an array of primitive instances to be
defined.[1] Example 5-4 shows an example of an array of instances.

[1] Refer to the IEEE Standard Verilog Hardware Description Language document for
detailed information on the use of an array of instances.

Example 5-4 Simple Array of Primitive Instances

wire [7:0] OUT, IN1, IN2;

// basic gate instantiations.

nand n_gate[7:0](OUT, IN1, IN2);

// This is equivalent to the following 8 instantiations

nand n_gate0(OUT[0], IN1[0], IN2[0]);
nand n_gate1(OUT[1], IN1[1], IN2[1]);
nand n_gate2(OUT[2], IN1[2], IN2[2]);
nand n_gate3(OUT[3], IN1[3], IN2[3]);
nand n_gate4(OUT[4], IN1[4], IN2[4]);
nand n_gate5(OUT[5], IN1[5], IN2[5]);
nand n_gate6(OUT[6], IN1[6], IN2[6]);
nand n_gate7(OUT[7], IN1[7], IN2[7]);

5.1.4 Examples

Having understood the various types of gates available in Verilog, we will discuss a real
example that illustrates design of gate-level digital circuits.

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Gate-level multiplexer

We will design a 4-to-1 multiplexer with 2 select signals. Multiplexers serve a useful
purpose in logic design. They can connect two or more sources to a single destination.
They can also be used to implement boolean functions. We will assume for this example
that signals s1 and s0 do not get the value x or z. The I/O diagram and the truth table for
the multiplexer are shown in Figure 5-4. The I/O diagram will be useful in setting up the
port list for the multiplexer.

Figure 5-4. 4-to-1 Multiplexer

We will implement the logic for the multiplexer using basic logic gates. The logic
diagram for the multiplexer is shown in Figure 5-5.

Figure 5-5. Logic Diagram for Multiplexer

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The logic diagram has a one-to-one correspondence with the Verilog description. The
Verilog description for the multiplexer is shown in Example 5-5. Two intermediate nets,
s0n and s1n, are created; they are complements of input signals s1 and s0. Internal nets
y0, y1, y2, y3 are also required. Note that instance names are not specified for primitive
gates, not, and, and or. Instance names are optional for Verilog primitives but are
mandatory for instances of user-defined modules.

Example 5-5 Verilog Description of Multiplexer

// Module 4-to-1 multiplexer. Port list is taken exactly from

// the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;

// Internal wire declarations

wire s1n, s0n;
wire y0, y1, y2, y3;

// Gate instantiations

// Create s1n and s0n signals.

not (s1n, s1);
not (s0n, s0);

// 3-input and gates instantiated

and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);

// 4-input or gate instantiated

or (out, y0, y1, y2, y3);

endmodule

This multiplexer can be tested with the stimulus shown in Example 5-6. The stimulus
checks that each combination of select signals connects the appropriate input to the
output. The signal OUTPUT is displayed one time unit after it changes. System task
$monitor could also be used to display the signals when they change values.

Example 5-6 Stimulus for Multiplexer

// Define the stimulus module (no ports)

module stimulus;

// Declare variables to be connected

// to inputs
reg IN0, IN1, IN2, IN3;

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reg S1, S0;

// Declare output wire

wire OUTPUT;

// Instantiate the multiplexer

mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

// Stimulate the inputs

// Define the stimulus module (no ports)
initial
begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\n",IN0,IN1,IN2,IN3);

// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);

// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1, S0, OUTPUT);
end

endmodule

The output of the simulation is shown below. Each combination of the select signals is
tested.

IN0= 1, IN1= 0, IN2= 1, IN3= 0

S1 = 0, S0 = 0, OUTPUT = 1

S1 = 0, S0 = 1, OUTPUT = 0

S1 = 1, S0 = 0, OUTPUT = 1

S1 = 1, S0 = 1, OUTPUT = 0

4-bit Ripple Carry Full Adder

In this example, we design a 4-bit full adder whose port list was defined in Section 4.2.1,
List of Ports. We use primitive logic gates, and we apply stimulus to the 4-bit full adder

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to check functionality . For the sake of simplicity, we will implement a ripple carry adder.
The basic building block is a 1-bit full adder. The mathematical equations for a 1-bit full
adder are shown below.

sum = (a b cin)

cout = (a b) + cin (a b)

The logic diagram for a 1-bit full adder is shown in Figure 5-6.

Figure 5-6. 1-bit Full Adder

This logic diagram for the 1-bit full adder is converted to a Verilog description, shown in
Example 5-7.

Example 5-7 Verilog Description for 1-bit Full Adder

// Define a 1-bit full adder

module fulladd(sum, c_out, a, b, c_in);

// I/O port declarations

output sum, c_out;
input a, b, c_in;

// Internal nets
wire s1, c1, c2;

// Instantiate logic gate primitives

xor (s1, a, b);
and (c1, a, b);

xor (sum, s1, c_in);

and (c2, s1, c_in);

xor (c_out, c2, c1);

endmodule
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A 4-bit ripple carry full adder can be constructed from four 1-bit full adders, as shown in
Figure 5-7. Notice that fa0, fa1, fa2, and fa3 are instances of the module fulladd (1-bit
full adder).

Figure 5-7. 4-bit Ripple Carry Full Adder

This structure can be translated to Verilog as shown in Example 5-8. Note that the port
names used in a 1-bit full adder and a 4-bit full adder are the same but they represent
different elements. The element sum in a 1-bit adder is a scalar quantity and the element
sum in the 4-bit full adder is a 4-bit vector quantity. Verilog keeps names local to a
module. Names are not visible outside the module unless hierarchical name referencing is
used. Also note that instance names must be specified when defined modules are
instantiated, but when instantiating Verilog primitives, the instance names are optional.

Example 5-8 Verilog Description for 4-bit Ripple Carry Full Adder

// Define a 4-bit full adder

module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;

// Internal nets
wire c1, c2, c3;

// Instantiate four 1-bit full adders.

fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);

endmodule

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Finally, the design must be checked by applying stimulus, as shown in Example 5-9. The
module stimulus stimulates the 4-bit full adder by applying a few input combinations and
monitors the results.

Example 5-9 Stimulus for 4-bit Ripple Carry Full Adder

// Define the stimulus (top level module)

module stimulus;

// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4

fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);

// Set up the monitoring for the signal values

initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b, SUM= %b\n",
A, B, C_IN, C_OUT, SUM);
end

// Stimulate inputs
initial
begin
A = 4'd0; B = 4'd0; C_IN = 1'b0;

#5 A = 4'd3; B = 4'd4;

#5 A = 4'd2; B = 4'd5;

#5 A = 4'd9; B = 4'd9;

#5 A = 4'd10; B = 4'd15;

#5 A = 4'd10; B = 4'd5; C_IN = 1'b1;

end

endmodule

The output of the simulation is shown below.

0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000

5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111
10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111
15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010
20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001
25 A= 1010, B=0101, C_IN= 1,, C_OUT= 1, SUM= 0000

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5.2 Gate Delays

Until now, we described circuits without any delays (i.e., zero delay). In real circuits,
logic gates have delays associated with them. Gate delays allow the Verilog user to
specify delays through the logic circuits. Pin-to-pin delays can also be specified in
Verilog. They are discussed in Chapter 10, Timing and Delays.

5.2.1 Rise, Fall, and Turn-off Delays

There are three types of delays from the inputs to the output of a primitive gate.

Rise delay

The rise delay is associated with a gate output transition to a 1 from another value.

Fall delay

The fall delay is associated with a gate output transition to a 0 from another value.

Turn-off delay

The turn-off delay is associated with a gate output transition to the high impedance value
(z) from another value.

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If the value changes to x, the minimum of the three delays is considered.

Three types of delay specifications are allowed. If only one delay is specified, this value
is used for all transitions. If two delays are specified, they refer to the rise and fall delay
values. The turn-off delay is the minimum of the two delays. If all three delays are
specified, they refer to rise, fall, and turn-off delay values. If no delays are specified, the
default value is zero. Examples of delay specification are shown in Example 5-10.

Example 5-10 Types of Delay Specification

// Delay of delay_time for all transitions

and #(delay_time) a1(out, i1, i2);

// Rise and Fall Delay Specification.

and #(rise_val, fall_val) a2(out, i1, i2);

// Rise, Fall, and Turn-off Delay Specification

bufif0 #(rise_val, fall_val, turnoff_val) b1 (out, in, control);

Examples of delay specification are shown below.

and #(5) a1(out, i1, i2); //Delay of 5 for all transitions

and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off
= 5

5.2.2 Min/Typ/Max Values

Verilog provides an additional level of control for each type of delay mentioned above.
For each type of delay?rise, fall, and turn-off?three values, min, typ, and max, can be
specified. Any one value can be chosen at the start of the simulation. Min/typ/max values
are used to model devices whose delays vary within a minimum and maximum range
because of the IC fabrication process variations.

Min value

The min value is the minimum delay value that the designer expects the gate to have.

Typ val

The typ value is the typical delay value that the designer expects the gate to have.

Max value

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The max value is the maximum delay value that the designer expects the gate to have.

Min, typ, or max values can be chosen at Verilog run time. Method of choosing a
min/typ/max value may vary for different simulators or operating systems. (For Verilog-
XL , the values are chosen by specifying options +maxdelays, +typdelays, and
+mindelays at run time. If no option is specified, the typical delay value is the default).
This allows the designers the flexibility of building three delay values for each transition
into their design. The designer can experiment with delay values without modifying the
design.

Examples of min, typ, and max value specification for Verilog-XL are shown in Example
5-11.

Example 5-11 Min, Max, and Typical Delay Values

// One delay
// if +mindelays, delay= 4
// if +typdelays, delay= 5
// if +maxdelays, delay= 6
and #(4:5:6) a1(out, i1, i2);

// Two delays
// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2);

// Three delays
// if +mindelays, rise= 2 fall= 3 turn-off = 4
// if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6
and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);

Examples of invoking the Verilog-XL simulator with the command-line options are
shown below. Assume that the module with delays is declared in the file test.v.

//invoke simulation with maximum delay

> verilog test.v +maxdelays

//invoke simulation with minimum delay

> verilog test.v +mindelays

//invoke simulation with typical delay

> verilog test.v +typdelays

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5.2.3 Delay Example

Let us consider a simple example to illustrate the use of gate delays to model timing in
the logic circuits. A simple module called D implements the following logic equations:

out = (a b) + c

The gate-level implementation is shown in Module D (Figure 5-8). The module contains
two gates with delays of 5 and 4 time units.

Figure 5-8. Module D

The module D is defined in Verilog as shown in Example 5-12.

Example 5-12 Verilog Definition for Module D with Delay

// Define a simple combination module called D

module D (out, a, b, c);

// I/O port declarations

output out;
input a,b,c;

// Internal nets
wire e;

// Instantiate primitive gates to build the circuit

and #(5) a1(e, a, b); //Delay of 5 on gate a1
or #(4) o1(out, e,c); //Delay of 4 on gate o1

endmodule

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This module is tested by the stimulus file shown in Example 5-13.

Example 5-13 Stimulus for Module D with Delay

// Stimulus (top-level module)

module stimulus;

// Declare variables
reg A, B, C;
wire OUT;

// Instantiate the module D

D d1( OUT, A, B, C);

// Stimulate the inputs. Finish the simulation at 40 time units.

initial
begin
A= 1'b0; B= 1'b0; C= 1'b0;

#10 A= 1'b1; B= 1'b1; C= 1'b1;

#10 A= 1'b1; B= 1'b0; C= 1'b0;

#20 $finish;
end

endmodule

The waveforms from the simulation are shown in Figure 5-9 to illustrate the effect of
specifying delays on gates. The waveforms are not drawn to scale. However, simulation
time at each transition is specified below the transition.

1. The outputs E and OUT are initially unknown.

2. At time 10, after A, B, and C all transition to 1, OUT transitions to 1 after a delay
of 4 time units and E changes value to 1 after 5 time units.

3. At time 20, B and C transition to 0. E changes value to 0 after 5 time units, and
OUT transitions to 0, 4 time units after E changes.

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 Figure 5-9. Waveforms for Delay Simulation

It is a useful exercise to understand how the timing for each transition in the above
waveform corresponds to the gate delays shown in Module D.

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5.3 Summary

In this chapter, we discussed how to model gate-level logic in Verilog. We also discussed
different aspects of gate-level design.

• The basic types of gates are and, or, xor, buf, and not. Each gate has a logic
symbol, truth table, and a corresponding Verilog primitive. Primitives are
instantiated like modules except that they are predefined in Verilog. The output of
a gate is evaluated as soon as one of its inputs changes.

• Arrays of built-in primitive instances and user-defined modules can be defined in

Verilog.

• For gate-level design, start with the logic diagram, write the Verilog description
for the logic by using gate primitives, provide stimulus, and look at the output.
Two design examples, a 4-to-1 multiplexer and a 4-bit full adder, were discussed.
Each step of the design process was explained.

• Three types of delays are associated with gates: rise, fall, and turn-off. Verilog
allows specification of one, two, or three delays for each gate. Values of rise, fall,
and turn-off delays are computed by Verilog, based on the one, two, or three
delays specified.

• For each type of delay, a minimum, typical, and maximum value can be specified.
The user can choose which value to apply at simulation time. This provides the
flexibility to experiment with three delay values without changing the Verilog
code.

• The effect of propagation delay on waveforms was explained by the simple, two-
gate logic example. For each gate with a delay of t, the output changes t time units
after any of the inputs change.

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