Microprocessor and Microcontroller
INT Interrupt line, connected to INTR of microprocessor
INTA-
Interrupt ack, received active low from microprocessor
bar
IR0-7 Asynchronous IRQ input lines, generated by peripherals.
Block Diagram
Interrupt Request Register (IRR): The interrupts at IRQ input lines are
handled by Interrupt Request Register internally. IRR stores all the interrupt
requests in it in order to serve them one by one on the priority basis.
In-Service Register (ISR): This register stores all the interrupt requests
those are being served, i.e. ISR keeps a track of the requests being served.
Priority Resolver: This unit determines the priorities of the interrupt
requests appearing simultaneously. The highest priority is selected and stored
into the corresponding bit of ISR during INTA pulse. The IR0 has the highest
priority while the IR7 has the lowest one, normally in fixed priority mode.The
priorities however may be altered by programming the 8259A in rotating
priority mode.
Interrupt Mask Register (IMR): This register stores the bits required to
mask the interrupt puts. IMR operates on IRR at the direction of the Priority
Resolver.
Fig. 2.8 8259 Block Diagram
Interrupt Control Logic: This block manages the interrupt and interrupt
acknowledge signals to be sent to the CPU for serving one of the eight interrupt
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