Dr. N. Karuppiah & Dr. S.
Ravivarman
The Converter: The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter. The converter is designed to give fast,
accurate, and repeatable conversions over a wide range of temperatures. The
converter is partitioned into 3 major sections: the 256R ladder network, the
successive approximation register, and the comparator. The converter’s digital
outputs are positive true.
The 256R ladder network approach was chosen over the conventional R/2R
ladder because of its inherent monotonicity, which guarantees no missing
digital codes. Additionally, the 256R network does not cause load variations on
the reference voltage. The bottom resistor and the top resistor of the ladder
network are not the same value as the remainder of the network. The difference
in these resistors causes the output characteristic to be symmetrical with the
zero and full-scale points of the transfer curve. The first output transition
occurs when the analog signal has reached + 1 ⁄ 2 LSB and succeeding output
transitions occur every 1 LSB later up to full-scale.
Fig. 2.18 Functional Block Diagram
The successive approximation register (SAR) performs 8 iterations to
approximate the input voltage. For any SAR type converter, n-iterations are
required for an n-bit converter. The A/D converter’s successive approximation
register (SAR) is reset on the positive edge of the start conversion (SC) pulse.
The conversion is begun on the falling edge of the start conversion pulse. A
conversion in process will be interrupted by receipt of a new start conversion
pulse. Continuous conversion may be accomplished by tying the end-of-
conversion (EOC) output to the SC input. If used in this mode, an external start
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