Objective: (a) Transient analysis of BJT inverter.

(b) DC analysis (VTC) of BJT inverter.

Outcome: To analyze transient & DC analysis of BJT inverter using P-spice

Requirement of Software: P-spice, Model Editor.

Theory:-
BJT is a three terminal semiconductor device constructed with three doped semiconductor
regions that is base, collector, emitter separated by two p-n junction .Bipolar junction

E
transistor is a type of transistor that use both electron and hole as charge carriers. BJT works
in three operating regions.

C
1) cut off region
2) saturation region

E
3) active region

,
BJT works as a switch in cut- off and saturation region. In inverter application of BJT, if we

T
provide logic 1 at the input output gives logic zero and vice-versa.

E
VCC

I
4
R2
1k
3

M
Q1
VIN 1 R1
2 Q 40237
1k

BJT as INVERTER
Source Code:

(a) BJT Inverter

*Pulsed Input voltage.
VIN 1 0 PULSE (0 5 0 1MS 1MS 500MS 600MS)
VCC 4 0 DC 5V
Q1 3 2 0 Q40237
.MODEL Q40237 NPN(Is=69.28E-18 Xti=3 Eg=1.11 Vaf=100 Bf=288.5 Ne=1.186
+ Ise=69.28E-18 Ikf=22.4m Xtb=1.5 Br=1.143 Nc=2 Isc=0 Ikr=0 Rc=4
+ Cjc=893.1f Mjc=.3017 Vjc=.75 Fc=.5 Cje=939.8f Mje=.3453 Vje=.75
+ Tr=1.574n Tf=141.2p Itf=.27 Vtf=10 Xtf=30 Rb=10)
* National pid=42 case=TO72

E
* 88-09-07 bam creation
RB 1 2 10K
RC 4 3 1K

C
.TRAN 0 120US
.OP
.PROBE

E
.END

,
(b) BJT Inverter

VIN 1 0 DC 5V

T
VCC 4 0 DC 5V
Q1 3 2 0 Q40237

E
.MODEL Q40237 NPN(Is=69.28E-18 Xti=3 Eg=1.11 Vaf=100 Bf=288.5 Ne=1.186
+ Ise=69.28E-18 Ikf=22.4m Xtb=1.5 Br=1.143 Nc=2 Isc=0 Ikr=0 Rc=4

I
+ Cjc=893.1f Mjc=.3017 Vjc=.75 Fc=.5 Cje=939.8f Mje=.3453 Vje=.75
+ Tr=1.574n Tf=141.2p Itf=.27 Vtf=10 Xtf=30 Rb=10)
* National pid=42 case=TO72
* 88-09-07 bam creation

M
RB 1 2 10K
RC 4 3 1K
.DC VIN 0 5 0.1
.OP
.PROBE
.END

Result : The result has been verified.

 E
Fig 1: Transient Analysis of BJT Inverter

E C
T ,
IE
M Fig 2: DC Analysis of BJT inverter
 Questions

1. When a transistor is used in digital circuits, it operates in which region?

2. SPICE stands for?

3. What is meaning of transient?

4. What is step input?

5. What are transient and dc analysis?

6. What is simulation?

E
7. A transistor has a current gain of 0.99 in the CB mode. Its current gain

C
in the CC mode is….?

8. When the input to the inverter is high (+5 V). the base-emitter

E
junction is in which bias?

,
9. Why CE configuration is most popular in amplifier circuits?

10. Can a transistor be obtained by connecting tow semiconductor diodes

T
back-to-back?

IE
M
Objective: (a) Transient analysis of NMOS inverter using step input.

(b) Transient analysis of NMOS inverter using pulse input.

(c) DC analysis (VTC) of NMOS inverter.

Course Outcomes: To analyze NMOS inverter using step input using P-spice.

Requirement of Software: P-spice, Model Editor.

Theory: MOS logic so named because it uses metal oxide field effect transistor. They have

E
become very popular logic in comparison to the bipolar junction transistor. The NMOS
transistor is operated by creating inversion layer in P type transistor body. This inversion
layer called n channel created by applying voltage to the gate. In NMOS, positive gate

C
voltage is required for conduction that means for logic 1 it treated is ON and for logic 0 it
treated as OFF. The MOS logic circuits are simplest to fabricate and require very small space.

, E
VDD
1

T
R1
10k

E
2
M1
3

I
M2SK1044

V1
VG S

M
0

NMOS as INVERTER

Source Code:

(a) NMOS Inverter

*Pulsed Input voltage.
VGS 3 0 PULSE (0 5 0 1ns 1ns 20us 40us)
VDD 1 0 DC 5V
*NMOS with model M
M1 2 3 0 0 M2SK1044
* Model for NMOS with model M1
.Model M2SK1044 NMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
R1 1 2 10K
.TRAN 0 40us
.OP
.PROBE
.END

(b) NMOS Inverter

*Pulsed Input voltage.
VGS 3 0 PULSE (0 5 0 1ns 1ns 20us 40us)

E
VDD 1 0 DC 5V
*NMOS with model M
M1 2 3 0 0 M2SK1044

C
* Model for NMOS with model M1
.Model M2SK1044 NMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0

E
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919

,
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
R1 1 2 10K
. TRAN 0 160US

T
.OP
.PROBE

E
.END

I
(c) NMOS Inverter
VGS 3 0 DC 5V
VDD 1 0 DC 5V
*NMOS with model M

M
M1 2 3 0 0 M2SK1044
* Model for NMOS with model M1
.MODEL M2SK1044 NMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
R1 1 2 10K
.DC LIN VGS 0 5 0.1
.OP
.PROBE
.END

Result: The result had been verified.

 E
Fig 1: Transient Analysis of NMOS Inverter using step input

E C
T ,
IE
Fig 2: Transient Analysis of NMOS Inverter using pulse input

M
Fig 3: DC analysis of NMOS Inverter
 Questions

1. In which way NMOS is better than BJT?

2. What is the difference between depletion type and enhancement type

NMOS transistor?

3. Which is better in NMOS and PMOS?

4. MOSFET is also called IGFET. Why?

5. What is value of switching threshold voltage for an ideal inverter is

E
equal to if supply is V DD ?

C
6. What are the different layers in MOS transistor?

7. When the channel is said to be pinched off?

E
8. What are the steps involved in manufacturing of IC?

,
9. What is Body Effect?

10. Why is the substrate in NMOS connected to Ground and in PMOS to

T
VDD?

IE
M
Objective: (a) Analysis of CMOS inverter using pulse input.
(b) Transient Analysis of CMOS inverter using step input.
(c) DC analysis (VTC) of CMOS inverter without parameter.
(d) DC analysis (VTC) of CMOS inverter with parameter.

Course Outcomes: To analyze CMOS inverter using different inputs using P-spice.

Requirement of Software: P-spice, Model Editor.

E
Theory:

C
A CMOS is complimentary MOS transistor. This logic family is obtained by connecting p-
channel and n-channel MOSFET in series. MOS device is fabricated in the same chip, which

E
make its fabrication more complicated and packaged density. But it posses the important
advantage of higher speed and low power consumption. CMOS become popular in MSI and

,
LSI areas and is only possible logic for fabrication of VLSI design.

E T
I
VDD

1
M1
M2SJ102

M
2
3

R1
100k
V1 M2
VG S M2SK1044

0
0
0

CMOS as INVERTER

Source Code:

(a) CMOS Inverter

*Pulsed Input voltage.
VGS 3 0 PULSE (0 5 0 1NS 1NS 20US 40US)
VDD 1 0 DC 5V
M1 2 3 1 1 M2SJ102
.MODEL M2SJ102 PMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=2u Uo=300 Phi=.6 Kp=517.6n W=.55 L=2u Rs=20m Vto=-.8464
+ Rd=0 Rds=50K Cgso=266.4p Cgdo=684.2p Cbd=1.598n Mj=.5 Pb=.8
+ Fc=.5 Rg=43.92 Is=170.4E-18 N=.7688 Rb=51.08m)
R1 2 0 100K
M2 2 3 0 0 M2SK1044
.MODEL M2SK1044 NMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)

E
.TRAN 0 120US
.OP
.PROBE

C
.END

(b) CMOS Inverter

E
VGS 3 0 PULSE (0 5 0 1NS 1NS 20US 40US)

,
VDD 1 0 DC 5V
M1 2 3 1 1 M2SJ102
.MODEL M2SJ102 PMOS

T
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=2u Uo=300 Phi=.6 Kp=517.6n W=.55 L=2u Rs=20m Vto=-.8464

E
+ Rd=0 Rds=50K Cgso=266.4p Cgdo=684.2p Cbd=1.598n Mj=.5 Pb=.8
+ Fc=.5 Rg=43.92 Is=170.4E-18 N=.7688 Rb=51.08m)

I
R1 2 0 100K
M2 2 3 0 0 M2SK1044
.MODEL M2SK1044 NMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0

M
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
.TRAN 0 40US
.OP
.PROBE
.END

(c) CMOS Inverter

VGS 3 0 DC 5V
VDD 1 0 DC 5V
M1 2 3 1 1 M2SJ102
.MODEL M2SJ102 PMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=2u Uo=300 Phi=.6 Kp=517.6n W=.55 L=2u Rs=20m Vto=-.8464
+ Rd=0 Rds=50K Cgso=266.4p Cgdo=684.2p Cbd=1.598n Mj=.5 Pb=.8
+ Fc=.5 Rg=43.92 Is=170.4E-18 N=.7688 Rb=51.08m)
R1 2 0 100K
M2 2 3 0 0 M2SK1044
.MODEL M2SK1044 NMOS
(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
.DC LIN VGS 0 5 0.1
.OP
.PROBE
.END

E
(d) CMOS Inverter
VGS 3 0 DC 5V

C
VDD 1 0 DC 5V
M1 2 3 1 1 M2SJ102
.MODEL M2SJ102 PMOS

E
(+ LEVEL=3 L=2.0000E-6 W=.5 RS=10.000E-3 RD=10.000E-3 VTO=3 RDS=1.0000E6
+ TOX=2.0000E-6 CGSO=40.000E-12 CGDO=10.000E-12 CBD=1.0000E-9 RG=5

,
+ RB=1.0000E-3 GAMMA=0 KAPPA=0)
RL 2 0 100K
M2 2 3 0 0 M2SK1044

T
.MODEL M2SK1044 NMOS
(+ LEVEL=3 L=2.0000E-6 W=.5 RS=10.000E-3 RD=10.000E-3 VTO=3 RDS=1.0000E6

E
+ TOX=2.0000E-6 CGSO=40.000E-12 CGDO=10.000E-12 CBD=1.0000E-9 RG=5
+ RB=1.0000E-3 GAMMA=0 KAPPA=0)

I
.DC LIN VGS 0 5 0.1
.STEP LIN NMOS M2SK1044(VTO) 0 5 1
.OP
.PROBE

M
.END

Result: The result has been verified.

 E
Fig 1: Transient Analysis of CMOS Inverter using step input

E C
T ,
IE
Fig 2: Transient Analysis of CMOS inverter using pulse input

M
Fig 3: DC Analysis of CMOS inverter using pulse input without parameter
Fig 4: DC Analysis of CMOS inverter with parameter

C E
, E
E T
I
M
 Questions
1. What is the full form of CMOS?
2. What are two important characteristics of CMOS transistor?
3. If W/L ratio of CMOS is increased, what is the effect upon propagation delay?
4. If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured
at….?
5. What will be the effect on output voltage if the positions of n-MOS and p-MOS in CMOS
inverter circuit are exchanged?

E
6. In the CMOS inverter the output voltage is measured across..?
7. When the input of the CMOS inverter is equal to Inverter Threshold Voltage V th , both

C
transistors are operating in which region?
8. What is the value of Noise margin of typical CMOS inverter approximately?

E
9. On which parameter does the fan-out of CMOS depend?
10. In CMOS logic circuit, why switching operation occurs?

T ,
IE
M
Objective: (a) Transient Analysis of NOR Gate inverter.
(b) DC analysis (VTC) of NOR Gate inverter.

Course Outcomes : To analyze Transient &DC characterstics of NOR Gate inverter using
P- spice

Requirement of Software: P-spice, Model Editor.

Theory: NOR gate is one of the logic gates to perform the digital operation on the input
signals. It is the combination of OR Gate followed by NOT gate.

E
For the design of any circuit with the CMOS technology, we need parallel or series
connections of NMOS and PMOS with a NMOS source tied directly or indirectly to ground

C
and a PMOS source tied directly or indirectly to VDD.
The circuit shows the realization of CMOS NOR gate which consists of two PMOS and two

E
NMOS gates. Here in this circuit when we provide low logic on VGS, then the two PMOS will

,
be short circuited and two NMOS will be open circuited. The output VOUT will be shorted to
VDD and produces ONE output.When we provide high logic on VGS, then the two PMOS

T
will be open circuited and two NMOS will be short circuited. In this case path establishes
from VOUT to GND through NMOS, but no path to VDD. So, VOUT will be at LOW level.

E
VDD

I
1
M2SJ102

M1

M
VGS 2
3
M2SJ102

M2
4 O/P

VGS M3
M4
VGS
M2SK1045
M2SK1045

0
0

NOR gate inverter through CMOS.

Source Code:
(a) NOR Gate Inverter
*Pulsed Input voltage.
VGS 2 0 PULSE (0 5 0 1NS 1NS 20US 40US)
VDD 1 0 DC 5V
M1 3 2 1 1 M2SJ102
M2 4 2 3 3 M2SJ102
.Model M2SJ102 PMOS (Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0
Xj=0
+ Tox=2u Uo=300 Phi=.6 Kp=517.6n W=.55 L=2u Rs=20m Vto=-.8464
+ Rd=0 Rds=50K Cgso=266.4p Cgdo=684.2p Cbd=1.598n Mj=.5 Pb=.8
+ Fc=.5 Rg=43.92 Is=170.4E-18 N=.7688 Rb=51.08m)
M3 4 2 0 0 M2SK1044
M4 4 2 0 0 M2SK1044

E
.Model M2SK1044 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0
Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293

C
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
.TRAN 0 120US

E
.OP
.PROBE

,
.END

(b) NOR Gate Inverter

T
VGS 2 0 DC 5V
VDD 1 0 DC 5V

E
M1 3 2 1 1 M2SJ102
M2 4 2 3 3 M2SJ102

I
.Model M2SJ102 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0
Xj=0
+ Tox=2u Uo=300 Phi=.6 Kp=517.6n W=.55 L=2u Rs=20m Vto=-.8464
+ Rd=0 Rds=50K Cgso=266.4p Cgdo=684.2p Cbd=1.598n Mj=.5 Pb=.8

M
+ Fc=.5 Rg=43.92 Is=170.4E-18 N=.7688 Rb=51.08m)
M3 4 2 0 0 M2SK1044
M4 4 2 0 0 M2SK1044
.Model M2SK1044 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0
Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
.DC LIN Vgs 0 5 0.1
.OP
.PROBE
.END

Result : The result has been verified.

 C E
, E
E T
I
M
 Questions

1. Why NOR gate is also called universal logic gate?

2. In negative convention, the Boolean logic 1 is equivalent to..?
3. Which gate is faster NAND or NOR?
4. How threshold voltage of NMOS can be increased?
5. In MOSFET operating in saturation region, the channel length
modulation causes?

E
6. The gate oxide in CMOS process is preferably grown by using..?
7. Which process is preferred to form SiO2 of MOSFET?

C
8. Why we prefer enhancement MOSFET over depletion MOSFET?
9. Why do we prefer NAND over NOR?

, E
E T
I
M
Objective: (a) Transient Analysis of NAND Gate inverter.
(b) DC analysis (VTC) of NAND Gate inverter.

Course Outcomes : To analyze Transient &DC characteristics of NAND Gate inverter using

P-spice.

Requirement of Software: P-spice, Model Editor.

Theory: NAND gate is one of the basic logic gates to perform the digital operation on the
input signals. It is the combination of AND Gate followed by NOT gate.

E
For the design of any circuit with the CMOS technology, we need parallel or series
connections of NMOS and PMOS with a NMOS source tied directly or indirectly to ground

C
and a PMOS source tied directly or indirectly to VDD.
The circuit shows the realization of CMOS NAND gate which consists of two PMOS and

E
two NMOS gates. Here in this circuit when we provide low logic , then the two PMOS will

,
be short circuited and two NMOS will be open circuited. The output Vout will be shorted to
VDD and produces ONE output. When we provide High logic on V GS, then the two PMOS

T
will be open circuited and two NMOS will be short circuited. In this case path establishes
from VOUT to GND through NMOS, but no path to VDD. So, VOUT will be at LOW level.

IE
VDD
1

M2SJ102 M2SJ102
VGS

M
M1 M2

3 VOUT
VGS 2 M3

M2SK1044

M4

M2SK1044

NAND gate inverter through CMOS.

Source Code:
(a) NAND Gate
*Pulsed Input voltage.
VGS 2 0 PULSE (0 5 0 1NS 1NS 20US 40US)
VDD 4 0 DC 5V
M1 3 2 1 1 M2SJ102
M2 3 2 1 1 M2SJ102
.model M2SJ102 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0
Xj=0
+ Tox=2u Uo=300 Phi=.6 Kp=517.6n W=.55 L=2u Rs=20m Vto=-.8464
+ Rd=0 Rds=50K Cgso=266.4p Cgdo=684.2p Cbd=1.598n Mj=.5 Pb=.8
+ Fc=.5 Rg=43.92 Is=170.4E-18 N=.7688 Rb=51.08m)

E
M3 3 2 4 4 M2SK1044
M4 4 2 0 0 M2SK1044
.model M2SK1044 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0

C
Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919

E
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
.TRAN 0 120US

,
.OP
.PROBE
.END

T
(b) NAND Gate

E
VGS 2 0 DC 5V
VDD 1 0 DC 5V

I
M1 3 2 1 1 M2SJ102
M2 3 2 1 1 M2SJ102
.model M2SJ102 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0
Xj=0

M
+ Tox=2u Uo=300 Phi=.6 Kp=517.6n W=.55 L=2u Rs=20m Vto=-.8464
+ Rd=0 Rds=50K Cgso=266.4p Cgdo=684.2p Cbd=1.598n Mj=.5 Pb=.8
+ Fc=.5 Rg=43.92 Is=170.4E-18 N=.7688 Rb=51.08m)
M3 3 2 4 4 M2SK1044
M4 4 2 0 0 M2SK1044
.model M2SK1044 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0
Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
.DC LIN VGS 0 5 0.1
.OP
.PROBE
.END

Result : The result has been verified.

 Fig 1: Transisent Analysis of NAND gate Inverter

C E
, E
E T
I
M Fig 2: DC Analysis of NAND gate Inverter
 Questions

1. Why NAND gate is also called universal logic gate?

2. In CMOS NAND gate, p transistors are connected in..?

3. As the number of inputs increases, the NAND gate delays..?

4. Draw CMOS input and output characteristics?

5. What do we observe from transient and DC analysis of NAND gate?

E
6. An important parameter of logic gate circuitry is noise margin. What exactly is “noise margin,” and
how is it defined for logic gates?

C
7. In CMOS circuitry, one side of the DC power supply is usually labeled as “V DD ”, while the other
side is labeled as “V SS ”. Why is this? What do the subscripts “DD” and “SS” represent?

E
8. A problem unique to certain types of CMOS logic gates is something called SCR latch up. Explain

,
what this phenomenon is, and what causes it.

9. What logic state does a floating CMOS gate input naturally assume? How does this compare

T
against traditional TTL?

IE
M
Objective:- Design and Simulation of a Differential Amplifier

Outcome: To model a Differential Amplifier for simulation (with Resistive Load, Current
Source Biasing).

Requirement of software:- P-spice, Model Editor

Theory:-
In a differential amplifier for constant IE, RE should be very large. This also increases the
value of CMRR but if RE value is increased to very large value, IE (quiescent operating

E
current) decreases. To maintain same value of IE, the emitter supply VEE must be increased.
To get very high value of resistance RE and constant IE, current, current bias is used.

E C
T ,
IE
M Differential amplifier with constant current biasing
Source Code:
Design and simulation of differential amplifier

VS 1 2 AC 1 SIN (0 10MVPEAK 10KHZ)

VCM 2 0 SIN (0 10MVPEAK 5KHZ)

VCC 11 0 DC +15V

VDD 12 0 DC -15V

Q1 3 1 5 Q2N2222

E
Q2 4 2 5 Q2N2222

.MODEL Q2N2222 NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307

C
+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1

E
+ Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75

,
+ Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

* National pid=19 case=TO18

T
* 88-09-07 bam creation

E
RC1 11 3 1K

I
RC2 11 4 1K

RE 5 12 7.2K

M
.TRAN 5US 200US

.AC DEC 5 1K 100MEG

.PRINT TRAN V(3)

.PRINT AC V(3)

.PROBE

.END

We can simulate it P-spice and observe its response.

Result: It has been simulated on P-spice successfully.

 Fig 1- Transient Analysis of Differential Amplifier

C E
, E
Questions

T
1. When a differential amplifier is operated single-ended, the output is?

E
2. What is a differential amplifier?

I
3. If ADM = 3500 and ACM = 0.35, the CMRR is ……….

4. With zero volts on both inputs, an OP-amp ideally should have an

M
output ………..

5. the most realistic value for open-loop voltage gain of an OP-amp is

……

6. The tail current of a differential amplifier is …….

7. what is the value of input impedance of a differential amplifier in

beta terms?

8. The input stage of an Op-amp is usually a ……….

Objective:- Analysis of frequency response of Common Source Amplifiers.

Outcome: To Analyze frequency response of common source amplifiers.

Requirement of software:- P-spice, Model Editor

Theory:-Metal Oxide Semiconductor Field Effect Transistor,or MOSFET for short, is an

excellent choice for small signal linear amplifiers as their input impedance is extremely high
making them easy to bias but for a MOSFET to produce linear amplification, it has to operate
in its saturation region, unlike the Bipolar Junction Transistor. But just like the BJT, it too
needs to be biased around a centrally fixed Q-point.

E
We can control how the MOSFET operates by creating or enhancing its conductive channel
between the source and drain region producing a type of MOSFET commonly called an n-
channel Enhancement-mode MOSFET, which simply means that unless we bias them

C
positively on the gate(negatively for p-channel), no channel current will flow.

Enhancement MOSFET,E-MOSFET can be classed as normally-off (non-conducting)

E
devices, that is they only conduct when a suitable gate-to-source positive is applied, unlike
Depletion type MOSFET which are normally on device conducting when the gate voltage is

,
zero.
Frequency response of electric or electronics circuit allows us to see exactly how the output
gain (known as the magnitude response) and the phase (known as the phase response) change

T
at a particular single frequency, or over a whole range of different frequencies from 0 Hz,(dc)
to many thousands of mega-hertz,(MHz) depending upon the design characteristics of the

E
circuit.
Below fig. shows an n-channel enhancement type MOSFET amplifier with series-shunt

I
feedback.

M
A MOSFET feedback Amplifier
Source Code:

VIN 1 7 AC 10MV

VDD 8 0 15V

RS 1 2 250

C1 2 3 1UF

R1 8 3 1.4MEG

E
R2 3 0 1MEG

RD 8 4 15K

C
RS1 5 9 100

E
RS2 9 0 15K

,
CS 9 0 20UF

C2 4 6 0.1UF

T
R3 6 7 15K

E
R4 7 0 5K

I
RL 6 0 10K

M1 4 3 5 5 M2n7000

M
.MODEL M2n7000 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2
Vmax=0 Xj=0

+ Tox=2u Uo=600 Phi=.6 Kp=1.073u W=.12 L=2u Rs=20m Vto=1.73

+ Rd=.5489 Rds=48MEG Cgso=73.61p Cgdo=6.487p Cbd=74.46p Mj=.5

+ Pb=.8 Fc=.5 Rg=546.2 Is=10f N=1 Rb=1m)

.AC DEC 10 10HZ 100MEGHZ

.PLOT AC VM(6)

.OP

.PROBE

.END

Result: It has been simulated on P-spice successfully.

 C E
E
Fig1:- Output of Common Source MOSFET feedback amplifier

,
Questions

E T
1. When gate to source voltage of common source amplifier is at positive peak, what will be

I
drain to source voltage.

2. With which Common source amplifier's source is connected to ?

M
3. D-MOSFET in case of common source amplifier can operate with gate to source voltage
zero at which point?

4. If a certain amplifier has DC drain resistance of 1.0k Ω where load resistance of 1.0k Ω is
capacitively coupled to the drain, than gain become ?

5. A common source amplifier has ?

6. What is frequency response?

7. What is common source amplifier?

Objective:- Analysis of frequency response of source follower amplifiers.

Outcome:- To Analyze of frequency response of cascade FET amplifiers

Requirement of software:- P-spice, Model Editor

Theory:-

In electronics, a common-drain amplifier, also known as a source follower, is one of three

basic single-stage field effect transistor (FET) amplifier topologies, typically used as a
voltage buffer.

C E
, E
E T
I
M
Source follower amplifier

typical implementation of the common drain or source follower / buffer circuit is very easy to
realize in a practical fashion.
The circuit show below gives a typical example of a FET source follower / buffer circuit. The
capacitors C1 and C2 are used to couple the AC signal between stages and block the DC
elements. The resistor R1 provides the gate bias, holding he gate at ground potential. The
source circuit shows the resistor R2 to ground - its value is determined by the channel current
that is required
Source Code:

VIN 1 0 AC 1.8V
VDD 3 0 DC 5V
C1 1 2 10UF
R1 3 2 50K
R2 4 0 1K
R3 2 0 100K
M 3 2 4 4 M2SK1044
.model M2SK1044 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0

E
Xj=0
+ Tox=2u Uo=600 Phi=.6 Kp=1.022u W=3.8 L=2u Rs=20m Vto=3.293
+ Rd=1.413 Rds=800K Cgso=366.9p Cgdo=24.34p Cbd=2.781n Mj=.7919

C
+ Pb=.3905 Fc=.5 Rg=0 Is=10f N=1 Rb=1m)
.AC DEC 10 10HZ 10MEGHZ
.OP

E
.PROBE
.END

T ,
Result: It has been simulated on P-spice successfully.

IE
M
Fig 1: Frequency response of source follower amplifier
 Questions

1. What is meaning of source follower circuit?

2. The input output characteristic of an amplifier is ..?

3.In MOSFET amplifier, the input is applied as:

4. In MOSFET amplifier, the parameter that changes due to the changes in input is …?

E
5. Input impedance of MOSFET amplifier in Common Source configuration is..?

6. What is the voltage gain of the MOSFET ?

C
7.The MOSFET is said to be in diode connected configuration if:..?

8. The diode connected MOSFET acts as..?

, E
E T
I
M
Objective: Analysis of frequency response of cascode amplifier

Outcome: - To analyze frequency response of cascode amplifier

Requirement of Software: P-spice, Model Editor.

Theory: The cascode is a two-stage amplifier that consists of a common-emitter stage feeding
into a common-base stage.

Compared to a single amplifier stage, this combination may have one or more of the following
characteristics: higher input–output isolation, higher input impedance, high output impedance,

E
higher bandwidth.The cascode arrangement is also very stable

E C
T ,
IE
M
Cascode Amplifier

Source Code:
V1 1 0 DC 11.5V

V2 4 6 AC .5V

V3 6 0 DC 1.5V

C1 2 0 10NF

C2 4 5 10NF

R1 1 2 80K

R2 5 6 80K

Q1 3 2 7 Q40237
Q2 7 5 0 Q40237

.model Q40237 NPN(Is=69.28E-18 Xti=3 Eg=1.11 Vaf=100 Bf=288.5 Ne=1.186

+ Ise=69.28E-18 Ikf=22.4m Xtb=1.5 Br=1.143 Nc=2 Isc=0 Ikr=0 Rc=4

+ Cjc=893.1f Mjc=.3017 Vjc=.75 Fc=.5 Cje=939.8f Mje=.3453 Vje=.75

+ Tr=1.574n Tf=141.2p Itf=.27 Vtf=10 Xtf=30 Rb=10)

* National pid=42 case=TO72

* 88-09-07 bam creation

E
R3 3 8 4.7K

C
V4 8 0 DC 20V

.AC DEC 10 10HZ 10MEGHZ

E
.OP

,
.PROBE

T
.END

Result: The result had been verified.

IE
M
Fig 1:Analysis of frequency response of cascade amplifiers
 QUESTIONS

1. A radio receiver has …………… of amplification.

a) One stage

b)Two stages

c)Three stages

d) More than one stages

2.The cascade amplifier is a multistage configuration of which?..

E
3.In obtaining the frequency response curve of an amplifier, the …………

C
a) Amplifier level output is kept constant

b) Amplifier frequency is held constant

E
c) Generator frequency is held constant

,
d) Generator output level is held constant

4. The best frequency response is of ………. coupling.

T
5. Transformer coupling is used for ………….. amplification

E
6. In an RC coupling scheme, the coupling capacitor CC must be large enough

I
………..

7. In RC coupling, the value of coupling capacitor is about ……….

M
8. The noise factor of an ideal amplifier expressed in db is …………..

9. When a multistage amplifier is to amplify d.c. signal, then one must use ……..

coupling.

10.In practice, voltage gain is expressed ……………

Objective: Analysis of frequency response of Differential amplifier.

Course Outcomes: To Analyze of frequency response of Differential amplifiers.

Requirement of Software: P-spice, Model Editor.

Theory: The electronic amplifier used for amplifying the difference between two input
signals can be called as a differential amplifier. In general, these differential amplifier cinsist
of two terminals namely inverting terminal and non-inverting terminal these inverting and
non inverting terminals are represented with –and + respectively.

On the other hand, an Op-Amp operating in differential mode can readily act differential

E
amplifier as it result in an out voltage given by V0=(V1-V2) where V1 and V2 represent the
voltage applied at its inverting and non inverting input terminals (can be taken in any order)

C
and Ad refers to its differential gain. As per this equation, the output of the Op-Amp must be
zero when the voltage applied at its terminals is equal to each other. However practically it
will not be so as the gain will not be same for both or the input.

, E
E T
I
M
Differential Amplifier
Design and simulation of differential amplifier

VS 1 2 AC 1 SIN (0 10MVPEAK 10KHZ)

VCM 2 0 SIN (0 10MVPEAK 5KHZ)

VCC 11 0 DC +15V

VDD 12 0 DC -15V

Q1 3 1 5 Q2N2222

Q2 4 2 5 Q2N2222

E
.model Q2N2222 NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307

+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1

C
+ Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75

E
+ Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10)

,
* National pid=19 case=TO18

* 88-09-07 bam creation

T
RC1 11 3 1K

E
RC2 11 4 1K

I
RE 5 12 7.2K

.TRAN 5US 200US

.AC DEC 5 1K 100MEG

M
.PRINT TRAN V(3)

.PRINT AC V(3)

.PROBE

.END

Result: The result had been verified.

 Fig 1- AC Analysis of Differential Amplifier

C E
E
Questions

,
1. What is frequency response of differential amplifier?

T
2. An ________, or op-amp, is a differential amplifier with very high

E
differential-mode gain, very high input impedances, and a low output

I
impedance.
3. How many types of plots can be obtained in the AC analysis of network
using bode plot?

M
4. What happens when the operating frequency of an op amp increase?
5. Which technique is used to determine the stability of op amp?
6. In the freqency response plot, the frequency is expressed in?
7. What is a graph of the magnitude of the gain versus frequency?
 C E
, E
E T
I
M