School

of
Electronics and Communication Engineering

Institutional Research Project Report

on
3-BIT PIPELINE ANALOG TO DIGITAL
CONVERTER

By:

1. Ramya S Patil USN:01FE20BEC119

2. Akash S Upase USN:01FE20BEC156
3. Kshetrapal S Baligar USN:01FE20BEC160
4. Sagar Tugashetti USN:01FE20BEC163

Semester: VII, 2023-2024

Under the Guidance of

Dr. Sujata S Kotabagi

1
 K.L.E SOCIETY’S
KLE Technological University,
HUBBALLI-580031
2023-2024

SCHOOL OF ELECTRONICS AND COMMUNICATION

ENGINEERING

CERTIFICATE

This is to certify that project entitled “ 3-BIT PIPELINE ANALOG TO DIGITAL

CONVERTER ” is a bonafide work carried out by the student team of ”Akash S
Upase[01FE20BEC156], Kshetrapal Baligar [01FE20BEC160], Ramya S Patil
[01FE20BEC119], Sagar Tugashetti[01FE20BEC163]”. The project report has
been approved as it satisfies the requirements concerning Institutional research project
work prescribed by the university curriculum for BE (VII Semester) in the School of
Electronics and Communication Engineering of KLE Technological University for the
academic year 2023-2024.

Dr. Sujata S Kotabagi Dr.Suneeta V. Budihal Dr.Basavaraj S A

Guide Head of School Registrar

External Viva:

Name of Examiners Signature with date

1.

2.

2
 ACKNOWLEDGMENT

The contentment that lies with effectively completing the ”3-

BIT PIPELINE ANALOG TO DIGITAL CONVERTER” would
be insufficient without citing the names of individuals who made
a huge difference in the completion of this project. Their consis-
tent guidance, support, and encouragement helped us a lot for the
project to come to fruition.

We are grateful to our reputable university, KLE Technological

University, Hubballi, for giving us the chance to realize our greatest
aspiration. We want to thank our Head of School of Electronics
and Communication, Dr.Suneeta V. Budihal from the bottom of
our hearts for giving us the guidance and inspiration that was
necessary to see this project through to completion.

We sincerely thank you for the recommendations and support

provided by our guide, Dr. Sujata S Kotabagi for guidance and
support. We also acknowledge the assistance and support provided
by the entire Prakalp team in finishing our project.

Finally, we would express our deep sense of gratitude to everyone

who has extended their helping hand, Acknowledged, encouraged,
and helped in our endeavor.

-Akash S Upase, Ramya S Patil , Kshetrapal S Baligar , Sagar

Tugashetti

3
 ABSTRACT

These days, several applications demand high-performance data

converters. Gainful parameters for sampling rate, resolution, and
power dissipation should be present in these data converters. These
are the required ADC specifications for broadband transceivers,
wireless communication applications, and numerous other digital
devices. The goal of this research is to produce pipeline architecture
ADCs that have excellent resolution, fast processing speeds, and
low power consumption.

The project presents a 3 bit, 100MSPs Pipeline analog to digital

converter. A bootstrapped switch is utilized to sample the input
signal. Bootstrapping minimizes power penalty while improving
speed and reducing distortion in the sample and hold circuits. 0V
to 0.7V is the achieved input voltage range. ADC’s comparator
circuit is developed with a 7-pack, 150 MHz opamp. Residue am-
plifier is used in the circuit to increase the gain.

In this project, a 180nm-based Cadence Virtuoso software tool

is used to design a 3-bit ADC with 1-bit resolution at each stage.
An operational amplifier is the fundamental building element of
a pipeline design. The supply voltage of 1.8V is used by pipeline
architecture and Opamp.

4
Contents

1 Introduction 10
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Literature survey . . . . . . . . . . . . . . . . . . . 11
1.4 Problem statement . . . . . . . . . . . . . . . . . . 12
1.5 ADC Performance Parameters . . . . . . . . . . . . 12
1.6 Organization of the report . . . . . . . . . . . . . . 14

2 System design 15
2.1 Block diagram and Methodology . . . . . . . . . . 15
2.2 Functional Block Diagram . . . . . . . . . . . . . . 16
2.2.1 7-pack Operational Amplifier . . . . . . . . 16
2.2.2 Sample and Hold Circuit . . . . . . . . . . . 17
2.2.3 Comparator . . . . . . . . . . . . . . . . . 18
2.2.4 Subtractor . . . . . . . . . . . . . . . . . . 19
2.2.5 Residue Amplifier . . . . . . . . . . . . . . 19
2.2.6 Single Stage Pipeline ADC . . . . . . . . . . 20
2.2.7 3-bit Pipeline ADC . . . . . . . . . . . . . . 20

3 Implementation details 21
3.1 Specifications . . . . . . . . . . . . . . . . . . . . . 21
3.2 Design Algorithm . . . . . . . . . . . . . . . . . . 21
3.3 Working of Pipeline ADC . . . . . . . . . . . . . . 22

4 Results and discussions 23

5
 4.1 Output Of 7-Pack opamp . . . . . . . . . . . . . . 23
4.2 Output of Sample and Hold . . . . . . . . . . . . . 24
4.3 Output Of Comparator . . . . . . . . . . . . . . . 24
4.4 Output Of Subtractor . . . . . . . . . . . . . . . . 25
4.5 Output Of Residue Amplifier . . . . . . . . . . . . 25
4.6 Output Of Complete 3-bit Pipeline ADC . . . . . . 26

5 Conclusions and future scope 27

5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Future scope . . . . . . . . . . . . . . . . . . . . . 27

6 Bibliography 28

6
List of Tables

3.1 Design specification of 7-pack opamp . . . . . . . . 21

7
List of Figures

2.1 Functional block diagram of the circuit . . . . . . . 15

2.2 7-pack opamp circuit . . . . . . . . . . . . . . . . . 16
2.3 Sample and Hold Circuit . . . . . . . . . . . . . . . 17
2.4 Comparator Circuit . . . . . . . . . . . . . . . . . 18
2.5 Subtractor Circuit . . . . . . . . . . . . . . . . . . 19
2.6 Residue Amplifier Circuit . . . . . . . . . . . . . . 19
2.7 1-bit pipeline ADC Circuit . . . . . . . . . . . . . 20
2.8 3-bit pipeline ADC Circuit . . . . . . . . . . . . . 20
4.1 Gain of 7-pack operational amplifier . . . . . . . . . 23
4.2 Output Waveform of Sample and hold circuit . . . . 24
4.3 Output Waveform of Comparator circuit . . . . . . 24
4.4 Output Waveform of Subtractor circuit . . . . . . . 25
4.5 Output Waveform of Residue Amplifier circuit . . . 25
4.6 Output Waveform of 3-bit Pipeline ADC circuit . . 26

8
Chapter 1

Introduction

Digital blocks have become more popular than analog blocks in IC designs
because to their ease of processing, simplicity in design, precision, and
low power consumption. ADCs are practically always used for converting,
processing, and storing an analog signal as a digital signal. The primary
drivers behind the digitalization of electronic systems are their strong anti-
interference capabilities, great stability, vast adaptability, and low sensi-
tivity to noise. Pipeline ADC, Flash ADC, SAR ADC, Sigma Delta ADC,
etc. are some examples of ADC architectures. The appealing combination
of low power consumption, high resolution, and high speed is provided
by the pipelined analog-to-digital converter architecture. For low-power
applications, like as wireless communication systems, the pipelined ADC
serves as the best option. Pipeline architecture facilitates power reduction,
digital error correction via capacitor scaling, and digital gain calibration.
Pipeline ADC is therefore appropriate for applications requiring high res-
olution and high speed.

1.1 Motivation
Due to a rise in bandwidth demand brought on by quicker on-chip pro-
cessing and denser circuitry, serial input/output (I/O) data rates have
topped 10Gbits/second (Gb/s). Analog-to-digital converter (ADC) based
receivers with digital signal processing (DSP) are becoming more popu-
lar. In addition to ADCs, digital-to-analog converters (DAC) are in high
demand.DACs convert discrete digital signals into continuous analog im-
pulses. Capacitive DACs are the preferred DAC architecture because of
its simplified power, improved matching, and simpler construction. Ca-
pacitive DACs are only recommended over resistive and current steering

9
DACs in situations needing medium to high resolution. The Capacitive
DAC-based approach has a lot of benefits, but there are still issues with
parasitic capacitance, capacitor mismatch, and capacitor sizing that af-
fect DAC performance. Digital solutions will become more flexible and
portable between IC fabrication processes as technology develops, which
will ultimately result in lower power and cost.

1.2 Objectives

1. To design a low-power 3-bit Pipeline ADC with high conversion speed

in 180nm technology.
2. The Pipeline ADC has to be designed to support a low input voltage
range.

1.3 Literature survey

To understand the existing works in the context of the proposed idea, some
papers are discussed below.
[1] The work likely focuses on the design and implementation of a 4-bit
pipeline analog-to-digital converter (ADC) using CMOS technology that
ensures fast speed with the usage of operational amplifiers and reduces
power consumption.
[2] The design of a 4-bit pipeline ADC in less than 0.18 µm CMOS tech-
nology was examined in this work. The need for small-sized, low-power,
high-speed analog-to-digital converters that lower power consumption and
die size has increased due to the rapid improvement of CMOS manufactur-
ing technology and the ongoing spread of mixed analog and digital VLSI
systems.
[3] This paper describes a 1.5-V, 10-bit, 200-MS/s CMOS Pipeline Analog-
to-Digital Converter. A high resolution at a high sampling frequency is
used in this pipeline architecture. The sharing of the amplifier is shown in
this particular paper.
[4]This paper represents pipeline ADC 8 bits, 20 Msamples/s was im-
plemented in 0.6 µm technology with total power dissipation of 75.47 mW.
Referring to the result of the experiment, the ADC can be implemented

10
for video rate applications. The system uses clock management to manage
data conversion so that the system is simple and has good precision.
[5] This research presents an enhanced design and comparative analysis
of low-power operational amplifiers that use an NMOS current mirror as a
bias circuit, as reported in the cited publication. The CADENCE 180nm
CMOS process, which is necessary for designing pipeline adc, was used to
design the updated circuit.
[6]The article describes a DTMOS-based 16 bit 100 MS/s SAR ADC
for biomedical implant systems with a 1V power supply. DTMOS logic
uses little electricity.This device consists of a digital SAR logic with low
leakage, an R-2R DAC, and a low power comparator.
[7] This paper provides the Circuit techniques for low-voltage and high-
speed A/D converters where the signal range has the largest effect on the
opamps, making the use of a rail-to-rail output stage mandatory. The
applications of the SO technique are also discussed to improve speed.

1.4 Problem statement

”Design a 3-bit, 100MS/s Pipeline Analog to Digital Converter using the

bootstrapped switch in 180nm technology for low power application.”

1.5 ADC Performance Parameters

• Resolution: The smallest incremental voltage that an ADC can detect

and consequently produce a change in digital output is referred to as the
resolution of the ADC. It is referred to as the amount of bits the ADC
outputs.

• Offset Error: It is visible when the DAC produces an output while the
input is 00000000. Because of this, the output curve and the ideal output
curve are not regularly matched.

• Gain error: Once the offset error has been removed, the difference be-
tween the ideal and actual curves at full scale is referred to as the gain error.

11
 • Accuracy: How many bits are reproducible from conversion to con-
version is referred to as a converter’s accuracy. In other words, accuracy
measures how accurately the ADC’s output corresponds to the input.

• Integral nonlinearity Error: The integral nonlinearity error is defined

as the deviation from the ideal straight line after offset and gain errors
have been taken into account. Traditionally, the ”best fit” straight line
linking the first and last code transition endpoints is used to establish the
straight(ideal) line.

• Differential nonlinearity error (DNL): It is the difference between the

actual code width of an ideal converter and that of a non-ideal converter.

• Missing codes: The output code that is missing from the transfer func-
tion when no input voltage value can produce the intended output code is
known as the missing code.

• Dynamic Range: The ratio of the converter’s largest output signal

to its smallest output signal (1LSB) is known as the dynamic range. The
following equation can be used to represent dynamic range as shown:
Dynamic rang=20log10(ratio).

• Signal-to-noise ratio(SNR): The ratio of the strength of the fundamen-

tal to the overall noise power minus the harmonic components is known
as the signal-to-noise ratio. It is written in a database. The SNR covers
all of the Nyquist interval’s noise. It might be influenced by the incoming
signal’s frequency. It can be mathematically written as:
SNR=10log(SignalPower/total noise floor power)

• Signal to Noise plus Distortion(SNDR): The fundamental to total

noise plus harmonic power ratio is known as the SNDR. It is written in a
database. Mathematically it can be written as
SNDR=10log(SignalPower/noise+Harmonic Power)

• Effective Number of Bits(ENOB): The highest signal-to-noise + dis-

tortion ratio is calculated by ENOB using bits.The relation between SNDR
in db and ENOB is

12
ENOB=(SINADdb-1.76)/6.02

• Total Harmonic Distortion(THD): THD is defined as the fundamental

power divided by the total power of harmonic distortion. It is expressed
in db.
THD=10log(SignalPower)/(noise +Total Harmonic Power)

• Spurious Free Dynamic Range(SFDR): The difference between the

strength of the signal and the strongest spurious frequency component is
used to determine the SFDR.The SFDR is often stated in dB. Mathemat-
ically it can be expressed as
SFDR=10log(Signal Power)/(Power of largest spurious frequency)

1.6 Organization of the report

So far, the proposed work has described the introduction, the motivation,
and the objectives of the assigned problem

Chapter 2 The System Design describes the block diagram of the pro-
posed solution.

Chapter 3 Implementation details describe the specifications and design.

Chapter 4 Results and Discussion describes the results and analysis. It

talks about the differences in required and obtained results.

Chapter 6 Conclusions and Future Scope contains the conclusion of the

project with a discussion on the future scope‘ and its applications.

13
Chapter 2

System design

In this chapter, The block diagram and methodology of the system are
discussed. Later, all the individual blocks such as the bootstrapped sam-
ple and hold circuit, 7-pack op-amp, comparator, subtractor, and residue
amplifier are explained in detail.

2.1 Block diagram and Methodology

Figure 2.1: Functional block diagram of the circuit

The low power consumption, excellent resolution, and fast speed of

the pipelined analog-to-digital converter architecture make it appealing.
Thus, for low-power applications like as wireless communication systems,
the pipelined ADC is the best option. CMOS IC technology is widely
used in both analog and digital applications. Pipeline architecture enables
power reduction, digital error correction via capacitor scaling, and digital
gain calibration. Pipeline ADC is therefore appropriate for applications
requiring high resolution and high speed.

14
 An N-step converter, the pipeline ADC converts one bit at a time. The
N stages of the pipeline ADC are connected in series, allowing it to attain
high resolution (10–13 bits) at comparatively quick rates as shown in Figure
2.1. A sample-and-hold, a summer, a gain of two amplifiers, and a 1-bit
ADC (a comparator) are present in every stage.

The pipeline converter’s high throughput is one of its key benefits. For
each clock cycle, one conversion will be finished following an initial delay
of N clock cycles. The first stage is free to work on the subsequent samples
while the second stage operates on the residue from the previous step.
Each stage operates on the residue passed down from the previous stage,
thereby allowing for fast conversions.

2.2 Functional Block Diagram

It consists of 5 main blocks:
1. 7-pack operational amplifier
2. Sample and Hold Circuit
3. Comparator
4. Subtractor
5. Residue Amplifier

2.2.1 7-pack Operational Amplifier

Figure 2.2: 7-pack opamp circuit

15
 To design a Pipelined ADC the basic block is Operational Amplifier.
The opamp is designed using UMC 180nm technology with a 1.8V power
supply. The designed opamp’s gain is determined by an AC analysis on the
schematic. the gain to be obtained for the pipeline adc to work effectively
is 60dB. Many aspects such as slew rate, phase margin, ICMR and supply
voltage are considered and calculated to obtain specific gain for the ADC.
7-pack opamp could imply that multiple amplification stages are in-
volved in the analog signal processing before it reaches the ADC stages.
Each operational amplifier in the ”7-pack” might handle a specific part of
the signal processing or amplification, contributing to the overall perfor-
mance of the pipeline ADC.

2.2.2 Sample and Hold Circuit

Figure 2.3: Sample and Hold Circuit

An essential part of analog-to-digital converters (ADCs) are bootstrapped

samplers. With little power loss, the bootstrapping procedure lowers the
distortion and increases speed. The Sample and Hold circuit shown in
figure 2.3 is an electronic device that creates voltage samples from input
and then holds those samples for a set period. The sampling time refers
to the period when the sample and hold circuit generate a sample of the
input signal. Similar to this, holding time refers to how long the circuit
keeps the sampled value in memory. The switch links the capacitor to the
output of a buffer amplifier to sample the input signal. The capacitor is
charged or discharged by the buffer amplifier to make the voltage across

16
the capacitor almost equal to or proportional to the input voltage. The
switch separates the capacitor from the buffer when it is in hold mode.
The circuit is intrinsically volatile because the capacitor is always depleted
by its leakage currents and usable load currents but for all but the most
demanding applications, the voltage drop within a given hold period is still
within an acceptable error margin.

2.2.3 Comparator

Figure 2.4: Comparator Circuit

The comparator in a pipeline ADC is responsible for comparing the

input signal with a reference voltage in each stage, contributing to the
successive approximation process and overall conversion accuracy. The
parallel processing nature of the pipeline structure allows for high-speed
and high-resolution analog-to-digital conversion. The output of the com-
parator is a digital signal indicating whether the input voltage is greater
or less than the reference voltage.
The comparator has 2 inputs, one input is from the output of the sam-
ple and hold circuit and the other input is the reference voltage/2 of the
previous block. It compares both the inputs and provides the output which
is further fed to the subtractor block.

17
2.2.4 Subtractor

Figure 2.5: Subtractor Circuit

The subtractor comes into play in the residue amplifier.The subtractor

in the residue amplifier performs the subtraction operation by taking the
input analog voltage and subtracting the digital approximation obtained
from the preceding stages. The result of this subtraction represents the
residue, which is then passed to the next stage for further processing.

2.2.5 Residue Amplifier

Figure 2.6: Residue Amplifier Circuit

The residue is the difference between the actual analog input signal
and the digital approximation obtained from the previous pipeline stages.
The residue amplifier’s role is to amplify and process this residue signal
for further conversion in the pipeline. It typically involves subtracting the
digital approximation from the input signal. The residue amplifier often
includes a gain adjustment to control the amplification of the residue signal.

18
2.2.6 Single Stage Pipeline ADC
The integrated circuit of Pipeline ADC for a single bit is shown in Figure
2.7. There is a Transmission switch which is used to connect between
comparator and amplifier block.

Figure 2.7: 1-bit pipeline ADC Circuit

2.2.7 3-bit Pipeline ADC

The 3-bit ADC is designed using 3 single-bit ADC’s.

Figure 2.8: 3-bit pipeline ADC Circuit

19
Chapter 3

Implementation details

This chapter contains specifications taken for design of Pipeline ADC,design

algorithm and complete working of Pipeline ADC.

3.1 Specifications
Design Specification:
1. Sampling Rate - 100MS/s
2. Resolution - 3 bits
3. Power Supply - 1.8V

Design specification of 7-pack operational amplifier :

Table 3.1: Design specification of 7-pack opamp

Parameters Values
DC Gain 1000 = 60DB
Phase Margin =¿60 degree
Slew Rate 20V/usec
ICMR 0.8V to 1.6V
CL 2pF
VDD 1.8V

3.2 Design Algorithm

1. Sample and Hold: A sample and hold circuit captures the input volt-
age(VIN) by holding the input signals for some time before delivering the
output. Here we have used Bootstrapped sample and hold which serves
as an integral component of analog-to-digital converters(ADCs).The boot-

20
strapping action reduces the distortion and improves the speed with mini-
mal power penalty.
2. Comparator: Compares sampled input voltage and the output of
the DAC. When the output voltage of the DAC is greater than the input
voltage, the MSB of ADC changes accordingly.

3. Subtractor: A subtractor circuit is used in pipeline architecture to

subtract the sample and hold the output from the transmission gate switch
output and the subtractor’s output is fed into the residue amplifier.

4. Residue Amplifier: The residue amplifier is used to increase the gain

of the degraded signal. The circuit for the residue amplifier is generated
using an Opamp circuit.

Transmission Switch: Transmission gates, which can be built with two

inverters, are utilized in 3-bit pipeline architecture. The input to an in-
verting terminal of a subtractor circuit is the output of the gate, and the
output of the comparator serves as the comparator’s select line.

3.3 Working of Pipeline ADC

Operations performed by each stage of the converter are :

1. Compare the sampled input signal to half of the reference voltage,

once it has been obtained, the bit conversion for that stage is each com-
parator’s output.

2. The result is passed to the amplifier after half of the reference voltage
is deducted from the held signal if the input voltage is greater than half of
the reference voltage (comparator output is 1). The original input signal
should be passed to the amplifier if the input voltage is less than half of
the reference voltage(comparator output is 0). The residue is the output
that comes from each stage of the converter.

3. Divide the summation result by two before sending it to the sample

and hold the phase of the following process.

21
Chapter 4

Results and discussions

The results of individual blocks have been discussed here.

4.1 Output Of 7-Pack opamp

An Opamp’s gain is determined by performing an AC analysis on the
schematic. The stated frequency range is 10–100 MHz, and the resulting
gain is 59 dB. Figure 4.1 displays the opamp gain.

Figure 4.1: Gain of 7-pack operational amplifier

22
4.2 Output of Sample and Hold
Here, the output functionality of the sample and hold circuit is shown in
Figure 4.2. which is having sinusoidal input of 10MHz frequency sampled
at the rate of 100MSPS and sample time of 5ns.

Figure 4.2: Output Waveform of Sample and hold circuit

4.3 Output Of Comparator

The Output of the comparator is shown in figure 4.3, which compares the
input voltage with reference voltage with very minimal offset error.

Figure 4.3: Output Waveform of Comparator circuit

23
4.4 Output Of Subtractor
The Output of the subtractor is shown in Figure 4.4 to examine the circuit,
the example inputs given are 500mV and 300mV and the obtained result
is 200mV.

Figure 4.4: Output Waveform of Subtractor circuit

4.5 Output Of Residue Amplifier

The Output of the residue amplifier is shown in Figure 4.5 which doubles
the obtained output. The example input is 300mV and the obtained output
is 600mV.

Figure 4.5: Output Waveform of Residue Amplifier circuit

24
4.6 Output Of Complete 3-bit Pipeline ADC
The Output of the Integrated Circuit is shown in figure 4.6 which converts
the analog input into digital output. When the input is 0.7V, the reference
voltage is 0.8V and the expected code is 111 and the waveform of this input
value is shown in figure 4.6. Power dissipation is 28mW.

Figure 4.6: Output Waveform of 3-bit Pipeline ADC circuit

25
Chapter 5

Conclusions and future scope

This chapter discusses the conclusion and future scope of the pipeline ADC
system.

5.1 Conclusion
Sub-blocks such as comparator, subtractor, sample and hold circuit, and
residue amplifier have been used in the implementation of the pipeline ar-
chitecture. The primary goal was to minimize both width and power dis-
sipation. This 3-bit architecture achieves a power dissipation of 28 mW.
In the sample and hold circuit, the bootstrapping action reduces the dis-
tortion and improves the speed with minimal power penalty which is the
major requirement in today’s industries.

5.2 Future scope

• There are just a few methods that could potentially improve the perfor-
mance of data converters. The input signal bandwidth for the entire ADC
circuit will grow with further operational amplifier optimization. Addi-
tionally, the digital sub-circuits can be optimized to use less power while
maintaining good accuracy.
• Utilising a sample and hold buffer will result in a better-sampled signal
that can drive heavy loads. The data converter’s sample rate can also be
increased by using the time-interleaved technique.

26
Chapter 6

Bibliography

[1] Ms. R. M. Shende, Prof. P. R. Gumble, ” ARCHITECTURE OF 4-BIT

PIPELINE ADC IN CMOS TECHNOLOGY”, Volume 2, Issue 3, March
2013, ISSN: 2278 – 1323.

[2] Ms. Rita M. Shende, Prof. P. R. Gumble, ” Low Power High Speed
4 Bit Resolution Pipeline ADC Design in submicron CMOS Technology”,
Volume 3, Issue 1, January 2013 ISSN: 2277 128X.

[3] ManjuDevi Arunkumar P Chavan K.N Muralidhara, Ph.D,” A 1.5-V,

10-bit, 200-MS/s CMOS Pipeline Analog-to-Digital Converter”, Volume
88 – No.7.

[4]Indhudhara Gowda T G, Manasa A, “Design and VLSI Implementa-

tion of 8-Bit Pipelined ADC Using Cadence180nm Technology”, Volume 3
Issue IX, September 2015 ISSN: 2321-9653.

[5] Eri Prasetyo, Dominique Ginhac , Michel Paindavoine” Design and

Implementation a 8 bits Pipeline Analog to Digital Converter in the Tech-
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[6] M. I. Idris, N. Yusop, S. A. M. Chachuli,M.M. Ismail, Faiz Arith,A.

M. Darsono” Low Power Operational Amplifier in 0.13um Technology”,
Vol. 9, No. 1; 2015, ISSN 1913-1844 E-ISSN 1913-1852.

[7] M. Waltari, Circuit techniques for low-voltage and high-speed A/D

converters. PhD thesis, Helsinki University of Technology, Finland, 2002.

27