R7732

Enhanced Quadruple Mode PWM Flyback Controller

General Description Features
R7732 series is the successor of R7730/1 and fully l UVLO 9V/14V
compatible with most of SOT-23-6 product so far in the l Soft-Start Function
market. It's an enhanced, high-performance and current l Current Mode Control
mode PWM controller. It focuses on "easy to design" in l Built-in Slope Compensation
different applications and it will save both design effort and l Internal Leading Edge Blanking
external components. l PWM Quadruple Mode for Green-Mode
l Excellent Green Power Performance
Besides the general features shown in the Features
l Cycle-by-Cycle Current Limit
section, R7732 covers wide protection options, such as
l Internal Over Voltage Protection
internal Over Load Protection (OLP) and Over Voltage
l Internal Over Load Protection
Protection (OVP) to eliminate the external protection
l Secondary Rectifier Short Protection
circuits. Moreover, it also features Secondary Rectifier
l Opto-Coupler Short Protection
Short Protection (SRSP) and CS pin open protection. This
l Feedback Open-Loop Protection
protection will make the PSU design for reliability and safety
l CS Pin Open Protection
easier.
l Built-in Jittering Frequency
R7732 is designed for power supply such as NB adaptor l Built-in PRO Pin for External Arbitrary OVP/OTP
which is a very cost effective and compact design. The l Soft Driving for EMI Noise
precise external OVP and Over Temperature Protection l High Noise Immunity
(OTP) can be implemented by very simple circuit. The l RoHS Compliant and Halogen Free
start-up resistors can also be replaced by bleeding
resistors to save power loss and component count. Application
l Switching AC/DC Adaptor and Battery Charger
Ordering Information l Printer Power Supply
R7732 l DVD Open Frame Power Supply
Package Type l Set-Top Box (STB)
E : SOT-23-6
l ATX Standby Power
Lead Plating System
l TV/Monitor Standby Power
G : Green (Halogen Free and Pb Free)
l PC Peripherals
R7732 Version (Refer to Version Table)
l NB Adaptor
Note :
Richtek products are : Pin Configurations
} RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
(TOP VIEW)
} Suitable for use in SnPb or Pb-free soldering processes. GATE VDD CS

6 5 4

2 3

GND COMP PRO

SOT-23-6

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R7732
Marking Information
R7732GGE R7732LGE R7732AGE
F0= : Product Code F2= : Product Code F3= : Product Code
F0=DNN F2=DNN F3=DNN
DNN : Date Code DNN : Date Code DNN : Date Code

R7732HGE R7732RGE
F4= : Product Code F6= : Product Code
F4=DNN F6=DNN
DNN : Date Code DNN : Date Code

R7732 Version Table

Version R7732G R7732R R7732L R7732A R7732H
Frequency 65kHz 65kHz 65kHz 65kHz 100kHz
OLP Delay Time 56ms 56ms 56ms 28ms 36ms
Internal OVP(27V) Auto Recovery Auto Recovery Latch Latch Auto Recovery
OLP & SRSP Auto Recovery Auto Recovery Auto Recovery Latch Auto Recovery
PRO Pin High Latch Auto Recovery Latch Latch Auto Recovery
PRO Pin Low Auto Recovery Latch Latch Latch Latch

Typical Application Circuit

Vo+

+
+

AC Mains
(90V to 265V)

Vo-

#
5
3 PRO VDD 6
GATE

R7732
2 4
COMP CS
GND

NTC 1

# See Application Information

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Functional Pin Description
Pin No. Pin Name Pin Function
1 GND Ground.
Voltage Feedback Pin. By connecting an opto-coupler to close control loop and achieve
2 COMP
the regulation.
3 PRO For External Arbitrary OVP or OTP.
4 CS Primary Current Sense Pin.
5 VDD Power Supply Pin.
6 GATE Gate Drive Output to drive the external MOSFET.

Function Block Diagram

VDD

VL_TH +
Auto Auto
IBIAS - Recovery Recovery OVP
+
PRO
+ - 27V
- Latch Latch
VH_TH
Secondary Rectifier Short
POR
1.7V - & CS Open Protection
Shutdown
+ Logic
UVLO
+
Brownout
Sensing - 9V/14V
Counter
COMP Open Bias &
Sensing Bandgap

OLP Oscillator

SS Dmax
Constant
Power
Soft Driver
S
Q GATE
-
COMP - R
+
PWM
Comparator
CS Slope
Ramp VCOMP
VBURL
Quadruple Mode
VBURH
LEB X3 VDD

GND

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Absolute Maximum Ratings (Note 1)
l Supply Input Voltage, VDD ----------------------------------------------------------------------------------------- −0.3V to 30V
l GATE Pin -------------------------------------------------------------------------------------------------------------- −0.3V to 16.5V
l PRO, COMP, CS Pin ----------------------------------------------------------------------------------------------- −0.3V to 6.5V
l IDD ----------------------------------------------------------------------------------------------------------------------- 10mA
l Power Dissipation, PD @ TA = 25°C
SOT-23-6 -------------------------------------------------------------------------------------------------------------- 0.4W
l Package Thermal Resistance (Note 2)
SOT-23-6, θJA -------------------------------------------------------------------------------------------------------- 250°C/W
l Junction Temperature ----------------------------------------------------------------------------------------------- 150°C
l Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C
l Storage Temperature Range --------------------------------------------------------------------------------------- −65°C to 150°C
l ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 3kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------ 250V

Recommended Operating Conditions (Note 4)

l Supply Input Voltage, VDD ----------------------------------------------------------------------------------------- 12V to 25V
l Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C
l Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
VDD Section
V DD Over Voltage Protection Level VOVP 26 27 28 V
V DD Zener Clamp VZ 29 -- -- V
On Threshold Voltage VTH_ON 13 14 15 V
Off Threshold Voltage VTH_OFF 8.5 9 9.5 V
VDD Holdup Mode Entry Point VDD_LOW VCOMP <1.6V -- 10 -- V
VDD Holdup Mode Ending Point VDD_HIGH VCOMP <1.6V -- 10.5 -- V
Latch-off Voltage VLH -- 14 -- V
Latched Reset Voltage VLH_RST -- 9 -- V
VDD = V TH_ON – 0.2V,
Start-up Current IDD_ST -- 20 35 µA
TA = -40ºC to 100ºC (Note 5)
VDD = 15V, V COMP = 2.5V,
Operating Supply Current IDD_OP -- 1.3 2.2 mA
GATE pin open
Latch-off Operating Current IDD_LH TA = -40ºC to 100ºC (Note 5) -- -- 40 µA

To be continued

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Parameter Symbol Test Conditions Min Typ Max Unit
Oscillator Section
R7732G/R/L/A 60 65 70 kHz
Normal PWM Frequency fOSC
R7732H 92 100 108 kHz

Frequency Reduction Mode Minimum R7732G/R/L/A 18 22 -- kHz

fFR_MIN
Frequency R7732H -- 25 -- kHz
Maximum Duty Cycle DCYMAX 70 75 80 %
PWM Frequency Jitter Range △f -- ±6 -- %
PWM Frequency Jitter Period TJIT For 65kHz -- 4 -- ms
Frequency Variation Versus
fDV VDD= 12V to 25V -- -- 2 %
V DD Deviation
Frequency Variation Versus TA= -30°C to 105°C
fDT -- -- 5 %
Temperature Deviation (Note 5)
COMP Input Section
Open-Loop Voltage VC OMP_OP COMP pin open 5.5 5.75 6 V
R7732G/R/L -- 56 -- ms
COMP Open-Loop Protection Delay Time TOLP R7732A -- 28 -- ms
R7732H -- 36 -- ms
Short Circuit Current IZERO VCOMP= 0V -- 1.2 2.2 mA
Frequency Reduction Mode Entry Voltage VFR_ET -- 3 -- V
Frequency Reduction Mode Ending R7732G/R/L/A -- 2.9 -- V
VFR_ED
Voltage R7732H -- 2.8 -- V
Current-Sense Section
Initial Peak Current Limitation Offset VC S_TH 0.68 0.7 0.72 V
Leading Edge Blanking Time T LEB (Note 6) 150 250 350 ns
Internal Propagation Delay Time T PD (Note 6) -- 100 -- ns
Minimum On Time TON_MIN 250 350 450 ns
GATE Section
Rising Time TR VDD= 15V, CL= 1nF -- 125 -- ns
Falling Time TF VDD= 15V, CL= 1nF -- 40 -- ns
GATE Output Clamping Voltage VC LAMP VDD= 25V -- 14 -- V
PRO Interface Section
Pull Low Threshold VL_TH 0.47 0.5 0.53 V
Pull High Threshold VH _TH 3.5 3.8 4.1 V
Internal Bias Current IBIAS 90 100 110 µA
Pull High Sinking Current ISINK (Note 7) -- -- 1.2 mA

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Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Note 6. Leading edge blanking time and internal propagation delay time are guaranteed by design.
Note 7. The sourcing current of PRO pin must be limited below 5mA. Otherwise it may cause permanent damage to the device.

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Typical Operating Characteristics
IDD_ST vs. VDD IDD_ST vs. Temperature
25 30
TA = 25°C

20
25
I DD_ST (µA)

I DD_ST (µA)
15
20
10

15
5

0 10
0 3 6 9 12 15 -50 -25 0 25 50 75 100 125
VDD (V) Temperature (°C)

fOSC vs. VDD fOSC vs. Temperature

67 68

R7732G/R/L/A R7732G/R/L/A

66 66
f OSC (kHz)

f OSC (kHz)

65 64

64 62

63 60
10 13 16 19 22 25 -50 -25 0 25 50 75 100 125
VDD (V) Temperature (°C)

fOSC vs. VDD fOSC vs. Temperature

104 104

R7732H R7732H
102
102
f OSC (kHz)
f OSC (kHz)

100

100
98

98
96

96 94
10 13 16 19 22 25 -50 -25 0 25 50 75 100 125
VDD (V) Temperature (°C)

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VTH_ON vs. Temperature VTH_OFF vs. Temperature

16 10.0

15 9.5

VTH_OFF (V)
VTH_ON (V)

14 9.0

13 8.5

12 8.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

fFR_MIN vs. Temperature IDD_OP vs. Temperature

30 1.8
VDD = 15V,
VCOMP = 2.5V,
GATE Pin Open
25 1.6
f FR_MIN (kHz)

I DD_OP (mA)

20 1.4

15 1.2

10 1.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

VCOMP_OP vs. Temperature VOVP vs. Temperature

6 29

5.8 28
VCOMP_OP (V)

VOVP(V)

5.6 27

5.4 26

5.2 25
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

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 R7732

TOLP vs. Temperature TOLP vs. Temperature

70 40

R7732G/R/L R7732A

65 35
TOLP (ms)

TOLP (ms)
60 30

55 25

50 20
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

TOLP vs. Temperature VCS_TH vs. Temperature

45 0.80

R7732H

40 0.75
VCS_TH (V)
TOLP (ms)

35 0.70

30 0.65

25 0.60
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

IDD_LH vs. Temperature IBIAS vs. Temperature

40 110

35
100
30
I DD_LH (µA)

I BIAS (µA)

25 90

20
80
15

10 70
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

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VH_TH vs. Temperature VL_TH vs. Temperature

6 0.60

5 0.55
VH_TH (V)

VL_TH (V)
4 0.50

3 0.45

2 0.40
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

TR vs. Temperature TF vs. Temperature

140 60

130 50
TF (ns)
TR (ns)

120 40

110 30

100 20
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

VCLAMP vs. Temperature DCYMAX vs. Temperature

18 78

16 76
DCYMAX (%)
VCLAMP (V)

14 74

12 72

10 70
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

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Application Information
PWM Quadruple Mode Freq.

R7732 applies quadruple mode for improving efficiency at

fOSC
light load operation. Please also refer to Figure 1 for details.
• PWM Mode : For most of load, the circuit will run at
traditional PWM current mode.
#
It's highly recommended to add a resistor in parallel
fFR_MIN
with opto-coupler. To provide sufficient bias current to
make TL-431 regulate properly, 1.2kΩ resistor is
suggested. VCOMP
VFR_ED VFR_ET
• Frequency Reduction Mode : The frequency reduction
mode function provides linear switching frequency Figure 2. PWM Frequency vs. COMP Voltage
reduction according to load conditions, as shown in
• Burst Mode : During light load, switching loss will
Figure 2. When the feedback voltage of COMP pin is
dominate the power efficiency calculation. This mode
lower than VFR_ET, the switching frequency starts to
is to cut switching loss. As shown in Figure 1, when
decrease. When the power supply is at light-load and
the output load gets light, feedback signal drops and
the feedback voltage of COMP pin lower than VFR_ED,
touches VBURL. PWM signal will be blanked and system
the switching frequency is clamped at fFR_MIN. This
ceases to switch. After VOUT drops and feedback signal
frequency reduction mode function reduces power
goes back to VBURH, switching will be resumed.
consumption under light-load and no-load conditions,
and easily meets even the strictest regulations.

Frequency
Normal Burst VDD
Reduction
Operation Mode Holdup Mode
Mode
Load

VDD

VDD_HIGH
VDD_LOW

VCOMP

VBURH
VBURL

GATE

Figure 1. PWM Quadruple Mode

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R7732
• VDD Holdup Mode: Under light load or load transient Start-up Circuit
moment, feedback signal will drop and touch VBURL. To minimize power loss, it's recommended that the start-
Then PWM signal will be blanked and system ceases up current is from bleeding resistor. It's not only good for
to switch. VDD could drop down to turn off threshold power saving but also could reset latch mode protection
voltage. To avoid this, when VDD drops to a setting quickly. Figure 3 shows IDD_Avg vs. RBleeding curve. User
threshold, 10V, the hysteresis comparator will bypass can apply this curve to design the adequate bleeding
PWM and burst mode loop and forces switching at a resistor.
very low level to supply energy to VDD pin. VDD holdup
mode was also improved to hold up VDD by less switching Gate Driver
cycles. This mode is very useful in reducing start-up A totem pole gate driver is fine tuned to meet both EMI
resistor loss while still get start-up time in spec. It's not and efficiency requirement in low power application. An
likely for VDD to touch UVLO turn off threshold during internal pull low circuit is activated after pretty low VDD to
any light load condition. This will also makes bias prevent external MOSFET from accidentally turning on
winding design and transient design easier. during UVLO.
Furthermore, VDD holdup mode is only designed to
Oscillator
prevent VDD from touching turn off threshold voltage
To guarantee precise frequency, it's trimmed to 5%
under light load or load transient moment. Relative to
tolerance. It also generates slope compensation saw-tooth,
burst mode, switching loss will increase on the system
75% maximum duty cycle pulse and overload protection
at VDD holdup mode, so it is highly recommended that
slope. It can typically operate at built-in 65kHz center
the system should avoid operating at this mode during
frequency and features frequency jittering function. Its
light load or no load condition, normally.

RBleeding

RBleeding
IDD_Avg

VDD

Figure 3. IDD_Avg vs. RBleeding Curve

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 R7732
jittering depth is 6% with about 4ms envelope frequency
at 65kHz. IBIAS VL_TH
+ Deglitch Auto
- 30µs Recovery
Tight Current Limit Tolerance
PRO
Since R7732 is the successor of R7731A, its current limit + Deglitch
Latch
setting is completely the same as R7731A. Generally, - 50µs
VH_TH
the saw current limit applied to low cost flyback controller
because of simple design. However, saw current limit is
hard to test in mass production. Therefore, it's generally VPRO

"guaranteed by design". The variation of process and Auto Recovery / Latch

VH_TH
package will make its tolerance wider. It will lead to 20%
Normal Operating
to 30% variation when doing OLP test at certain line
VL_TH
voltage. This will cause yield loss in power supply mass Auto Recovery / Latch
production. Through well foundry control, design and test
/ trim mode in final test, R7732 current limit tolerance is Figure 4. PRO Pin Diagram
tight enough to make design easier.
VDD
PRO Pin Application
R7732 features a PRO pin, as shown in Figure 4, and it
can be applied for external arbitrary OVP or OTP (ex:
Figure 5 to Figure 8).
If the voltage of PRO pin is greater than pull-low threshold PRO

VL_TH, the controller is enabled and switching will occur. (Option)

If the voltage of PRO pin falls below pull-low threshold or
rises to pull-high threshold VH_TH, the controller will be
shut down and cease to switch after deglitch delay. VDD OVP : VDD > VR + VZ + 3.8V

PRO pin is built in 1.5V internally, so leave PRO pin open Figure 5. For VDD OVP Only
if you don't need this function. If designer needs to apply
a bypass capacitor on PRO pin, it should not be more PRO
than 1nF. The internal bias current of PRO pin is
100µA(Typ.). R7732 has internal OVP. For arbitrary OVP
or OTP applications which behave as auto recovery or
latch, it can get these by PRO pin. For PRO pin pulling (Option)

high function applications, the voltage of PRO pin must NTC

rise above VH_TH (The supply current of PRO pin must be

greater than 1.2mA and be limited below 5mA.). When IC
enters latch mode, the IC maximum operating current is
40µA (100°C), and it will be release until VDD is fallen to Figure 6. For OTP Only
VTH_OFF.
PRO pin is guaranteed that below: If the voltage of PRO
pin reaches 4.1V or falls below 0.47V, the system will be
protected.

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R7732
VDD hiccup(R7732A: latch), the power loss and thermal
PRO during OLP will be averaged to an acceptable level over
the ON/OFF cycle of the IC. This will last until fault is
removed.
• Brownout Protection: During heavy load, this will
(Option)
trigger 56ms(R7732A: 28ms; R7732H: 36ms) protection
and shut down the system. If it is in light load condition,
system will be shut down after VDD is running low and
triggers UVLO.
Figure 7. For VDD OVP
• CS Pin Open Protection: When CS pin is opened,
the system will be shut down after couples of cycle. It
PRO Vo+
could pass CS pin open test easier.
• Over Voltage Protection: Output voltage can be
roughly sensed by VDD pin. If the sensed voltage
reaches 27V threshold, system will be shut down and
hiccup after 20µs deglitch delay for R7732G/R/H or latch
(Option) (Option) after 70µs deglitch delay for R7732L/A. This will last
until fault is removed.
• Feedback Open and Opto-Coupler Short: This will
Figure 8. For VOUT OVP trigger OVP or OLP. It depends on which one occurs
first.
Soft-Start
• Secondary Rectifier Short Protection: As shown in
During initial power on, especially at high line, current
Figure 9. The current spike during secondary rectifier
spike is kind of unlimited by current limit. Therefore,
short test is extremely high because of the saturated
besides cycle-by-cycle current limiting, R7732 still
main transformer. Meanwhile, the transformer acts like
provides soft start function. It effectively suppresses the
a leakage inductance. During high line, the current in
stat-up current spike. The typical soft-start duration is
power MOSFET is sometimes too high to wait for OLP
about 40 clock cycles. This will provide more reliable
delay time. To offer better and easier protection design,
operation and possibility to use smaller current rating
R7732 shut down the controller after couples of cycles
power MOSFET.
before fuse is blown up.
Secondary Rectifier Short
Protection
R7732 provide fruitful protection functions that intend to R7732G
protect system from being damaged. All the protection
functions can be listed as below:
VDD
• Cycle-by-Cycle Current Limit: This is a basic but
very useful function and it can be implemented easily
in current mode controller.
• Over Load Protection: Long time cycle-by-cycle VCOMP
current limit will lead to system thermal stress. To further
VCS
protect system, system will be shut down after 56ms
(R7732A: 28ms; R7732H: 36ms).
Through our proprietary prolong turn off period during Figure 9. Secondary Rectifier Short Protection

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 R7732
Negative Voltage Spike on Each Pin on a standard JEDEC 51-3 single-layer thermal test board.
Negative voltage (< -0.3V) on each pin will cause substrate The maximum power dissipation at TA = 25°C can be
injection. It leads to controller damage or circuit false calculated by the following formula :
trigger. Generally, it happens at CS pin due to negative PD(MAX) = (125°C - 25°C) / (250°C/W) = 0.4W for SOT-23-
spike because of improper layout or inductive current 6 package
sense resistor. Therefore, it is highly recommended to
The maximum power dissipation depends on the operating
add a R-C filter to avoid CS pin damage, as shown in
ambient temperature for fixed TJ (MAX) and thermal
Figure 10. Proper layout and careful circuit design should
resistance, θJA. For the R7732 package, the derating curve
be done to guarantee yield rate in mass production.
in Figure 11 allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation.
0.45
AC Mains

Maximum Power Dissipation (W).

(90V to 265V) 0.40

0.35

0.30

0.25

0.20
5 0.15
3 PRO VDD 6
GATE 0.10
R7732 0.05
2 4
COMP CS
GND 0.00
NTC 1 0 25 50 75 100 125
Ambient Temperature
R-C Filter
Figure 11. Derating Curves for R7732 Package

Figure 10. R-C Filter on CS Pin Layout Considerations

A proper PCB layout can abate unknown noise interference
Thermal Considerations
and EMI issue in the switching power supply. Please refer
For continuous operation, do not exceed absolute
to the guidelines when you want to design PCB layout for
maximum junction temperature. The maximum power
switching power supply:
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and } The current path (1) from bulk capacitor, transformer,
difference between junction and ambient temperature. The MOSFET, Rcs return to bulk capacitor is a huge high
maximum power dissipation can be calculated by the frequency current loop. It must be as short as possible
following formula : to decrease noise coupling and kept a space to other
low voltage traces, such as IC control circuit paths,
PD(MAX) = (TJ(MAX) - TA) / θJA
especially.
Where TJ(MAX) is the maximum junction temperature, TA is
} The path (2) from RCD snubber circuit to MOSFET is
the ambient temperature, and θJA is the junction to ambient
also a high switching loop, too. Keep it as small as
thermal resistance.
possible.
For recommended operating condition specifications of
} It is good for reducing noise, output ripple and EMI issue
the R7732, the maximum junction temperature is 125°C
to separate ground traces of bulk capacitor (a), MOSFET
and TA is the ambient temperature. The junction to ambient
(b), auxiliary winding (c) and IC control circuit (d). Finally,
thermal resistance, θJA, is layout dependent. For SOT-
connect them together on bulk capacitor ground (a).
23-6 packages, the thermal resistance, θJA, is 250°C/W

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R7732
The areas of these ground traces should be kept large. secondary winding, the output diode, and the output
} Placing bypass capacitor for abating noise on IC is filter capacitor. In addition, apply sufficient copper area
highly recommended. The bypass capacitor should be at the anode and cathode terminal of the diode for
placed as close to controller as possible. heatsinking. Apply a larger area at the quiet cathode
terminal. A large anode area can increase high-frequency
} In order to minimize reflected trace inductance and EMI,
radiated EMI.
it is minimized the area of the loop connecting the

AC Mains CBULK
(90V to 265V) (2)

(a)

CBULK Ground (a)

(c) Trace Trace Trace

5
3 PRO VDD 6
GATE IC Auxiliary MOSFET
Ground (d) Ground (c) Ground (b)
R7732
2 4 (1)
COMP CS
GND

NTC 1
(b)
(d)

Figure 12. PCB Layout Guide

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 R7732
Outline Dimension

H
D
L

C B

A
A1
e

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.889 1.295 0.031 0.051
A1 0.000 0.152 0.000 0.006
B 1.397 1.803 0.055 0.071
b 0.250 0.560 0.010 0.022
C 2.591 2.997 0.102 0.118
D 2.692 3.099 0.106 0.122
e 0.838 1.041 0.033 0.041
H 0.080 0.254 0.003 0.010
L 0.300 0.610 0.012 0.024

SOT-23-6 Surface Mount Package

Richtek Technology Corporation Richtek Technology Corporation

Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

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