Fault Simulation

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Logic Simulation
• Logic simulation may be utilized to
(1) verify the correctness of the design or
(2) predict the behavior of the design.

• Simulation accuracy and complexity depend on the circuit model.

• Functional level description down to transistor level.
• Two-valued (0 or 1), three-valued (0, 1, or u), or more complicated signal models.
• Inclusion of timing model, types of timing models.

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 Fault Simulation
• A fault simulator is used to evaluate the quality of tests.
• It can simulate the circuit response in the presence of faults.
• Fault dropping—test pattern generator utilizes fault simulation to remove faults detected
by newly generated test patterns from the fault list.

• Utilize fault-parallelism or pattern-parallelism to speed up the process.

• Inputs:
• The design under test, the fault list
• Outputs:
• Detected faults, fault coverage, fault detection dictionary
VLSI System Testing 60 Jiun-Lang Huang, GIEE/ICDA, NTU
 Test Pattern Generation

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Why?
• Fault simulation with user-given patterns is insufficient and inefficient.
• ATPG aims to generate a high-quality test pattern set (high fault coverage
with few patterns) to detect the target faults.

• Modern ATPGs consider not only fault coverage and the pattern count but
also test power, compressibility, and diagnosability.

VLSI System Testing 62 Jiun-Lang Huang, GIEE/ICDA, NTU

 Sequential ATPG?
• Very low efficiency.
• With full-scan design, sequential ATPG is no longer needed.

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 Some Facts about ATPG
• Random pattern generation
• Use random patterns to detect easy-to-detect faults—fault simulation is cheaper than
pattern generation.

• Stop when fault coverage saturates.

• X-ratio
• Most ATPG patterns are sparsely specified.
• The ratio of unspecified bits (at PI and PPI), i.e., X-ratio, is generally higher than 90%.
• Test power reduction and test compression techniques rely heavily on X-bits.

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 Full-Scan Design

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 The Scan Concept

VLSI System Testing 66 Jiun-Lang Huang, GIEE/ICDA, NTU

 The Scan-Design Rules
• The designers must adhere to the rules so that the design is scan-testable.
• Rule I: Use only D-type master-slave FFs.
• Rule II: At least one PI pin must be available for TC.
• Scan-in and out can be shared (using MUX) with functional
PI and PO.

• Rule III: All FF clocks must be controllable from PI.

• This is necessary for FFs to function as a scan register.
• Rule IV: Clock must NOT feed the data inputs of FFs.
• To avoid potential race conditions in the normal mode.
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VLSI System Testing 68 Jiun-Lang Huang, GIEE/ICDA, NTU
 Tests for Scan Circuits
• Phase I:
• Shift test
• Targets the scan flip-flops.
• Phase II:
• Combinational test
• Target the faults in the combinational circuit.

VLSI System Testing 69 Jiun-Lang Huang, GIEE/ICDA, NTU

 Phase I: Shift Test
• A toggle sequence
• 00110011… of length n+4 is scanned in.
• n is the maximum number of FFs in a scan chain.
• Each SFF experiences all four transitions: 0→1, 0→0, 1→1, 1→0.
• The shift test covers most single stuck-at faults in the FFs.
• The shift test also verifies the correctness of the shift operation.

VLSI System Testing 70 Jiun-Lang Huang, GIEE/ICDA, NTU

 Phase II: Combinational Test
• Each test vector consists of I and S
i i

• Scan-test length
•n comb(n + 1) + n

•n comb:
number of
combinational tests

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 Multiple Scan Chains
• To reduce test time.
• However, each scan register has its own scan-in and scan-out.
• The scan registers may differ in length.
• Test time determined by the longest one.

VLSI System Testing 72 Jiun-Lang Huang, GIEE/ICDA, NTU

 Problem w/ Scan Design
• Area/performance overhead
• Increased gate count and routing area
• MUXed input (in single-clock SFF design)
• Extra load capacitance at FF output.
• Long test application time.
• Not applicable to all designs.
• Must follow the scan design rules.
• High power dissipation during testing.
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 Design Automation

VLSI System Testing 74 Jiun-Lang Huang, GIEE/ICDA, NTU

 Physical Design of Scan w/ Standard Cells
• Placing the cells without scan wiring.
• Replace FFs with SFFs.
• Wider than original.
• Add TC control line.
• At most one track in every alternate
routing channel.

• Scan path routing.

• One track in every alternate routing
channel is possible.

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 At-Speed Test Application
• For timing-related faults, need two-vector patterns.
• However, a scan cell only stores one vector.
• LoC (Launch-on-Capture) or LoS (Launch-on-Shift).

VLSI System Testing 76 Jiun-Lang Huang, GIEE/ICDA, NTU

 Scan-Based LoC Test Pattern Application
at-speed
cycle
clk PI
combinational
PO

logic
se
PI I1 I2 PPI PPO

PPI S1 S2 FFs SE
SO SI
V1 ready launch V2 capture response

• An LoC pattern consists of two vectors.

•V 1 = < I1, S1 >, V2 = < I2, S2 > where I/S corresponds to PI/PPI.

•S 2 is generated by CUT.

• At-speed cycle is identical or similar to functional

operation.
77
ITC-Asia 2021 20210819
 University of Maryland Baltimore County
LAUNCH-ON-SHIFT (LOS)
Baltimore, MD 21250
tehrani,plusquel @umbc.edu
• Skewed-load

IC LC CC

CLK
ng fre-
aunch- SEN

ch-off-
lt test- Scan−in pattern i Scan−in pattern i+1
Scan−out response i−1 Scan−out response i
sed at- (a)
t scan
encap-
IC LC CC
opera- GIEE/ICDA, NTU VLSI System Testing 78
 LOW COST TESTER LIMITATIONS
• PI hold constant from launch to capture
• PO masked

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 LOC VS. LOS
• Fault coverage
• Hardware requirement
• Test power

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