VLSI Testing
Boolean Testing (Fault Model Based ) Part I: Combinational Circuits ATPG*
Professor Chien-Mo James Li Graduate Institute of Electronics Engineering National Taiwan University
* Some slides in this lecture are courtesy of Prof. Jiun-Lang Huang, NTUEE
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Summary
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Exhaustive Test Too Long
Example: 64-bit ripple-carry adder
A total of 64 + 64 + 1 = 129 inputs. 65 outputs. Assume that both ATE and the adder operates at 1GHz.
Exhaustive Test Strategy # of patterns Test time Exercise all input combinations 2129 72 x 1022 yrs
SSF Test Exercise all stuck-at faults 1,728 1.728 s
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Boolean Testing (Fault Model Based)
General Fault Objective (i.e. no specific targeted faults)
Random pattern generation Critical Path Specific Fault Objective (aka deterministic ATPG) (Focus of this Chapter) Boolean Algebraic and Boolean difference Path Tracing Path Sensitization, D algorithm, PODEN, FAN
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Why Combinational ATPG?
Easier computation
Combinational ATPG much faster than sequential ATPG Most sequential circuits have scan chains Internal memory elements controllable (like PI) and observable (like PO)
Design For Testability (DFT) very popular now
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Scan Design
One of the most popular Design-for-Test (DfT) techniques. Stitch memory elements (aka. bistables) into shift registers.
Test vectors can be shifted in. Output response can be shifted out. Note: excluding RAM Convert the difficult sequential ATPG problem to a more tractable combinational ATPG problem.
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Cost of scan-design:
5 20% area overhead Performance degradation Extra pins for scan-chain control Longer test time Still, the combination of scan-design + combo. ATPG remains the most popular test solution.
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Example: MUX-D Scan Design
Scan_enable =1 shift mode Scan_enable = 0 normal operation mode CL = Combinational Logic
Scan_out Scan_in Primary inputs CL 1 0 D ck Q CL 1 0 D ck Q 1 0 D ck Primary outputs Q CL
Scan_enable clock
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Scan Operation (for Stuck-at Faults)
PI = primary inputs; PO = primary outputs SO = Scan Output; Strobe = Observe
Cycle
Scan -in
System clock Normal
Scan-out Shift-out
Scan chain Shift in operation wafeforms
operation (& shift in )
Apply PI
clock
Strobe PO Strobe SO
Scan_Enable
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Summary
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Random Pattern Generation
Randomly generated input patterns are selected by a fault simulator Problem
Fault coverage often saturates after easy-to-detect faults are detected
Fault Coverage
Test Length
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Random Pattern Resistant Faults
Definition Faults that are difficult to be tested by random patterns Example: stuck-at-0 fault at an n-input AND gate output Need test pattern (1,1,1,1) If random patterns, (Assume equal signal probability of 0.5 at each input), P(1,1,1) = 0.5n
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Summary
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Notation
Consider a network N that realizes the function f(x1,x2,,xn), and
denote by the input xi stuck-at-0 fault. f(x1,x2,,xn) = f(x1,x2,, xi-1,0, xi+1,,xn) = fi(0) Similarly, denote xi stuck-at-1 () by f(x1,x2,,xn) = f(x1,x2,, xi-1,1, xi+1,,xn) = fi(1)
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Shannons Expansion
f = xifi(1) + xifi(0)
fi(0) fi(1) xi f
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Boolean Difference Approach
A test vector t detects fault if f(t) f(t)
i.e. f(x) f(x) =1 The set of tests that detect (xi stuck-at-0) is: T = f(x) f(x) =1 T = [xifi(1) + xifi(0)] fi(0) = xi[fi(1) fi(0)] =1 Similarly, set of tests that detect (xi stuck-at-1) is: T = f(x) f (x) =1 T = [xifi(1) + xifi(0)] fi(1) = xi[fi(1) fi(0)] =1
Definition
fi(1) fi(0) is referred to as Boolean difference of f w.r.t. xi and is denoted by f/xi Therefore xi f/xi represents the set of all tests for xi stuck-at-0. xif/xi represents the set of all tests for xi stuck-at-1. 16 NTUEE/GIEE
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Boolean Difference Example
1a xb 1c 0d sa0 1/0 1/0 0/1 1 1/0 1/0 0 f Good/faulty
f = (a + b)c + cd The set of all tests for c stuck-at-0 is T = c f/c.
df/dc = f(a,b,0,d) f(a,b,1,d) = d (a + b) = (a + b)d + abd T = acd + bcd + abcd = {1x10, x110, 0011}
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Boolean Difference Properties
f/xi is condition to sensitize xi to f
f/xi =1 means f dependent on xi f/xi =0 means f independent of xi
f/xi = f/xi f/xi = f/xi Exercise
(f+g)/xi = f[g/xi] g[f/xi] [f/xi g/xi ] (fg)/xi =? (f g)/xi =?
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Internal Faults
The Boolean difference can also be used to derive tests for stuck-at
faults that are internal to the circuit. Let g be an internal signal of a network N represented by f(x1,x2,,xn). g is also a function of input variables g = G(x1,x2,,xn) f can be expressed as a function of input variables and g: f(x1,x2,,xn) fg(g,x1,x2,,xn). The test sets for faults at g are g sa0: G [fg/g] g sa1: G [fg/g]
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Example
0a 0b 1c xd 0/1 g sa1 0/1 0 0/1 0 f
Consider signal g. f = (a + b)c + cd
g=a+b fg = gc + cd fg/g = fg=0 fg=1 = ( cd)(c + cd) =c
Tests for g sa0
(a + b)c = ac + bc Tests for g sa1 (a + b)c = abc
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Chain Rule
f(x) y g(x,y)
x and y are two vectors with no common variables. g(x,y) = gf(y) g/xi = g/f f/xi Can generalize the chain to arbitrary length.
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Chain Rule - Example
a b f g c d
f = ab g/f = 1 cd = c + d f/a = 0 b = b g/a = g/f f/a = (c + d)b
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Problem with Boolean Difference
Boolean expression not always available
Especially in synthesized circuits
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Summary
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Path Sensitization Methods
Composed of the following atomic operations
Fault activation (aka. Excitation, provoke) Error propagation Line justification Implication
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Single Path Sensitization Method
1. 2. Specify inputs to generate appropriate value at the fault site for fault excitation. Select one path from the fault site to an output and specify additional input values to propagate the fault effect along the path to the output. Specify input values so as to justify the signal values assigned in 1 and 2.
3.
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Rules for Error Propagation
Type of gate AND OR NAND NOR Restrictions on off inputs All must be 1 All must be 0 All must be 1 All must be 0
Off inputs = inputs that not on the sensitization path For a given fault, there might be more than one sensitization path If a chosen path lead to inconsistent input values, change a
sensitization path
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Example
d 1 a 1 b 1 c e 0 1 0 G2 G1 0/1 sa1 1 3 0 0 G4 G5 G6 f1 f2
Consider stuck-at-1 Fault excitation
a=b=c=1 Through G5 Through G6 G2 = 1 G4 = 1 a=d=0 contradiction c = 1, e = 0 test vector: abce
Two error propagation paths
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Problem of Single Path Sensitization
Single path sensitization is NOT complete.
Boolean difference approach finds test abce for d sa0. Can single path sensitization?
1 a 1 b
G2 G3 G4
1 0/1 0/1 1 G6 1/0 f
d sa0 G1 1/0 e 1
G5
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1 a 1 b
G2 G3 G4 G5
1 0/1 1 1 G6 1/0 f
d sa0 G1 1/0 e
Single path sensitization
Fault activation a=b=1 Fault propagation Through G3, G6 : G2 = G4 = G5 = 1 G2 = 1 c=1 G4 = 1 e=0 G5 = 0 contradiction G1 = 0 contradiction Through G4, G6 also fails. Fails to find a test for d sa0.
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Multiple Path Sensitization
1 0/1 0/1 1 G6 1/0 f
1 a 1 b
G2 G3 G4 G5
d sa0 G1 1/0 e 1
Both the two paths G3-G6 and G4-G6 are sensitized, i.e., the error is
propagated along both paths. G2 = G5 = 1 c=e=1
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Summary
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The D-Algorithm [Roth 66]
The D-algebra DTypes of cubes Components of the D-algorithm An D-algorithm example Flowchart of the D-algorithm Another example Problems with the D-Algorithm
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The D-Algebra
The D-Algebra
Represent the good and faulty behavior at the same time. Introduce the symbol D in addition to 0, 1, x D = 1/0 represents a signal which has value 1 in fault-free circuit and 0 in the faulty circuit. (i.e. Stuck-at zero) D 0/1 x means not yet specified or dont care in ATPG
D D D D
D D 0
D D D D D D
D D 1
D 0
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The D-Algorithm
The D-algebra Types of cubes Components of the D-algorithm An D-algorithm example Flowchart of the D-algorithm Another example Problems with the D-Algorithm
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Primitive D-Cubes
Specify the minimal input conditions which must be applied
to a logic element to produce an error signal at its output.
Primitive D-cubes of AND gate output stuck-at faults:
Stuck-at-0 fault: 11D Stuck-at-1 fault: 0xD and x0D Used when Fault Activation
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Singular Cover
The minimum input assignments for the output of a gate/function to
be 0 or 1. Used in Line Justification and Implication
a b a b 0 1
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f 0 0 0 1 0 1
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Singular covers of AND
a 1 0 x b 1 x 0 f 1 0 0
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Find the singular covers of the function f(a,b,c) = ac + b
Singular covers of f
b=1
a
1
b x 1 0 0
c 0 x x 1
f 1 1 0 0
0 x
a=1
1 x
c=1
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Cubes Example
a b 1 2 h j G1 G2
1
Primitive D-cube Singular covers of G2 Singular covers of G3 Singular covers of G4 Singular covers of G5 Singular covers of G6
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3 c e 4
8 G4 10 9 5 sa0 G3 7 6 11 f
3
x 0 x 1
G5 12 G6 13
7 8 9 10 11 12 13
2
1 0 x x 1
4
x x 0 1
5
D 1 1 1 0 1 x 0
x 1 0
1 1 0 1 x 0 x 0 1 x 0 1 x 1 0 1 1 0 0 x 1 0 x 1
0 0 1 0 0 1
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The Propagation D-Cube
The minimum input assignments required to propagate an error
signal (D or D) from the input(s) to the output of a gate/function.
Used in D-Drive
A D 1 D D 1 D
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B 1 D D 1 D D
Z = AB D D D D D D
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A 0 D D 0 D D
B D 0 D D 0 D
Z = (A+B) D D D D D D
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The D-Algorithm
The D-algebra Types of cubes Components of the D-algorithm DAn D-algorithm example Flowchart of the D-algorithm Another example Problems with the D-Algorithm
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D-Frontiers
During the test generation process, the gates whose output value is
currently x, but have one or more error signals (D or D) at their inputs.
D D
x
D
D D D
x x
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D-Drive
The D-drive selects an element in the
D-frontier and attempts to propagate the D and/or D from its input(s) to its output (using propagation D-cube).
Da 1 b
c D
Test cube Propagation D cube of gate C Test cube after D-drive
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a D D D
b X 1 1
c X D D
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Test Cube
Specified Boolean values for testing a fault
Not only primary inputs, also internal nodes Notation TC(n) = test cube at ATPG step n
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Implication
Forward Implication
For some gates, partially specified input values uniquely determines the output values. Backward Implication For some gates, knowing the output values (and some input values) can uniquely determine the un-specified input values.
Use singular cover
1 0
0 0
1 0
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Justification
Check if specified values are consistent
1 Justification failed 0 1 1
Want 0 here
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Backtrack
When a conflict occurs, backtrack to the last decision point and take
another choice.
Decision point 1 4
2 Justification Fail
3 Justification Fail
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The D-Algorithm
The D-algebra Types of cubes Components of the D-algorithm A D-algorithm example DFlowchart of the D-algorithm Another example Problems with the D-Algorithm
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An Example 8 h
a b 31 c 1 e 4
1
1 2
1 1
G4 10 9 j D5 sa0 G1 D G3 7 06 G2 11 f
6 7 8 9 10 11 12 13
G5 12 G6 13
Comments Fault Activation
Initial test cube TC(0) = Primitive D-cube for G1 Propagation D-cube of G3, PDG3 TC(1)=TC(0)PDG3 Singular Cover SCG2 TC(2)=TC(1)SCG2
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D-frontier: {G3}
1 1 1 1 1 1
0 0
D-Drive through G3
Backward implication
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a b 31 c e 41
1 2
1 1
x1 h 8 10 9 1 x G4 j D sa0 G1 5 D G3 7 06 G2 f 11
2 3 4 5 6 7 8 9
D G5 12 G6 13
10
11
12
13
Comments D-frontier: {G5,G6}
TC(2) Propagation D-cube of G5, PDG5 TC(3)=TC(2)PDG5
D D 1 D
Choose path through G5. D-drive through G5
D 1 X X 1
Singular Cover SCG4
1 1 1 D D
line justification Done!
TC(4)=TC(3)SCG4
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1 1
1 1
1 1
1 1
D D
0 0
D D
1 1
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The D-Algorithm
The D-algebra Types of cubes Components of the D-algorithm A D-algorithm example Flowchart of the D-algorithm DAnother example Problems with the D-Algorithm
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Flowchart of the D-Algorithm
Initial test cube TC(0)
Select a primitive D-cube (C) C TC(i) TC(i+1) perform implication Select from the D-frontier a gate and for the gate a propagation D-cube (C). no
Is there a D or D at PO? yes yes
Backtrack
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no
Line justification possible?
Test generated
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Line Justification
no Any un-justified line in TC? yes Select an un-justified line, and for the line a Singular Cover (SC)
Test generated
Intersect SC with TC yes
No more backtrack Line justification impossible
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Consistent? no Backtrack
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The D-Algorithm
The D-algebra Types of cubes Components of the D-algorithm A D-algorithm example Flowchart of the D-algorithm Another example Problems with the D-Algorithm
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Another D-Algorithm Example
2 1 1 1 4 3 1
1 2 3 4 5 Primitive Dcube:TC(0) Implication: Select D-frontier G5: TC(1) Implication: SCG1 TC(2) Implication: SCG4 TC(3) 1 1 1 1 1
G1 5 0 sa1 6 G2 D G3 7
1 2 3
G4 G5
81 9D G8 12
G6 10 G7 11
4 5 6 7
10
11
12
1 1 1 1 X 1
1 1 1 1 1 1
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D D D D 0 0 0 0 D D 1 1 D D D D
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2 1 1 1 4 0 3 1
G1 5 0 sa1 6 G2 D 0 G3 7 1
G4 G5
81 9D G8 D 12
G6 101 G7 111
10
11
12
TC(3) 6 Select D-frontier G8: (from {G6,G8}). Implication: TC(4) Justify line 10: SCG6 TC(5) Justify line 7: fail Backtrack to 6 TC(3)
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0
D D D D D D D 0 0 0 1
1 1 1 1 1 1 1
D D D D D D D 1 1 1 1 1 1 1 1 1 1 1 1 D D D D D
7 8
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2 1 1 1 4 1 3 1
G1 5 0 sa1 6 G2 D G3 7 0
1 2 3
G4 G5
81 9D G8 D 12
G6 10D G7 111
4 5 6 7
10
11
12
Backtrack to 6 9 10 11 12 13 Select D-frontier G6 TC(4) Implication: SCG3 TC(5) Implication: SCG7 TC(6) Implication: SCG8 TC(7) Test generated
1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0
D D D D D D 0 0 0 0 0
1 1 1 1 1 1
D D D D D D D D D D D D 1 1 1 1 D D
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The D-Algorithm
The D-algebra Types of cubes Components of the D-algorithm A D-algorithm example Flowchart of the D-algorithm Another example Problems with the D-Algorithm D-
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Problems with the D-Algorithm
Large search space
Assignment of values is allowed for internal signals Backtracking could occur at each gate Inefficient for large circuits and some special classes of circuits Example: ECAT (error-correction-and-translation) circuits.
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ECAT Circuits
A B C E F G H sa0 J K L M Q R N P
Primitive D-cube: A = B = 1, H = D To propagate through P to output R
One possible choice is N = Q = 1, but this is impossible because N and Q realize complementary functions. D-algorithm will exhaustively enumerate input values to confirm that N = Q = 1 is impossible.
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The Decision Tree
A B C E F G H sa0 J K L M
J=1,K=0 Q=1 N=1 J=0,K=1 L=0,M=0 L=1,M=1 C=0,E=0 F=0,G=1
Q
C=1,E=1 F=1,G=0
Justification impossible
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Summary
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The PODEM Algorithm [Goel 81]
Only allow assignments of input values.
Greatly reduce the search space.
The assigned input values are then propagated toward internal lines
by implication.
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PODEM
Essentially a process of finding a PI and a binary value for initial
assignment.
Continue assigning PI values.
Check if D or D is being propagated to primary outputs. After each PI assignment, perform forward implication. If at any stage, either the fault cannot be excited or the error cannot be propagated further, backtrack to the most recent PI assignment and change it.
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Flowchart of PODEM
Assign a binary value to an unassigned PI Forward implication of all PIs. No test Exists. Test generated yes Is there a D or D at PO? no no Is there an untried no combination of values on assigned PIs? yes Set untried combination to assigned PIs.
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Test possible w/ additional PI assignments?
maybe
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Components of PODEM
Determine an initial objective.
If the fault effect has not appeared at the fault site, the initial objective is directed toward fault activation. Given the initial objective, a PI and a binary value are chosen such that there is a good likelihood of meeting the objective. By using the backtrace procedure.
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PODEM Example
1 2 8 1 h G4 10 9 j D5 sa0 G1 D G3 7 06 G2 11 f 1 D G5 12 G6 13
a b 31 c 1 e 4
1 1
Initial objective: G1 output =1 Backtrace to PI: b = 1 Backtrace to PI: a = 1 Objective: propagate through G3, G3 output = D Backtrace to PI: C = 1 Backtrace to PI: e = 1 Objective: propagate through G5, G5 output = D Backtrace to PI: h= 1 Test Generated: abceh=11111
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Questions to Be Answered
What path to backtrace? What PI value to assign? What path to propagate D (D) to PO?
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What Path to Backtrace?
Decision Gate:
One input can control gate output to objective value OR/NAND with output objective =1 AND/NOR with output objective =0 choose easiest input Imply Gate: One input cant control gate output to objective value OR/NAND with output objective =0 AND/NOR with output objective =1 Choose hardest input Why? find out if test exists or not ASAP
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Example
If Objective c=0; choose c1 If objective C=1; choose c2
U V + Y Z A c1 c2
&
B
&
+ F
C
&
Note: need testability measures to guide ATPG
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What PI Values to Assign?
If even parity path
Assign same value as objective Assign opposite value as objective
If odd parity path
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Flowchart of Back-trace
Backtrace(s,vs) a=s v = vs
Return (a,v)
yes
Is a a primary input? no
Set a to be the hardest-to-control input to v.
Set a to be the easiest-to-control input to v. No, decision gate Objective requires setting all inputs?
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no Is a a NAND, NOR, or NOT gate? yes v = v
Yes, imply gate
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What Path to Propagate D to PO?
All gate output of the chosen path must have X values
Called X-PATH chose shortest path to PO do backtrack
If more than one X-path to choose,
If X-path disappear,
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Example of Backtrack
b1 a1 1 d0 c1
Initial objective: (G2,0) Backtrace to PI: b = 1 Initial objective: (G2,0) Backtrace to PI: c = 1 Implication:G2 = D Try error propagation through G5. a=1 Implication: G1 = 0,G4 = 1,G5 = D
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G1 0 G2 sa1 D
G4 1 G5 D G6 1 D G7 0 1
Try error propagation through G8. Initial objective: (G6,1) Backtrace to PI: d = 0 Implication:G3 = 1,G7 = 0,G8 = 1 X-path disappear! Backtrack to most recent PI assignment: d=0 d=1 Implication:G3 = 0,G6 = D,G8 = D
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G8 1 D z
G3 1 0
Test generated!
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Summary
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FAN Fanout-Oriented Test Generation
Techniques to accelerate the test generation process [Fujiwara 85] Adding these improvements to PODEM
Stop backtraces at Headlines Immediate Implications Unique sensitization Multiple backtrace
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Bound, Free, Head Lines
Bound line: line fed (directly or indirectly) by fanout stem Free Line: line that is not Bound Head Line: free line that is either
Fanout stem (e.g. line j), or Input to a gate with bound output (e.g. line h)
a b c d e Bound
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&
h i + m
&
k Head
Free
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Stop Backtraces at Head Lines
headlines
Primary inputs
Primary outputs
Headlines are
Points where the circuit can be partitioned such that a cone of logic driven by PIs can be isolated from the rest of the circuit by cutting the headlines. The values of the PIs that feed the headline points are deferred until the ATPG algorithm knows the value assignments for the headline points. Reduce search space.
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Immediate Implications (BA Fig 7.25)
A B C G1 G2 H K E
FAN Initial objective L = 0
G3
J G4
sa1
PODEM (different from textbook ) Initial objective L = 0 Backtrace to PI: A=1 (G4 is imply gate, choose hardest path Three bubbles, assign opposite value) Backtrace to PI: B=1 Forward Implication: H = 0, J = 1 Objective K=1; Backtrace to PI: C=0 Objective E=1; Assign E=1
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Set J = K = E = 1
J=1
H=0 A=B=1 K=1 C=0
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Unique Sensitization
Only one path to propagate D on signal C to output H. Example: want to propagate D from C to H
A 1 B 0
G1
G2 E
D G3 1 F
D 1
G4
FAN
Set all the off-path inputs to non-controlling values. G1 = 1, E = 1, F = 1, A = 1 B=0 PODEM Initial objective: set G1 to 1 Backtrace to PI: A = 0 assigning A = 0 will later block the propagation of D
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Breadth-First Multiple Backtrace
All must be set to 1.
11 1
Both must be set to 0.
1 0
11 1
0
Set to 1 the input w/ easiest-to-control to 1 input.
PODEMs depth-firth search is sometimes inefficient. Breadth-firth multiple backtrace identifies possible signal conflicts
earlier.
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Combinational ATPG
Outline
Introduction Random pattern generation Boolean difference approach Path sensitization method D-Algorithm PODEM FAN Other ATPG acceleration techniques Concluding Remarks
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Current ATPG Approach
First General Fault Objective
Generate random patterns until FC saturate Generate deterministic until FC reach 100% Or computation time exceed certain limit
Then use Specific Fault Objective
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Algorithm Completeness
The completeness of an ATPG program represents its ability to
exhaust the whole input space to report that a fault is un-testable. Important in applications like redundancy removal. An incomplete ATPG program may reports a fault as un-testable even though a test for that fault does exist.
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Reading
BA Ch. 7
Especially Sec. 7.5
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