Simulation-Based Methods

Lecture 14 Sequential Circuit ATPG

Use of fault simulation for test generation Contest

Genetic Algorithms Spectral Methods

Summary

Directed search Cost functions

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Motivation

Difficulties with time-frame method:

Advantages of simulation-based methods

Long initialization sequence Impossible initialization with three-valued logic (Section 5.3.4) Circuit modeling limitations Timing problems tests can cause races/hazards High complexity Inadequacy for asynchronous circuits

Advanced fault simulation technology Accurate simulation model exists for verification Variety of tests functional, heuristic, random Used since early 1960s
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A Test Causing Race

A

X X

C s-a-1 A

1 1 Z

C s-a-1 1/0 Z

B Time-frame -1

Time-frame 0

Test is a two-vector sequence: X0, 11 10, 11 is a good test; no race in fault-free circuit 00, 11 causes a race condition in fault-free circuit

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Using Fault Simulator

Generate new trial vectors No

Vector source:

Functional (test-bench), Heuristic (walking 1, etc.), Weighted random, random

Trial vectors

Yes

coverage, CPU time limit, etc.)

Stopping criteria (fault satisfied?

Fault simulator
Restore circuit state No

Fault list
Update fault list
Append vectors

Stop

New faults detected?

Yes

Test vectors

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Background

Seshu and Freeman, 1962, Asynchronous circuits, parallel fault simulator, single-input changes vectors. Breuer, 1971, Random sequences, sequential circuits Agrawal and Agrawal, 1972, Random vectors followed by D-algorithm, combinational circuits. Shuler, et al., 1975, Concurrent fault simulator, random vectors, sequential circuits. Parker, 1976, Adaptive random vectors, combinational circuits. Agrawal, Cheng and Agrawal, 1989, Directed search with cost-function, concurrent fault simulator, sequential circuits. Srinivas and Patnaik, 1993, Genetic algorithms; Saab, et al., 1996; Corno, et al., 1996; Rudnick, et al., 1997; Hsiao, et al., 1997.
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Contest

A Concurrent test generator for sequential circuit testing (Contest). Search for tests is guided by cost-functions. Three-phase test generation:

Ref.: Agrawal, et al., IEEE-TCAD, 1989.

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Initialization no faults targeted; cost-function computed by true-value simulator. Concurrent phase all faults targeted; cost function computed by a concurrent fault simulator. Single fault phase faults targeted one at a time; cost function computed by true-value simulation and dynamic testability analysis.

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Directed Search
Trial vectors Vector space
12 10 10 9 Tests 3 8 7 5 4 1

Cost=0

Initial vector

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Cost Function

Defined for required objective (initialization or fault detection). Numerically grades a vector for suitability to meet the objective. Cost function = 0 for any vector that perfectly meets the objective. Computed for an input vector from truevalue or fault simulation.

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Phase I: Initialization

Initialize test sequence with arbitrary, random, or given vector or sequence of vectors. Set all flip-flops in unknown (X) state. Cost function:

Trial vectors: A heuristically generated vector set from the previous vector(s) in the test sequence; e.g., all vectors at unit Hamming distance from the last vector may form a trial vector set. Vector selection: Add the minimum cost trial vector to the test sequence. Repeat trial vector generation and vector selection until cost becomes zero or drops below some given value.
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Cost = Number of flip-flops in the unknown state Cost computed from true-value simulation of trial vectors

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Phase II: Concurrent Fault Detection

Initially test sequence contains vectors from Phase I. Simulate all faults and drop detected faults. Compute a distance cost function for trial vectors:

Trial vectors: Generate trial vectors using the unit Hamming distance or any other heuristic. Vector selection:

Simulate all undetected faults for the trial vector. For each fault, find the shortest fault distance (in number of gates) between its fault effect and a PO. Cost function is the sum of fault distances for all undetected faults.

Add the trial vector with the minimum distance cost function to test sequence. Remove faults with zero fault distance from the fault list. Repeat trial vector generation and vector selection until fault list is reduced to given size.
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Distance Cost Function

s-a-0

0
0 0 Initial vector 0 0 0 8 Trial vectors 1 0 0 2 0 1 0 8 0 0 1 8

1 1

Trial vectors
0 0 0 8 1 1 0 1 1 0 1 2

Trial vectors 0 1 0 8 1 0 0 1 1 1 Fault detected

2 0

Minimum cost vector

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Distance cost function for s-a-0 fault

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Test clusters

Concurrent Test Generation

Vector space

Initial vector

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Need for Phase III

Vector space

Initial vector

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Phase III: Single Fault Target

Cost (fault, input vector) = K x AC + PC

the faulty line.

Activation cost (AC) is the dynamic controllability of Propagation cost (PC) is the minimum (over all paths to
POs) dynamic observability of the faulty line. K is a large weighting factor, e.g., K = 100. Dynamic testability measures (controllability and observability) are specific to the present signal values in the circuit. Cost of a vector is computed for a fault from true-value simulation result. Cost = 0 means fault is detected.

Trial vector generation and vector selection are similar to other phases.

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Dynamic Test. Measures

Number of inputs to be changed to achieve an objective:

Example: A vector with non-zero cost.

(DC0,DC1) = (1,0) 1

DC0, DC1 cost of setting line to 0, 1 AC = DC0 (or DC1) at fault site for s-a-1 (or s-a-0) PC cost of observing line
Cost(s-a-0, 10) = 100 x 2 + 1 = 201

0
(0,1)

s-a-0 AC = 2 PC = 1 0 (0,2) 1 1 (1,0) (1,0)

1 (0,1) (1,0)

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Dynamic Test. Measures

Example: A vector (test) with zero cost.

Cost(s-a-0, 01) = 100 x 0 + 0 = 0 1

(DC0,DC1) = (0,1)

(1,0)

s-a-0
(1,0)

AC = 0 PC = 0 1 (1,0)

0
(1,0) (0,1)

(0,2)

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Other Features

More on dynamic testability measures:

Types of circuits: Tests are generated for any circuit that can be simulated:

Unknown state A signal can have three states. Flip-flops Output DC is input DC, plus a large constant (say, 100), to account for time frames. Fanout PC for stem is minimum of branch PCs.

Combinational No clock; single vector tests. Asynchronous No clock; simulator analyzes hazards and oscillations, 3-states, test sequences. Synchronous Clocks specified, flip-flops treated as black-boxes, 3-states, implicit-clock test sequences.
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Contest Result: s5378

35 PIs, 49 POs, 179 FFs, 4,603 faults. Synchronous, single clock.

Contest
Random vectors 67.6% Gentest** 72.6% 122 490 -4.5 hrs. 10 sec. 75.5% 0

Fault coverage Untestable faults Test vectors Trial vectors used Test gen. CPU time# Fault sim. CPU time#

0
57,532 --

1,722
57,532 3 min.*

0
9 min.

9 min.*

# Sun Ultra II, 200MHz CPU *Estimated time **Time-frame expansion (higher coverage possible with more CPU time)
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Genetic Algorithms (GAs)

Theory of evolution by natural selection (Darwin, 1809-82.)

C. R. Darwin, On the Origin of Species by Means of Natural Selection, London: John Murray, 1859. J. H. Holland, Adaptation in Natural and Artificial Systems, Ann Arbor: University of Michigan Press, 1975. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Reading, Massachusetts: Addison-Wesley, 1989. P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design, Layout and Test Automation, Upper Saddle River, New Jersey, Prentice Hall PTR, 1999.

Basic Idea: Population improves with each generation.

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Population Fitness criteria Regeneration rules

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GAs for Test Generation

Population: A set of input vectors or vector sequences. Fitness function: Quantitative measures of population succeeding in tasks like initialization and fault detection (reciprocal to cost functions.) Regeneration rules (heuristics): Members with higher fitness function values are selected to produce new members via transformations like mutation and crossover.

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Strategate Results
s1423
Total faults Detected faults 1,515 1,414

s5378
4,603 3,639

s35932
39,094 35,100

Fault coverage
Test vectors CPU time HP J200 256MB

93.3%
3,943 1.3 hrs.

79.1%
11,571 37.8 hrs.

89.8%
257 10.2 hrs.

Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, Dynamic State Traversal for Sequential Circuit Test Generation, ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, July 2000.
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Spectral Methods
Replace with compacted vectors
Test vectors (initially random vectors) Fault simulation-based vector compaction

Compacted vectors

Append new vectors

Stop

Yes

Extract spectral characteristics (e.g., Hadamard coefficients) and generate vectors

Stopping criteria (coverage, CPU time, vectors) satisfied?

No

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Spectral Information

Random inputs resemble noise and have low coverage of faults. Sequential circuit tests are not random:

Vector compaction removes unnecessary vectors without reducing fault coverage:

Some PIs are correlated. Some PIs are periodic. Correlation and periodicity can be represented by spectral components, e.g., Hadamard coefficients.

Compaction is similar to noise removal (filtering) and enhances spectral characteristics.

Reverse simulation for combinational circuits (Example 5.5.) Vector restoration for sequential circuits.

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Spectral Method: s5378

Simulation-based methods Time-frame expansion Spectral-method* Strategate Contest Hitec Gentest Fault cov. Vectors CPU time Platform 79.14% 734 43.5 min. Ultra Sparc 10 79.06% 11,571 37.8 hrs. Ultra Sparc 1 75.54% 1,722 12.0 min. Ultra II 70.19% 912 18.4 hrs. 72.58% 490 5.0 hrs.

HP9000/J200 Ultra II

* A. Giani, S. Sheng, M. S. Hsiao and V. D. Agrawal, Efficient Spectral Techniques for Sequential ATPG, Proc. IEEE Design and Test in Europe (DATE) Conf., March 2001.

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Summary

Fault simulation is an effective tool for sequential circuit ATPG. Tests can be generated for any circuit that can be simulated. Timing considerations allow dealing with asynchronous circuits. Simulation-based methods generate better tests but produce more vectors, which can be reduced by compaction. A simulation-based method cannot identify untestable faults. Spectral methods hold potential.

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