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Module 2 – Floorplanning & Placement

16.1.1 Goals of floorplanning
1) Arrange the blocks on a chip
2) Decide the location of I/O pads
3) Decide the location and number of the power pads
4) Decide the type of power distribution
5) Decide the location & type of power distribution
Objectives of floorplanning
1) To minimize the chip area
2) Minimize delay

16.1.2 Measurement of dlay in floorplanning

Delay in floorplanning is decided by predicted capacitance. In turn, predicted capacitance depends
on
1) Interconnect lengths as a function of fanout (FO) and circuit block size
2) Wire-load table as shown below predicts the capacitance and delay of a net.

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Graph showing worst-case interconnect delay v/s feature size

It can be seen that, As we scale circuits, the worst-case interconnect delay increases

16.1.3 Floorplanning tool generates random floor plan. It consists of flexible blocks, fixed blocks,
Seeding is a process of randomization with a starting value called ‘seed’. Advantage of seeding is
that we can repeat a random number sequence by supplying the same number sequence by
supplying the same seed.

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CONGESTION ANALYSIS
Fig (a) shows the initial floorplan generated with a 2:1.5 aspect ratio
Fig (b) shows the altered floor plan with 1:1 chip aspect ratio
Fig(c) shows a trial floorplan with a congestion map. Here blocks A & C have been placed
With the terminal positions in the channels. Shading indicates the ratio of channel density to
channel capacity. As shown in the side box, routing congestion of 200%, 100% and 50% are
indicated with different shadings. Shading indicates the ratio of channel density to the
channel capacity. Dark areas show regions that cannot be routed because the channel
congestion exceeds the estimated capacity.
Fig(d) Resizing flexible blocks A and C alleviates congestion.
FLOORPLANNING CELL-BASED ASICS
Fig (a) shows the initial floorplan generated by the floorplanning tool. A & C are the two flexible
blocks and contains rows of standard cells (unplaced) A pop-up window shows the status of block
A
Fig (b) shows the estimated placement for blocks A and C. The connector positions are known and
a rat’s nest display shows the heavy congestion below box B

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Fig(c) shows
fig(c) shows one method of improving floor plan
Fig(d) The updated display shows the reduced congestion after the changes.

ROUTING A T-JUNCTION BETWEEN TWO CHANNELS IN TWO-LEVEL METAL

The dots represent logic cell pins
Fig a) shows , if the channel A (the stern of the T) is first routed, the width of channel B can be
adjusted.
Fig b) shows, if the channel B (the top of the T) is first routed, the width of channel A can be
adjusted.

16.1.4 CHANNEL DEFINITION

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Defining the channel routing order for a slicing floorplan using a slicing tree

Fig a) shows the method of cutting all the way across the chip between circuit blocks. Slicing is
continued until each piece contains just one block It can be seen that, each cut divides a piece into
two without cutting through a circuit block.
Fig b) shows a sequence of cuts: 1, 2, 3 and 4 that successively slices the chip until only one circuit
blocks are left
Fig c) shows the slicing tree corresponding to the sequence of cuts which gives the order in which
to route the channels: 4, 3, 2 and finally 1

Cyclic constraints
Fig a) shows a nonslicing floorplan with a cyclic constraint that prevents routing
Fig b) shows a the difficulty of finding a slicing floorplan without increasing the chip are.
Fig c) shows a floorplan which is sliced with initial cuts 1 or 2, but it has no cyclic constraints and
it is inefficient in area use and it will be very difficult to route.
Channel definition and ordering

Fig a) shows another type of channel definition which eliminates the cyclic constraint by merging
the blocks A & C
Fig c) shows a slicing structure
16.1.5 I/O PLANNING
Key words used are die, Chip carrier, package, bonding, pads, lead frame, core

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Pad ring, pad-limied die, core-limited die, pad-limited pads, core-limited pads, power pads, power
buses (Power rails), power ring, dirty power, clean power, electrodstatic discharge (ESD), chip
cavity, substrate connection, downbond ( or drop bond), pad seed, double bond. Multiple-signal
pad, oscillator pad, clock pad, corner pad, edge pads, two-pad corner cell, bond-wire angle design
rules, simultaneously switching outputs (SSOs), pad mapping, logical pad, physical pad, pad
library, pad-format changer or hybrid corner pad, global power nets, mixed-power supplies,
multiple power supplies, stagger-bond, area-bump, ball grid-array (BGA), pad slot (or pad site),
I/O-cell pitch, pad pitch, channel spine, preferred layer, preferred direction.

There are two types of dies- Pad-limited and core-limited die

Fig a) shows a pad-limited die- Here the die size is determined by the number of pads
Fig b) shows a core-limited die- Here the die size is determined by the core logic
Fig c) shows both pad-limited and core-limited pads for a square die.
BONDING PADS

Fig a) shows the chip which uses both pad-limited and core-limited pads
Fig b) shows hybrid corner pad

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Fig c) shows a chip with stagger bonded pads

Fig d) shows an area-bump bonded chip (or flip-chip). The chip is turned upside-down and solder
bumps connect the pads the lead frame.
GATE ARRAY I/O PADS

Fig a) shows a Cell-based ASICs containg pad cells of different sizes and widths.
Fig b) shows a corner of gate-array base.
Fig c) shows a gate-array base with different I/O cells and pad pitches

POWER PLANNING -

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Fig a) shows power distribution using m1 for VSS and M2 for VDD. This helps minimize the
number of vias and layer crossings needed but causes problems in the routing channels.
Fig b) shows a floorplan in which m1 is run parallel to the longest side of all channels and the
channel spine. This can make automatic routing easier but may increase the number of vias and
layer crossings
Fig c) shows an expanded view of part of a channel (interconnect is shown as lines). If power runs
on different layers along the spine of a channel, this forces signals to change layers.
Fig d) shows a closeup of VDD and VSS busses as they cross. Changing layers requires a large
number of via contacts to reduce resistance.

CLOCK PLANNING – CLOCK SPINE AND CLOCK TREE

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Fig a) shows a Clock spine for a gate array

Fig b) shows a clock spine for a cell-based ASIC (typical chips have thousands of clock nets)
Fig c) shows a clock spine driven from one or more clock driver cells. Delay in the dirver cell is a
function of the numbers of stages and the ration of output to input capacitance for each stage (taper)
Fig d) shows a clock latency and clock skew. Different techniques has to be used to minimize both
latency and skew.
CLOCK TREE

Fig a) shows a Clock tree with minimum delay by adopting the technique of tapering in about 3
successive steps.
Fig b) shows a clock tree with a faout of three successive nodes.
Fig c) shows a clock tree for a cell-based ASIC
16.2 PLACEMENT : Placement is more suited to automation than floorplanning. So we need
measurement techniques and algorithms.
16.2.2 Goals and Objectives

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Goals of Placement
1) should assure that the router can complete the routing step
2) should minimize all the critical net delays
3) should make the chip as dense as possible
Objectives of Placement
1) Should minimize power dissipation
2) Should minimize crosstalk between signals
16.2.3 Measurement of Placement Goals and Objectives
Key words used are :
Steiner trees, Rectilinear routing, Manhattan routing, Euclidean distance,
minimum rectilinear Steiner tree (MRST), bounding box, half-perimeter measure (or bounding-box
measure), meander factor, interconnect congestion, maximum cut line,
cut size, timing-driven placement, metal usage
Placement using Trees on Graphs
Fig a) shows a floorplan using trees on graph method
Fig b) shows an expanded view of the flexible block A having four rows of standard cells for
placement. (typical blocks may contain thousands or tens of thousands of logic cells).
To find the length of the net shown with four terminals, W through Z, by using
placement of four logic cells (labelled: A.211, A.19, A.43, A.25).
Fig c) shows nets (W, X, Y, Z) are drawn as a graph. The shortest connection is the minimum
Steiner tree.
Fig d) shows the minimum rectilinear Steiner tree using Manhattan routing. The rectangular
(Manhattan) interconnect-length measures are shown for each tree.

MEASUREMENT OF INTERCONNECT-LENGTHS

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Above figure shows the rectangular (Manhattan) interconnect-length measures for each tree
Fig a) shows Complete-graph measure.
Fig b) shows Half-perimeter measure.
MEASUREMENT OF INTERCONNECT CONGESTION FOR A CELL-BASED ASIC.

fig a) shows the measurement of congestion for a cell-based ASIC

fig b) shows an expanded view of flexible block a having maximum cut line.

16.2.4 Min-cut placement algorithm

Fig a) shows a an example of Min-cut method of placement by using Eigen value placement
technique
Fig b) shows one dimensional placement. Gere the small black squares represent the centers of the
logic cells.
Fig c) shows two dimensional placement. Here The eigenvalue method takes no account of the
logic cell sizes or actual location of logic cell connectors.
Fig d) shows the complete layout. Here the logic cells has been snapped to valid locations, leaving
room for the routing in the channel.

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16.2.6 Iterative placement improvement

The key words used during iterative placement are
i) iterative exchange
ii) -optimum
iii) Neighbourhood exchange algorithm
iv) -neighbourhood
v) Force-directed placement methods
vi) Hooke’s law
vii) force-directed interchange
viii) Force-directed relaxation
ix) Force-directed pairwise relaxation
Fig a) shows the method of Swapping the source logic cell with a destination logic cell in pairwise
interchange.
Fig b) shows the method of Swapping more than two logic cells at a time to reach an optimum
placement, but this is expensive in computation time. Limiting the search to neighborhoods reduces
the search time. Logic cells within a distance  of a logic cell form an  -neighborhood.
Fig c) Shows the method of one-neighbourhood.
Fig d) Shows the method of two-neighbourhood.

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Force directed Placement:

Fig a) shows the method of force directed placement having network with nine logic cells.
In fig b) shows the method of making a grid (one logic cell per bin).
In fig c), Forces are calculated as if springs were attached to the centers of each logic cell for
each connection. The two nets connecting logic cells A and I correspond to two springs.
In fig d) The forces are proportional to the spring extensions.
Force directed Iterative Placement improvement:
Fig a) shows the method of Force-directed interchange.
Fig b) shows the method of Force-directed relaxation.
Fig c) shows the method of Force-directed pairwise relaxation.

16.2.8 Timing driven Placement methods

Concepts: zero-slack algorithm primary inputs • arrival times • actual times •

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required times • primary outputs • slack time

THE ZERO-SLACK ALGORITHM.

(a) The circuit with no net delays.

(b) The zero-slack algorithm adds net delays (at the outputs of each gate, equivalent to
increasing the gate delay) to reduce the slack times to zero.

16.2.9 A simple placement example:

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Fig a) shows the network to be placed

Fig b) shows a placement where the bin size is equal to the logic cell size and all
the logic cells are assumed to be of equal size.
Fig c) shows an alternative placement with a lower total routing length.
Fig d) shows A layout that might result from the placement shown in b.
The channel densities correspond to the cut-line sizes.
It may be noticed that all the logic cells are not of the same size (which means there
are errors in the interconnect-length estimates we made during placement)
16.3 PHYSICAL DESIGN FLOW:
Timing-driven floorplanning and placement design flow.
Because interconnect delay now dominates gate delay, the trend is to include placement
within a floorplanning tool and use a separate router.
1. Design entry. The input is a logical description with no physical information.
2. Initial synthesis. The initial synthesis contains little or no information on any interconnect
loading.The output of the synthesis tool (typically an EDIF netlist) is the input to the floorplanner.
3. Initial floorplan. From the initial floorplan interblock capacitances are input to the synthesis
tool as load constraints and intrablock capacitances are input as wire-load tables.
4. Synthesis with load constraints. At this point the synthesis tool is able to resynthesize the
logic based on estimates of the interconnect capacitance each gate is driving. The synthesis
tool produces a forward annotation file to constrain path delays in the placement step.
5. Timing-driven placement. After placement using constraints from the synthesis tool, the

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location of every logic cell on the chip is fixed and accurate estimates of interconnect delay
can be passed back to the synthesis tool.
6. Synthesis with in-place optimization (IPO).The synthesis tool changes the drive strength
of gates based on the accurate interconnect delay estimates from the floorplanner without
altering the netlist structure.
7. Detailed placement. The placement information is ready to be input to the routing step.

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ROUTING

17.1 GOALS
Goal is to provide complete instructions to the detailed router•
OBJECTIVES:
1) Minimize the total interconnect length
2) Maximize the probability that the detailed router can complete the routing
3) Minimize the critical path delay

17.1.2 MEASUREMENT OF INTERCONNECT DELAY Key terms and concepts:

lumped-delay model • lumped capacitance • as interconnect delay becomes more important
other, more complex models, are used

Measuring the delay of a net.

Fig a) shows the inverter circuit. A driving a net with a fanout of two. Voltages V1 , V2 , V3 , and
V4 are the voltages at intermediate points along the net.
Fig b) shows the layout with the net segments (pieces of interconnect).
Fig c) shows the RC model with each segment replaced by a capacitance and resistance. The ideal
switch and pull-down resistance Rpd model the inverter A
17.1.3 & 17.1.4 GLOBAL ROUTING METHODS
Global routing between blocks - Global routing for a cell-based ASIC formulated as a graph
problem

Fig a) shows a cell-based ASIC with numbered channels.

Fig b) shows the channels form the edges of a graph.
Fig c) shows the channel-intersection graph. Each channel corresponds to an edge on a graph
whose weight corresponds to the channel length.

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17.1.7 BACK ANNOTATION

Fig a) shows a cell-based ASIC showing a single net with a fanout of four (five terminals). We
have to order the numbered channels to complete the interconnect path for terminals A1 through
F1.
Fig b) shows that the terminals are projected to the center of the nearest channel, forming a graph.
A minimum-length tree for the net that uses the channels and takes into account the channel
capacities.
Fig c) shows that the minimum-length tree does not necessarily correspond to minimum delay. If
we wish to minimize the delay from terminal A1 to D1, a different tree might be better.

Gate-array global routing.

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Fig a) shows a small gate array.

Fig b) shows an enlarged view of the routing. The top channel uses three rows of gate-array base
cells; the other channels use only one.
Fig c) shows a further enlarged view showing how the routing in the channels connects to the logic
cells.
Fig d) shows one of the logic cells, an inverter.
Fig e) shows that there are seven horizontal wiring tracks available in one row of gate-array base
cells— the channel capacity is thus 7.

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