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Derivation of State Graphs and Tables 431

14.1 Design of a Sequence Detector

To illustrate the design of a clocked Mealy sequential circuit, we will design a
sequence detector. The circuit has the form shown in Figure 14-1.

FIGURE 14-1
Sequence Detector X Z
to be Designed

Clock

The circuit will examine a string of 0’s and 1’s applied to the X input and generate an
output Z  1 only when a prescribed input sequence occurs. It will be assumed that the
input X can only change between clock pulses. Specifically, we will design the circuit
so that any input sequence ending in 101 will produce an output Z  1 coincident with
the last 1. The circuit does not reset when a 1 output occurs. A typical input sequence
and the corresponding output sequence are
X  0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0
Z  0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 (14-1)
(time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)
Initially, we do not know how many flip-flops will be required, so we will designate the
circuit states as S0, S1, etc., and later assign flip-flop states to correspond to the circuit
states.We will construct a state graph to show the sequence of states and outputs which
occur in response to different inputs. Initially, we will start the circuit in a reset state des-
ignated S0. If a 0 input is received, the circuit can stay in S0 because the input sequence
we are looking for does not start with 0. However, if a 1 is received, the circuit must go
to a new state (S1) to “remember” that the first input in the desired sequence has been
received (Figure 14-2). The labels on the graph are of the form X/Z, where the symbol
before the slash is the input and the symbol after the slash is the corresponding output.
When in state S1, if we receive a 0, the circuit must change to a new state (S2) to
remember that the first two inputs of the desired sequence (10) have been received.
If a 1 is received in state S2, the desired input sequence (101) is complete and the out-
put should be l. The question arises whether the circuit should then go to a new state
or back to S0 or S1. Because the circuit is not supposed to reset when an output
occurs, we cannot go back to S0. However, because the last 1 in a sequence can also
be the first 1 in a new sequence, we can return to S1, as indicated in Figure 14-3.

FIGURE 14-2 0
0

1
S0 0

S1

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432 Unit 14

FIGURE 14-3 0 1
S0 0
0
1
1 S1

S2 0
0

The graph of Figure 14-3 is still incomplete. If a 1 input occurs when in state S1, we
can stay in S1 because the sequence is simply restarted. If a 0 input occurs in state S2, we
have received two 0’s in a row and must reset the circuit to state S0 because 00 is not
part of the desired input sequence, and going to one of the other states could lead to an
incorrect output.The final state graph is given in Figure 14-4. Note that for a single input
variable each state must have two exit lines (one for each value of the input variable)
but may have any number of entry lines, depending on the circuit specifications.

FIGURE 14-4 0 1
Mealy State Graph S0 0
0
for Sequence 1 1
Detector 0 1 S1 0
0

S2 0
0

State S0 is the starting state, state S1 indicates that a sequence ending in 1 has
been received, and state S2 indicates that a sequence ending in 10 has been
received. An alternative way to start the solution would be to first define states
in this manner and then construct the state graph. Converting the state graph to
a state table yields Table 14-1. For example, the arc from S2 to S1 is labeled 1/1.
This means that when the present state is S2 and X  1, the present output is 1.
This 1 output is present as soon as X becomes 1, that is, before the state change
occurs. Therefore, the 1 is placed in the S2 row of the table.

TABLE 14-1 Present

Present Next State Output
State X0 X1 X0 X1
S0 S0 S1 0 0
S1 S2 S1 0 0
S2 S0 S1 0 1

At this point, we are ready to design a circuit which has the behavior described by
the state table. Because one flip-flop can have only two states, two flip-flops are needed
to represent the three states. Designate the two flip-flops as A and B. Let flip-flop states
A  0 and B  0 correspond to circuit state S0; A  0 and B  1 correspond to S1; and
A  1 and B  0 correspond to circuit state S2. Each circuit state is then represented by
a unique combination of flip-flop states. Substituting the flip-flop states for S0, S1 and S2
in the state table yields the transition table (Table 14-2).

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Derivation of State Graphs and Tables 433

TABLE 14-2 A+B+ Z

AB X0 X1 X0 X1
00 00 01 0 0
01 10 01 0 0
10 00 01 0 1

From this table, we can plot the next-state maps for the flip-flops and the map for
the output function Z:

X X X
AB 0 1 AB 0 1 AB 0 1

00 0 0 00 0 1 00 0 0

01 1 0 01 0 1 01 0 0

11 X X 11 X X 11 X X

10 0 0 10 0 1 10 0 1

A+ = X ′B B+ = X Z = XA

The flip-flop inputs are then derived from the next-state maps using the
same method that was used for counters (Section 12.4). If D flip-flops are used,
DA  A  X B and DB  B  X, which leads to the circuit shown in Figure 14-5.
Initially, we will reset both flip-flops to the 0 state. By tracing signals through the
circuit, you can verify that an output Z  1 will occur when an input sequence
ending in 101 occurs. To avoid reading false outputs, always read the value of
Z after the input has changed and before the active clock edge.

FIGURE 14-5
A′ A B′ B

Ck Ck
D D

Clock

The procedure for finding the state graph for a Moore machine is similar to that
used for a Mealy machine, except that the output is written with the state instead of
with the transition between states. We will rework the previous example as a Moore
machine to illustrate this procedure. The circuit should produce an output of 1 only
if an input sequence ending in 101 has occurred. The design is similar to that for the

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434 Unit 14

Mealy machine up until the input sequence 10 has occurred, except that 0 output is
associated with states S0, S1, and S2:

S0 1 S1
0
0 0

S2
0

Now, when a 1 input occurs to complete the 101 sequence, the output must become 1;
therefore, we cannot go back to state S1 and must create a new state S3 with a 1 output:

S0 1 S1
0
0 0

S3 1 S2
1 0

We now complete the graph, as shown in Figure 14-6. Note the sequence 100 resets
the circuit to S0. A sequence 1010 takes the circuit back to S2 because another 1
input should cause Z to become 1 again.

FIGURE 14-6 S0 1 S1
0 1
Moore State Graph 0 0
for Sequence
Detector 0
1 0
1
S3 S2
1 0
0

The state table corresponding to the circuit is given by Table 14-3. Note that there
is a single column for the output because the output is determined by the present state
and does not depend on X. Note that in this example the Moore machine requires one
more state than the Mealy machine which detects the same input sequence.

TABLE 14-3 Present Next State Present

State X0 X1 Output(Z)
S0 S0 S1 0
S1 S2 S1 0
S2 S0 S3 0
S3 S2 S1 1

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Derivation of State Graphs and Tables 435

Because there are four states, two flip-flops are required to realize the circuit. Using
the state assignment AB  00 for S0, AB  01 for S1, AB  11 for S2, and AB  10 for
S3, the following transition table for the flip-flops results (Table 14-4):

TABLE 14-4 A+B+

AB X0 X1 Z
00 00 01 0
01 11 01 0
11 00 10 0
10 11 01 1

The output function is Z  AB . Note that Z depends only on the flip-flop states
and is independent of X, while for the corresponding Mealy machine, Z was a func-
tion of X. The derivation of the flip-flop input equations is straightforward and will
not be given here.

14.2 More Complex Design Problems

In this section we will derive a state graph for a sequential circuit of somewhat greater
complexity than the previous examples. The circuit to be designed again has the form
shown in Figure 14-1. The output Z should be 1 if the input sequence ends in either
010 or 1001, and Z should be 0 otherwise. Before attempting to draw the state graph,
we will work out some typical input-output sequences to make sure that we have a
clear understanding of the problem statement. We will determine the desired output
sequence for the following input sequence:
X  0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 1 0
↑ ↑ ↑ ↑ ↑ ↑
a b c d e f
Z  0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 0
At point a, the input sequence ends in 010, one of the sequences for which we are look-
ing, so the output is Z  1. At point b, the input again ends in 010, so Z  1. Note that
overlapping sequences are allowed because the problem statement does not say any-
thing about resetting the circuit when a 1 output occurs. At point c, the input sequence
ends in 1001, so Z is again 1. Why do we have a 1 output at points d, e, and f ? This is
just one of many input sequences.A state machine that gives the correct output for this
sequence will not necessarily give the correct output for all other sequences.
We will start construction of the state graph by working with the two sequences
which lead to a 1 output.Then, we will later add arrows and states as required to make
sure that the output is correct for other cases. We start off with a reset state S0 which
corresponds to having received no inputs. Whenever an input is received that corre-
sponds to part of one of the sequences for which we are looking, the circuit should go
to a new state to “remember” having received this input. Figure 14-7 shows a partial
state graph which gives a 1 output for the sequence 010. In this graph S1 corresponds

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Derivation of State Graphs and Tables 439

FIGURE 14-12 S0 1 S1 State Input Sequences

0 1 0 S0 Reset or even 1’s
e d S1 Odd 1’s
0 0
1 b S2 Even 1’s and ends in 0
S2 1 S5 S3 Even 1’s and 00 has occurred
0 0 S4 Odd 1’s and 00 has occurred
S5 Odd 1’s and ends in 0
0 0
f cg
S3 1 S4
0 0
0 1 1
Even 1’s Odd 1’s

0’s can be ignored.Therefore, we can stay in S3 (arrow f ). Similarly, extra 0 inputs can be
ignored in S4 (arrow g).This completes the Moore state diagram, and we should go back
and verify that the correct output sequence is obtained for various input sequences.

14.3 Guidelines for Construction of State Graphs

Although there is no one specific procedure which can be used to derive state
graphs or tables for every problem, the following guidelines should prove helpful:
1. First, construct some sample input and output sequences to make sure that you
understand the problem statement.
2. Determine under what conditions, if any, the circuit should reset to its initial state.
3. If only one or two sequences lead to a nonzero output, a good way to start is to
construct a partial state graph for those sequences.
4. Another way to get started is to determine what sequences or groups of
sequences must be remembered by the circuit and set up states accordingly.
5. Each time you add an arrow to the state graph, determine whether it can go to
one of the previously defined states or whether a new state must be added.
6. Check your graph to make sure there is one and only one path leaving each
state for each combination of values of the input variables.
7. When your graph is complete, test it by applying the input sequences formulated
in part 1 and making sure the output sequences are correct.
Several examples of deriving state graphs or tables follow.

A sequential circuit has one input (X) and one output (Z). The circuit examines groups
Example 1 of four consecutive inputs and produces an output Z  1 if the input sequence 0101 or
1001 occurs. The circuit resets after every four inputs. Find the Mealy state graph.
Solution A typical sequence of inputs and outputs is
X  0101 0010 1001 0100
| |
Z  0001 0000 0001 0000 |
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440 Unit 14

The vertical bars indicate the points at which the circuit resets to the initial state.
Note that an input sequence of either 01 or 10 followed by 01 will produce an output of
Z  1. Therefore, the circuit can go to the same state if either 01 or 10 is received. The
partial state graph for the two sequences leading to a 1 output is shown in Figure 14-13.
Note that the circuit resets to S0 when the fourth input is received. Next, we add
arrows and labels to the graph to take care of sequences which do not give a 1
output, as shown in Figure 14-14.
FIGURE 14-13 State Sequence Received
0 S0
Partial State S0 Reset
0
Graph for 1 S1 0
Example 1 0
S1 S2 S2 1
S3 01 or 10
0 S4 010 or 100
1 0 1
0 1
S3

0
0

S4

FIGURE 14-14 State Sequence Received

S0
Complete State 0 1 S0 Reset
Graph for 0 0 S1 0
Example 1 1 S2 1
S1 1 S2
0 0 S3 01 or 10
0 0 0 0
0 0 0 S4 010 or 100
0
1 1 S5 Two inputs received, no 1
0 S5 S3 1 output is possible
S6 Three inputs received, no 1
0 1 0 output is possible
0 0 1 0
0
S6 S4

The addition of states S5 and S6 was necessary so that the circuit would not reset
to S0 before four inputs were received. Note that once a 00 or 11 input sequence has
been received (state S5), no output of 1 is possible until the circuit is reset.

A sequential circuit has one input ( X) and two outputs ( Z1 and Z2). An output
Example 2 Z1  1 occurs every time the input sequence 100 is completed, provided that the
sequence 010 has never occurred. An output Z2  1 occurs every time the input
sequence 010 is completed. Note that once a Z2  1 output has occurred, Z1  1
can never occur but not vice versa. Find a Mealy state graph and table.

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 be loaded
Once St L product register will
with values and multiplicand is available at
adder inputs Hence Load L Stl Load
at this state Circuit will check for M bit
if m I the addition will happen Adt and
will move to next state lata will shift the
product register by making Sh l and move to

If M o the addition will be skipped at will

only
shift the product register and will move to
S
MlAd M 1 Ad 1 add the multiplier

mysh
M o Ad o Sh l sn Shh shif product register

Cdn stifftaggy

The same sequence will be continued till

at the control circuit goes to bone state
and terminates the multiplication process

324
 Serial Adder with Accumulator

The figure below shows the block diagram of

serial adder with accumulator
stcstart
Si
5th
J kg R2 K xo di
g
segno

control I
circuit
SI egg
iff
I Sh f 43 42 Yi Yo Yi g
I
d c Citi
CLK

Q D

a Ena
Agg

Two swift registers used to hold the

are
4 bit numbers to be added X and Y
X register is accumulator and Y register is
addend register
When addition is completed content of
X'register is replaced with the sum
of X and Y
Y register is a cyclic shift register such
that at the end of four clock pulses
the value in addend
register is back to
SI is serial input Sh is
original state 325
 g
Sh I allows the value at SI to enter into
the shift register and values at acs aux will
get shifted night and no value will be available
at the input of full adder A similar
happens to the Y also
operation register
The result of addition of Ko and
yo will
be sum So and

Carry carny is fed as carry in

Ci This
while adding Ki and Yi
since Ci need to bae added with Xi and Yi
Ci will be stored in D register and will arrive
at the input of full adder during next clock pulse

only
At every clock pulse the next Isb of and
will arriveinput of full adder and will
at the
be added along with carry generated by previous
bit's addition
The figure below shows a numerical example
the
for same
X Y Ci Si Cit
to 0101 0111 O O l

ti 0010 1011 I O l

1320001 1101 I 1 I

3 1000 1110 I 1 O
326
tu 1100 0111 0 l O
 723 2274 Xo so So 23 12 74
no Si
Full Full
adder adder
43 41 42 Yo yo Yo 43 42 41 7
a Cz
Ct
Coto
DL DL
at to att

51 So 13 K2 s 5251 So 13 Sz
gz
Full Full
added adder
41 Yo 43 42 42 y yo yz
3 Cy
CZ C3
D DC
at Ez at c z

S3 S2 51 So notcured at 4
Full
434241 Yo
adder accumulator is
notused
filled with Blum MP
Goto
atta Dc

Designofcontrolcircintforsenaladderi
After receiving a stout signal Lst 1 control circuit
will put out four swift signals Ski and stops Sto
The state diagram is shown here
SHSh
St state input so
Sh ShiftsignedMp S3 Si
f L 327
H1 Sz Y
 A B
let So 00

Si 01

Sz I 0

53 I 1 Da At
AB
SE A B At Bt 5h st

O
ooo
O I 1
ooo
0 I
l
I O l I i DA AB ABT A B
I 1 O O I
O O o y
DBCBt
I I I 0 AB 01 11 10
I O l 1 gf 100
I i 1 o o I O

D
Oo
f C
DB St B t A B
Sh ADOO 01 11
10
St o O I l l
l
TDAR
DI DBQB sh St 1 A 113
a a

on

Realization of Controller circuit

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Circuits for Arithmetic Operations 607

FIGURE 18-13
Block Diagram for 9
Divider Using Bus Load
Ld
Notation Su Sh X (8:0) 0
Sh
Clock 9

Load 9-Wide
0 2-to-1 MUX 1

9 9
Bus
Merger
5 1 0 8

5-bit 3 Dividend (7:0)

Subtracter

X (8:4) 5
X (3:1)

0 4 X0 Bus
Splitter
Y (3:0) 9
(Divisor)

represents a bus splitter that splits the 9 bits from the X register into X8X7X6X5X4
and X3X2X1; X0 is not used. Bus mergers and splitters do not require any actual
hardware; they are just a symbolic way of showing bus connections.
The X register is a left-shift register with parallel load capability, similar to the
register in Figure 12-10. On the rising clock edge, it is loaded when Ld  1
and shifted left when Sh  1. Because the register must be loaded with the divi-
dend when Load  1 and with the subtracter output when Su  1, Load and
Su are ORed together and connected to the Ld input. The MUX selects the
dividend (preceded by a 0) when Load  1. When Load  0, it selects the bus
merger output which consists of the subtracter output, X3X2X1, and a logic 1.
When Su  1 and the clock rises, this MUX output is loaded into X. The net
result is that X8X7X6X5X4 gets the subtracter output, X3X2X1 is unchanged, and
X0 is set to 1.

Programmed Exercise 18.1

Cover the lower part of each page with a sheet of paper and slide it down as you
check your answers. Write your answer in the space provided before looking at the
correct answers.

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