Counter Sinkron 3 bit
OUTPUT Q OUTPUT Q'
CLK Present Next State Present Next State
State (PS) (NS) State (PS) (NS)
C B A C B A C B A C B A
1 0 0 0 0 0 1 1 1 1 1 1 0
2 0 0 1 0 1 0 1 1 0 1 0 1
3 0 1 0 0 1 1 1 0 1 1 0 0
4 0 1 1 1 0 0 1 0 0 0 1 1
5 1 0 0 1 0 1 0 1 1 0 1 0
6 1 0 1 1 1 0 0 1 0 0 0 1
7 1 1 0 1 1 1 0 0 1 0 0 0
8 1 1 1 0 0 0 0 0 0 1 1 1
Counter Sinkron 4 bit
OUTPUT Q OUTPUT Q'
Present Next State Present Next State
CLK
State (PS) (NS) State (PS) (NS)
DCBA DCBA DCBA DCBA
1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
2 0 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1
3 0 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0
4 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1
5 0 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0
6 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1
7 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0
8 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1
9 1 0 0 0 1 0 0 1 0 1 1 1 0 1 1 0
10 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1
11 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0
12 1 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1
13 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0
14 1 1 0 1 1 1 1 0 0 0 1 0 0 0 0 1
15 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 0
16 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1