ASSAM UNIVERSITY
CMOS Two stage op-amp in 180nm technology
A mini project report submitted in partial fulfilment of the requirements for the
degree of Bachelor of Technology
in
Electronics and Communication Engineering
Under the guidance of:
Prof. Debaprasad Das
Department of Electronics and Communication
Engineering
Triguna Sen School of Tehnology
Department of Electronics and communication
Engineering Assam University, Silchar 788011
August 2024
Declaration of Authorship
I/We, thee undersigned, declare that this report/thesis titled, 'CMOS two stage op--amp in 180nm
technology' and the work presented i n this thesis/report iis my/our own. I /We confirm that this work
submitted f or assessment is my/our own and i s expressed in my/our own words. Any uses made
within it of the works of other authors i n any form ( e.g., ideas, equations, figures, text, tables,
programs) are properly acknowledged at any point of their use . To the best of my/our
knowledge and belief, the same report has not been submitted either by me/us or by any other
person f or the award of any other degree or diplo
diploma of the university or other institute
nstitute of higher
learning.
1. Arif Iqbal Hussain
2. K.B.Chandrashekaran
3. Sagnikta Saha
Date:
Place:
i
“You have to dream before your dreams come true.”
Dr. A.P.J. Abdul Kalam
Design Of Two Stage CMOS Operational Amplifier
in 180nm Technology.
Abstract—In this paper a CMOS two stage operational amplifier has been presented which operates
at 1.8 V power supply at 0.18 micron (i.e., 180 nm) technology and whose input is depended on Bias
Current. The op-amp provides a gain of 69dB and a bandwidth of 140 kHz for a load of 1 OF. This
op-amp has a Common Mode gain of -25 dB, an output slew rate of 32 V/µs, and a output voltage
swing. The power consumption for the op-amp is 300µW.
Index Terms—Phase Margin, Gain Bandwidth Product, CMRR, ICMR, CMOS Analog circuit.
I. INTRODUCTION
The trend towards low voltage low power silicon chip systems has been growing due to the increasing
demand of smaller size and longer battery life for portable applications in all marketing segments including
telecommunications, medical, computers and consumer electronics. The operational amplifier is
undoubtedly one of the most useful devices in analog electronic circuitry. Op-amps are built with different
levels of complexity to be used to realize functions ranging from a simple dc bias generation to high-speed
amplifications or filtering. With only a handful of external components, it can perform a wide variety of
analog signal processing tasks. Op-amps are among the most widely used electronic devices today, being
used in a vast array of consumer, industrial, and scientific devices. Operational Amplifiers, more commonly
known as Op-amps, are among the most widely used building blocks in Analog Electronic Circuits.
Op-amps are linear devices which has nearly all the proper- ties required for not only ideal DC
amplification but is used extensively for signal conditioning, filtering and for performing mathematical
operations such as addition, subtraction, integration, differentiation etc. Generally, an Operational
Amplifier is a 3-terminal device. It consists mainly of an Inverting input denoted by a negative sign, (”-”)
and the other a Non-inverting input denoted by a positive sign (”+”) in the symbol for opamp. Both these
inputs are very high impedance. The output signal of an Operational Amplifier is the magnified difference
between the two input signals or in other words the amplified differential input. Generally, the input stage
of an Operational Amplifier is often a differential amplifier.
An operational amplifier is a DC-coupled differential input voltage amplifier with a rather high gain.
In most general purpose op-amps there is a single ended output. Usually an op-amp produces an output
voltage a million times larger than the voltage difference across its two input terminals. For most general
applications of an opamp negative feedback is used to control the large voltage gain. The negative
feedback also largely determines the magnitude of its output (”closed- loop”) voltage gain in numerous
amplifier applications, or the transfer function required. The op-amp acts as a comparator when used
without negative feedback, and even in certain applications with positive feedback for regeneration. An
ideal opamp is characterized by a very high input impedance (ideally infinite) and low output impedance
at the output terminal(s) (ideally zero).to put it simply the op- amp is one type of differential amplifier.
This section briefly discusses the basic concept of op-amp. An amplifier with the general characteristics
of very high voltage gain, very high input resistance, and very low output resistance generally is referred
to as an opamp. Most analog applications use an opamp that has some amount of negative feedback.
The Negative feedback is used to tell the opamp how much to amplify a signal. And since opamps are so
extensively used to implement a feedback system, the required precision of the closed loop circuit
determines the open loop gain of the system.
For this design process, we will first demonstrate the formula of main properties of an operational
amplifier in SectionII, than we will introduce how we find the proper parameters for our design in
Section
III, the simulation result of our design will be presented in Section IV.
INTRODUCTION TO OP-AMP:
The operational amplifier is undoubtedly one of the most useful devices in analog electronic circuitry. Op-
amps are built with vastly different levels of complexity to be used to realize functions ranging from a simple
dc bias generation to high speed amplifications or filtering. With only a handful of external components, it can
perform a wide variety of analog signal processing tasks. Op-amps are among the most widely used electronic
devices today, being used ina vast array of consumer, industrial, and scientific devices. Operational Amplifiers,
more commonly known as Op-amps, are among the most widely used building blocks in Analog Electronic
Circuits. Op-amps are used equally in both analog and digital circuits.
Op-amps are linear devices which has nearly all the properties required for not only ideal DC amplification but
is used extensively for signal conditioning, filtering and for performing mathematical operations such as
addition, subtraction, integration, differentiation etc . Generally an Operational Amplifier is a 3-terminal
device. It consists mainly of an Inverting input denoted by a negative sign, ("-") and the other a Non-
inverting input denoted by a positive sign ("+") in the symbol for op-amp. Both these inputs are very high
impedance. The output signal of an Operational Amplifier is the magnified difference between the two input
signals or in other words the amplified differential input. Generally the input stage of an Operational Amplifier
is often a differential amplifier.
Our aim is to create the physical design and fabricate a low power Op-amp .An ideal op-amp having a single-
ended out is characterized by a differential input, infinite voltage gain, infinite input resistance and zero output
resistance. In a real op-amp however these characters cannot be generated but their performance has to be
sufficiently good for the circuit behavior to closely approximate the characters of an ideal op-amp in most
applications. With the introductionof each new generation of CMOS technologies design of op-amps continues
to pose further challenges as the supply voltages and transistor channel lengths scale down.
CHARACTERISTICS OF IDEAL AND THE REAL OP-AMPS
The main differences between the characteristics of ideal op-amp and the real op-amp are:-
1. Finite Gain: operational amplifiers are mainly used to amplify the input signal and the higher
its open loop gain the better as in many applications they are used with a feedback loop, so
ideal op-amps are characterized by a gain of infinity. For practical op-amps, the voltage gain is
finite. Typical values for low frequencies and small signals are A = 102 – 105, corresponding
to 40-100 dB gain.
2. Input impedance, (Zin): The Input impedance of an op-amp for an ideal device has to be
infinite to prevent any current flowing from the source supply into the amplifiers input
circuitry.
3. Bandwidth, (BW): An ideal operational amplifier has an infinite Frequency Response and can thus
be used to amplify signals of any frequency. However as evident from the frequency response curve
below the gain of the amplifier is not constant irrespective of frequency and after the first pole it
begins to drop with a slope of 20dB/decade thus the higher the frequency of the first pole the higher
the range of freq over which it operates desirably.
4. Finite Linear Range: The linear relation V0 = A (Va-Vb) between the input and output voltages
are valid only for a limited range of v0. Normally the maximum value of v0 for linear operation is
somewhat smaller than the positive dc supply voltage, the minimum value of v0 is somewhat
positive with respect to the negative voltage.
5. Offset Voltage: The amplifiers output is supposed to be completely independent of
common potentials applied to both inputs and is supposed to be zero when the voltage
difference between the inverting and non-inverting inputs is zero. For an ideal op-amp, if V a = Vb
(which is easily obtained by short circuiting the input terminals) then v0 = 0. In real devices, this is
not exactly true, and a voltage V0,off ≠ 0 will occur at the output for shorted inputs. Since v0,off is
usually directly proportional to the gain, the effect can be more conveniently described in terms of
the input offset voltage Vin,off, defined as the differential input voltage needed to restore v0=0 in the
real devices. For MOS op-amps Vin,off is about 5-15mV.
6. Common Mode Rejection Ratio (CMRR): The common-mode input voltage is defined by V in,c =
(Va + Vb)/2 as contrasted with the differential-mode input voltage Vin,d = Va - Vb. The differential
gain AD and also the common-mode gain AC which can be measured as shown in figure, where A c
= V0/ Vin,c. The CMRR is now defined as AD/Ac or in logarithmic value CMRR = 20 log10(A D /
Ac) in dB. Typical CMRR values for MOS amplifiers are in the 60-80 dB range. The CMRR
measures how much the op-amp can suppress common-mode signals at its inputs. These normally
represent undesirable noise, and hence a large CMRR is an important requirement.
7. Frequency Response: Because of stray capacitances, finite carrier mobilities and so-on, the gain A
decreases at high frequencies. It is usual to describe this effect in terms of the unity gain bandwidth,
that is the frequency f0 at which |A (f0)| = 1. For MOS op-amps, f0 is usually in the range of 1-10
MHz. It can be measured with the op-amp connected in a voltage-follower configuration.
8. Slew Rate: For a large input step voltage, some transistors in the op-amp may be driven out of their
saturation regions or completely cut-off. As a result the output will follow the input at a slower
finite rate. The maximum rate of change dV0/dt is called slew rate. It is not directly related to the
frequency response. For typical MOS op-amps slew-rates of 1~20 V/µs can be obtained.
9. Nonzero Output Resistance: For a real MOS op-amp, the open loop output impedance is nonzero. It
is usually resistive, and is of the order of 0.1-5KΩ for op-amps with an output buffer, it can be
much higher (~1MΩ) for op-amps with un-buffered output. This affects the speed with which the
op-amp can charge a capacitor connected to its output and hence the highest signal frequency.
10. Noise: The MOS transistor generates noise, which can be described in terms of an equivalent
current source in parallel with the channel of the device. The noisy transistors in an op-amp give
rise to a noise voltage von at the output of the op-amp, this can be again modeled by an equivalent
voltage source Vn = Von/A at the op-amp input. Unfortunately, the magnitude of this noise is
relatively high, especially in the low frequency band where the flicker noise of the input devices
is high; it is about 10 times the noise occurring in an op-amp fabricated in bipolar technology. In a
wideband (say in the 10Hz to 1MHz range), the equivalent input noise source is usually of the order
of 10~50µV RMS, in contrast to the 3~5µv achievable for low-noise bipolar op-amps.
SYSTEM OVERVIEW
For opamps used in many useful applications, rather a surprisingly large number of applications, the actual
amplifier performance is closely approximated by an idealized amplifier model. Indeed quite frequently
circuits are designed explicitly to insure acceptability of this approximation. And in other cases where
the idealization is not a sufficiently accurate approximation nevertheless it often provides a starting
point for an iterative process towards a final design. Consider the 741 amplifier, an older but proven
industry-standard device, which has a voltage gain exceeding 105 in normal operation. To cause an output
voltage change between representative saturation voltage limits of ±15 volts, i.e., a full thirty-volt output
change, the input voltage change involved is less than 0.3millivolt. Such a small voltage difference often
may be neglected, i.e., approximated as zero, when compared to other circuit voltages with which it is
associated in a KVL loop equation.
This section briefly discusses the basic concept of op-amp. An amplifier with the general
characteristics of very high voltage gain, very high input resistance, and very low output resistance generally
is referred to as an opamp. Most analog applications use an opamp that has some amount of negative
feedback. The Negative feedback is used to tell the opamp how much to amplify a signal. And since op-amps
are so extensively used to implement a feedback system, the required precision of the closed loop circuit
determines the open loop gain of the system.
A basic op-amp consists of 4 main blocks
a. Current Mirror
b. Differential Amplifier
c. Level shift, differential to single ended gain stage
d. Output buffer
The general structure of op-amp is as shown in given figure below:-
CURRENT MIRROR
A current mirror is a electronic circuit designed to regulate and control the current through one active
device depending on the current through another active device. It alsoneeds to keep the output current
constant irrespective of the output load. The controlling current or the current depending on the value
of which the output current is determined is often a varying signal current. Practically, an ideal current
mirror can also be considered to be an ideal current amplifier. The current mirror is used in analog
circuits to provide bias currents and active loads. A current mirror is characterized by three main
specifications. One of them is the current level it produces. The AC output resistance is the second.
The AC output resistance determines how much the output current varies with the voltage applied to
the mirror. The third specification is the minimum voltage that needs to be maintained across the
output terminal of the current mirror for it to work properly. This minimum voltage that is to be
applied across the output transistor of the mirror to keep it in active mode dictates the voltage
specification for the current mirror. This voltage range in which the mirror works is called the
compliance range and the voltage beyond which the current mirror performance is no longer
satisfactory is called the compliance voltage. A number of secondary performance issues with mirrors
temperature stability also dictates the design procedure.
The basic current mirror implemented using MOSFET transistors is as shown in Figure. In the given
figure for the proper functioning of the device we make assume that both transistors M1 and M2
operate in saturation or active region. In this circuit, there is a direct relation between IREF and IOUT,
Fig: Current mirror circuit
INTRODUCTION TO DIFFERENTIAL AMPLIFIER
The differential amplifier is an essential building block in modern IC amplifiers. Many electronic
devices use differential amplifiers internally. A differential amplifier is a type of electronic
amplifier that multiplies the difference between two inputs by some constant factor (the differential gain).
The output of an ideal differential amplifier is given by:
Vout = Ad (V + - V -) .......................................................................................................................
in in
Where Vin+ and Vin- are the input voltages and Ad is the differential gain. In ideal op-amps though the gain
is not exactly equal for the two inputs. This means, for an instance, that if Vin+ and Vin- will be equal then
the output may not be zero as it should be for the ideal case. Therefore a more practical expression for the
output of an amplifier needs to include another term
Vout = Ad(V + - V -) +inAc((V +in+ V -)/2) ................................................................
in in
Where Ac is the common mode gain of the amplifier andAd is the differential mode gain of the amplifier.
COMMON SOURCE AMPLIFIER
A single stage operational amplifier that is a differential pair allows the direct flow of the small signal current
produced by the input differential pair through the output impedance. Though the gain of such a circuit may be
improved through the use of cascading in such circuits the output swing of the op-amp is further limited due to
addition of transistor stages. Often these limitations need to be addressed as the gain and or voltage swing
The principle of operation of a common source amplifier is based on the simple fact that by virtue of its
transconductance, a MOSFET converts a variation in its gate to source voltage into a small-signal
small drain current
which can be made to pass through a resistor to generate an output voltage.
For our design we choose a PMOS common source amplifier in the second stage. The reason behind
choosing a PMOS common source amplifier is to obtain higher output swing as also more gain while at the
same time keeping the flicker noise at its minimum. PMOS amplifiers are believed to generate lesser flicker
noise than NMOS amplifiers because of the lesser mobility of holes. Let us now consider a pmos common
source amplifier:
Fig: PMOS common source amp
COMMON SOURCE STAGE WITH CURRENT SOURCE LOAD
Since the total impedance that appears in this circuit at the output node is given by
Requivalent =(ro1 || ro2)
The gain for the amplifier now becomes
Av = - gm (ro1 || ro2)
II. THEORETICAL ANALYSIS
A. MOSFET as Two Stage amplifier
For MOSFET we have several basic parameters including
And
for calculation, we have parameters kn = 170µA/V2 and kp = 36µA/V2
B. Gain, Pole and zeros
We define the input Vin, the output voltage of the first stage i.e. the input voltage of the second stage V1, and
the output voltage of the whole circuit Vout, so we can get that for two stage operational amplifier we have
so we can calculate the voltage gain of two stage separately and then combine together. We set the output
resistance of the first stage Ro2||Ro4 as R1 and the output resistance of the second stage Ro6||Ro7 as R2.
We also set the output capacitance of the first stage as C1 and C2 ≈ CL for the second stage. So we finally
get that
With
And
to find the poles and zeros, we must transform the equation into form like
here for this two stage amplifier we have the DC gain of the amplifier
the zero point of the circuit
so we could set
When it comes to the poles of the circuit, approximately we have
we can simply it to
for another pole P2 we have
C1 is very small so we can simply it into
C. Phase Margin
The gain band with GBW is equal to
For phase margin, we have
and we have
by substituting
So
Then we need
And finally
to get more than 60◦ phase margin. Thus we also have
D. Slew Rate
In our design, the slew rate is just equal to
we already have I5 = 100µA so Cc must be under 10C, with is certain to full-fill. Here we need to obtain
10MV/s slew rate under 100MHz, so we need the voltage change more than 0.05V in one pulse, which is 5ns
in width.
E. Power
The power of the op-amp can be calculated by
• DESIGN PROCEDURE
A. Design Goal
Design your opamp such that the specifications are met under a ±10% variation of the supply voltage.
TABLE I
The Design Goal of the operational amplifier
Parameters Design Goal
Process 0.18µm CMOS
VDD 1.8V
VSS 0V
Load 1pF
Phase margin ≥60◦
ADM 0 ≥1000V/V (60dB)
ACM 0 ≤0.1V/V (-20dB)
Unity gain frequency ≥ 100MHz
Slew rate ≥10V/µs
Output voltage swing (differential peak to peak) ≥800mV pp
Power Minimum
B. Design Principle
The minimum size of the MOSFET we can use is 180nm in length and 400 nm in width, but normally we
don’t use the minimum channel length due to the increase of the λ. L ≥ 2Lmin is recommended, in this design,
we use L = 1u. And after initially designed, to optimise the performance of the op-amp, we will adjust the
length of some MOSFET while keep the (W/L) unchanged.
To control the systematic offset we set
We also have
And
During the procedure of the design. we first calculate the proper value of the compensate capacitance and
resistance, then we will design the first stage, finally the second stage will be designed.
C. Parameter Optimization
1) Design of Cc: To satisfy the phase margin of 60◦ we need Cc≥0.22CL, since we have CL = 1pF so we can
use Cc≥0.22pF. To achieve slew rate 10V/us we need Cc = 10pf, to meet a balance between two requirement,
and we choose Cc = 2pf
2) Design of M1 and M2: We have
and GBW is also called unity gain frequency, which is listed in the design goal with value of 100MHZ. So
we need to apply that
and for convince we choose a litter larger value 510µ. Since
and 2ID=I₅=100µA, finally we get
so we use 20 as the final value of the ratio.
3) Design of M3 and M4: To get more than 800mV of the output range, we need to at least 800mV input
common mode voltage range before the zero point, where the gain is 1. This characteristic parameter can
also be used to determine the size of the MOSFET M1 and M2. We have
we choose ICMR(+) at 1.6V and we get
4) Design of M5 and M8: In the meanwhile, we also need to fit the proper value of ICMR(-) to determine
the size of MOSFET M5. We have
With
Approximately we can choose
5) Design of M6: And also we need
so we need we want
and
So we need
So here we get
,
6) Design of M7:
7) Design of Rz:
8) Common and differential mode gain: After initially determining the parameters of the MOSFETs, we
need to check output voltage gain, than we may need to adjust the parameters to meet the requirements of
common and differential mode voltage gain.
TABLE II
The Parameters of MOSFETs
Device Length (L) Width (W) W/L Parameter Design
M1 1u 20u 20 Cc 2pF
M2 1u 20u 20 Rc 7KΩ
M3 1u 50u 50 Idc 10uA
M4 1u 50u 50
M5 1u 39u 39
M6 180n 20u 111
M7 1u 30u 30
M8 1u 10u 10
TABLE III
The Design result
Parameter Target Achieved
ADM 0 ≥1000V/V (60dB) 70.00dB
• OUR DESIGN
After we initially determine the parameters, we use Parameter Analysis in Cadence Virtuoso to optimize our
design and final we get the design as shown in Table II, and the simulation results are in Table III. The final
design schematic is named project-final
• CONCLUSION
In this design, we have satisfied all the parameters in the requirement and specially we achieved high A dm,
slew rate and wide unity gain phase margin. By comparison we found that the simulation result is a little
different from out theoretical design due to some omitting during our calculation. But after all, our
calculation has represented the real situation and offered great help in the design of the device.
• APPENDIX
FIG 1:Design of two stage op-amp
The open loop differential mode gain
The open loop common mode gain
Transient analysis
AC analysis
DC analysis
REFERENCES
[1] T. H. Kim, “6.012 DP: CMOS Integrated Differential Amplifier”.
[2] R. Sotner, J. Jerabek, R. Prokop, V. Kledrowetz, and J. Polak, “A CMOS Multiplied Input Differential
Difference Amplifier: A New Active Device and Its Applications”.
[3] A. R. A. El-mon’m and A. W. Abdallah, “CMOS Two-Stage Amplifier Design Approach”.
[4] M. H. Hamzah, A. B. Jambek, and U. Hashim, “Design and analysis of a two-stage CMOS op-amp using
Silterra’s 0.13 um technology,” in 2014 IEEE Symposium on Computer Applications and Industrial
Electronics (ISCAIE).
[5] S. Bandyopadhyay, D. Mukherjee, and R. Chatterjee, “Design Of Two Stage CMOS Operational
Amplifier in 180nm Technology With Low Power and High CMRR”.
[6] http://en.wikipedia.org/wiki/Operational_amplifier
[7] http://www.electronics-tutorials.ws/opamp/opamp_1.html
[8] http://www.allaboutcircuits.com/vol_3/chpt_8/3.html
[9] http://www.bcae1.com/opamp.htm
[10] http://webpages.ursinus.edu/lriley/ref/circuits/node5.html for opamp amplifier circuits
[11] http://talkingelectronics.com/projects/OP-AMP/OP-AMP-1.html for calculating gain
[12] http://www.williamson-labs.com/480_opam.htm labs.com/480_opam.htm
[13] http://www.tpub.com/content/neets/14180/css/14180_117.htm
[14] http://www.ecircuitcenter.com/Circuits/opsum/opsum.htm
[15] http://www.wisc-online.com/objects/ViewObject.aspx?ID=SSE8006
[16] http://conocimientoscurrentmirrors.blogspot.com/2010_02_01_archive.html
[17] http://wn.com/differential_amplifier
