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2018
e Parallel Binary Adder
• The A and B variables represent 2 binary numbers to be
added. The C variables are the carries. The S
variables are the sum bits.
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2018
e Half Adder
• Truth Table
• Boolean Equations
• Implementation
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2018
e Full Adder
• Truth Table
• Boolean Equations
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2018
e Circuitry for a full adder
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2018
e Full Adder from Half Adders
• Truth Table
• Boolean Equations
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2018
e Adder Example
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2018
e Parallel Adder
• Uses 1 full adder per bit of the numbers
• The carry is propagated from one stage to the next
most significant stage
– takes some time to work because of the carry propagation delay
which is n times the propagation delay of one stage.
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2018
e Complete Parallel Adder With Registers
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2018
e Design a carry look-ahead adder
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Integrated Circuit Parallel Adder
2018
e
• The most common parallel adder is a 4 bit device with 4
interconnected FAs and look-ahead Carry circuits.
• Parallel adders may be cascaded together as shown to
add larger numbers
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dc Parallel adder used to add and subtract numbers
2018
e in 2’s-complement system.
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dc 2’s Complement Addition using 1’s Complement
2018
e Operands
Parallel adder used to perform subtraction (A – B) using the
2’s-complement system. The bits of the subtrahend (B) are inverted
(1’s complement), and C0 = 1 to produce the 2’s complement
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dc Parallel adder/subtractor using the
2018
e
2’s-complement system
ADD = 1, SUB = 0:
B register passes to adder
and Carry in = 0
ADD = 0, SUB = 1:
Complement of B register
passes to adder and Carry
in = 1
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2018
e ALU Integrated Circuits
• ALUs can perform
different arithmetic and
logic functions as
determined by a binary
code on the function
select inputs.
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2018 Two 74HC382 ALU chips connected as an
e
eight-bit adder
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