Embedded Wi-Fi With SiWx917

Lecture 2.1: Introduction to

Neeraj Kumar Cheryala

Vasavi College of Engineering

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SiWx917 Block Diagram

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ARM Microcontroller – A 10000 Foot View

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ARM Architectures and Processors
 Arm architecture is a family of RISC-based processor
architectures
 Well-known for its power efficiency
 Hence widely used in mobile devices, e.g., smartphones, tablets and
IoT devices
 Designed and licensed by Arm to a wide eco-system of partners
 Arm Holdings
 Arm does not manufacture, but it licenses designs to semiconductor
partners who add their own Intellectual Property (IP) on top of
Arm’s IP, which they then fabricate and sell to customers.
 Arm also offers IP other than processors, such as physical IPs,
interconnect IPs, graphics cores and development tools.

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The ARM Cortex Family

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ARM Processors vs Architectures
 Arm architecture
 Describes the details of instruction set, programmer’s model,
exception model, and memory map
 Documented in the Architecture Reference Manual
 Arm processor
 Developed using one of the Arm architectures
 Documented in processor’s Technical Reference Manual

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ARM Processor Family

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ARM Cortex M Instruction Sets

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Programmer’s Model For ARM Cortex M4
 Processor registers
 The internal registers are used to store and process temporary
data within the processor core.
 All registers are inside the processor core, hence they can be
accessed quickly
 Load-store architecture
 To process memory data, they have to be first loaded from
memory to registers, processed inside the processor core using
register data only, and then written back to memory if needed.
 Cortex-M4 registers
 Sixteen 32-bit registers (thirteen are used for general-
purpose)
 Special registers

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Cortex M4 Registers

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Cortex M4 Registers
 R0 – R12: general purpose registers
 Low registers (R0 – R7) can be accessed by
any instruction
 High registers (R8 – R12) sometimes cannot
be accessed e.g. by some Thumb (16-bit)
instructions
 R13: Stack Pointer (SP)
 Records the current address of the stack
 Used for saving the context of a program while
switching between tasks
 Cortex-M4 has two SPs: Main SP, used in
applications that require privileged access
e.g. OS kernel, and Process SP, used in
base-level application code (when not
running an exception handler)
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Cortex M4 Registers
 R14: Link Register (LR)
 The LR is used to store the return address of a subroutine or a
function call
 The program counter (PC) will load the value from LR after a
function is finished

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Cortex M4 Registers
 xPSR, combined Program Status Register
 Provides information about program execution and ALU flags
 Application PSR (APSR)
 Interrupt PSR (IPSR)
 Execution PSR (EPSR)

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Cortex M4 Registers
 1-bit PRIMASK
 If set to one, will block all the interrupts apart from non-
maskable interrupt (NMI) and the hard fault exception
 1-bit FAULTMASK
 If set to one, will block all the interrupts apart from NMI
 1-bit BASEPRI
 If set to one, will block all interrupts of the same or lower
level (only allowing for interrupts with higher priorities)
 CONTROL: special register
 1-bit stack definition
 Set to one to use the process stack pointer (PSP)
 Clear to zero to use the main stack pointer (MSP)

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Cortex M4 Registers

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The CONTROL Register

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Privilege and Modes Of Operation

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Cortex M4 Memory Map

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Cortex M4 Memory Map Example

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Cortex M4 Program Image
 The program image in Cortex-M4 contains
 Vector table
 C start-up routine
 Program code – application code and data
 C library code – program codes for C library functions

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