UNIVERSITI TEKNOLOGI MALAYSIA
SKEE3223 - MICROPROCESSOR
Module 03
Dr Afzan Othman
MODULE 3
ARM ARCHITECTURE
Dr Afzan Othman
Register Set
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Cortex M4
Register Set
• Like all RISC architecture, Cortex-M processors are load/store machine
which perform operations only on CPU registers, except LD and ST (transfer
between CPU registers and memory locations.
• These CPU registers play crucial role in data processing, instruction
execution and controlling the programs flow.
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Cortex M4
Register Set
• General purpose registers, R0-R12
o This is the main registers used for arithmetic operations, logical operations, and
storing temporary data.
o R0-R7: Called low registers and are accessible by all instructions.
o R8-R12: Called high registers and are accessible by all 32-bit instructions and NOT
accessible by Thumb (16-bit) instructions.
• Stack pointer (SP), R13
o Points to the current position in the stack, which is used for storing return addresses,
local variables, and function arguments during function calls.
o Have two stack pointers and only ONE is visible and active at given time:
o Main Stack Pointer (MSP) – used in Handler mode
o Process Stack Pointer (PSP) – use in Thread mode
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Cortex M4
Register Set
• Link register (LR), R14
o Contains the return address when returning from a function or subroutine. (BL
instruction is executed)
o When link register is not used for holding return address it can be treated as general
purpose register.
• Program counter (PC), R15
o Contains the current program or instruction address that is to be executed.
o Can be modify by the program itself to control the flow of the program.
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Cortex M4
Special Registers
• Cortex-M also contains special purpose registers, which used to provide the
current microprocessor status and to control the mode of its operation.
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Cortex M4
Special Register : Program Status Register
• Program Status Registers (PSRs) consist of three status registers:
o Application Program Status Register (APSR)
o Interrupt Program Status Register (IPSR)
o Execution Program Status Register (EPSR)
• These register have special functions and can be accessed only by special
instruction.
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Cortex M4
Special Register : Program Status Register
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Cortex M4
Special Register : Application Program Status Register
• Condition Flags:
o N (Negative): Set if the result of an operation is negative.
o Z (Zero): Set if the result of an operation is zero.
o C (Carry): Set if an operation resulted in a carry out.
o V (Overflow): Set if an operation resulted in an overflow.
o Q (Saturation): Set if the saturation has occured
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Cortex M4
Special Register : Application Program Status Register
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Cortex M4
Special Register : Control Register
• Control Registers (CONTROL) used to configure the privilege level and
perform the selection of stack pointer register.
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Cortex M4
Special Register : Interrupt Masking Register
• Three different interrupt masking registers in Cortex-M processor:
o Priority masking register (PRIMASK)
o Fault mask register (FAULTMASK)
o Base priority masking register (BASEPRI)
• These registers are useful for interrupt enabling or disabling and mask the
interrupts based on the assigned priority levels.
• Can only be accessed when the processor is operating at privileged access
level.
• On reset these registers are cleared to zero resulting in no interrupt
masking.
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Cortex M4
Special Register : Interrupt Masking Register (PRIMASK)
• PRIMASK is a 1-bit (only least significant bit is used) register.
• When it is SET, all the exceptions/interrupts are blocked except:
o Reset Interrupt,
o the Non-Maskable Interrupt (NMI), and
o the HardFault
• Setting PRIMASK to 1 is equivalent to raising the priority level to 0.
• Common usage: to disable all of the interrupts when executing a critical
code section that should not be interrupted once its execution starts
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Cortex M4
Special Register : Interrupt Masking Register (FAULTMASK)
31 1 0
• FAULTMASK is a 1-bit (only least significant bit is used) register.
• When it is SET, allow Reset and NMI but masks the Hardfault the
exceptions.
• Setting FAULTMASK to 1 is equivalent to raising the priority level to -1.
• In contrast to PRIMASK, the FAULTMASK is cleared automatically when
returning from an exception.
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Cortex M4
Special Register : Interrupt Masking Register (BASEPRI)
• The flexibility in masking the interrupts is introduced by the BASEPRI
register.
• The interrupt masking performed depending on the current priority level
configuration.
• Since the number of priority levels in ARM Cortex-M architecture can be
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between 8 and 256, it correspondingly requires 3 to 8 bits to be used by the
BASEPRI register.
Memory Map
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Cortex M4
Memory Map
• ARM defines a standardized memory address space common to all Cortex-M
cores, which ensures code portability among different silicon manufacturer.
• The address space is 4GB wide, and it is organized in several sub-regions with
different logical functionalities.
• Code Area (512MB)
o This region typically maps to Flash memory, where the main program code and
constant data are stored.
o It may also include bootloader code and interrupt vectors.
o It can be used for executing code directly from Flash memory.
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Cortex M4
Memory Map
• SRAM (512MB)
o Where variables, the stack, and
dynamic data are stored.
o Accessing data from SRAM is
generally faster than accessing it
from Flash.
• Peripheral (512MB)
o Maps to the memory-mapped
registers of the on-chip
peripherals (GPIOs, timers, ADCs,
DACs, UARTs, SPI, I2C, etc.)
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o Each peripheral is assigned a
specific address range within this
region, allowing direct access to
control and status registers.
Cortex M4
Memory Map
• External RAM (1GB)
o Reserved for external RAM, such
as SDRAM or.
o Allows to expand available RAM
beyond the on-chip SRAM.
• External Device (1GB)
o Reserved for external devices that
are memory-mapped, such as
external Flash, EEPROM, or other
specialized hardware.
o It enables the microcontroller to
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interact with external
components as if they were part
of the memory, simplifying data
access and control.
Cortex M4
Memory Map
• Private Peripheral Bus (PPB)
o Contains additional system
peripherals and debugging
components, including the
Memory Protection Unit (MPU),
the Data Watchpoint and Trace
(DWT) unit, and the
Instrumentation Trace Macrocell
(ITM).
o Provides support for advanced
debugging features and real-time
data tracing.
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Cortex M4
Memory Map
• Vendor Specific
o Reserved for vendor-specific use
and may include proprietary
peripherals, memory, or custom
functionalities provided by the
microcontroller manufacturer.
o Examples include non-volatile
memory regions, additional
SRAM, or special-purpose
peripherals.
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Cortex M4
Bit Banding
• In embedded applications, it is quite common to work with single bits of a
word using bit masking.
• Example: Set or Clear the 3rd bit (bit 2) of unsigned byte.
Compiling
C programming
Assembly language
• Such simple operation requires three assembly instructions
• This leads to two problems:
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• Waste CPU cycles
• The code will not working with concurrent execution ( another task affect the content
of memory)
Cortex M4
Bit Banding
• Bit banding – ability to map each bit of a given area of memory to a whole
word in the aliased bit-banding memory region, allowing atomic access to
such bit
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• To modify bit 2 of $2000 0000 memory, simply access $2200 0008 memory
location (bit band alias region)
Cortex M4
Bit Banding
• To compute the address of alias regions:
• Example: to modify bit 2 of $2000 0000 memory, find the bit-band alias
region.
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Cortex M4
Bit Banding
• ARM defines two bit-band regions (SRAM and Peripheral), each has 1MB
wide and mapped to 32MB bit-band alias region.
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Cortex M4
Bit Banding
• Example: Set bit 2 in a word data of address $200F FFFF
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Processor Operating Mode
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Cortex M4
Operating Mode
• ARM processor supports two modes of operation:
1. Thread mode
• The processor enters Thread mode on reset or as a result of an exception return.
• Code execution in thread mode can have either privileged or unprivileged (user) access
levels.
2. Handler mode
• The processor enters Handler mode as a result of an exception.
• All code is privileged in handler mode.
• These modes of operation have associated pair of access level:
1. Unprivileged (user) access level
• Unable to modify the contents in memory region and registers
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• Instructions to access special registers cannot be used
• Cannot change the privileged level directly by writing the control register
2. Privileged access level
• Can use all available instructions and have access to all memory regions and registers
Cortex M4
Operating Mode
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STM32 Boards
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STM32 Boards
.
Nucleo-144
Discovery board • Extended Arduino pinout
• Most comprehensive: includes LCD, • Leverages low-cost Arduino shields
microphone, audio DAC& motion sensor
• So models lack crystal so the µC runs off
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• Older design internal 8 MHz RC
• License prohibits use in commercial products • PLL can be be used to run faster
Crystal installed so it can run at max speed • Many µC versions use the same layout
STM32 Boards
.
Blue Pill
Nucleo-32 • Not made by ST
• Arduino Nano size Cheapest
Nucleo-64
• Can be plugged into
• Arduino Uno pinout • Arduino Nano size
breadboards
• Additional I/O thru Morpho • Debugger/programmer is
• Lacks crystal (except
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connectors not included
STM32Lxxx)
• Some models lack crystal • One of many third-party
STM32 boards
• Many µC versions available
Nucleo-64: F446RE
Overview
• The Nucleo board F441RE have
these 4 features to make
experimentation easier.
• ST-Link debugger
• 2 buttons and a LED
• Arduino connector for stacking
Arduino shields
• Morpho connectors – to access
all STM32 I/O pins
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Nucleo-64: F446RE
Overview
STM32F411RE MCU:
• Core: ARM Cortex-M4
• Clock Speed: Up to 100 MHz
• Flash Memory: 512 KB
• SRAM: 128 KB
• FPU and DSP: Built-in single-precision
floating-point unit and digital signal
processing (DSP) instructions for efficient
real-time operations.
• Rich Peripheral Set: Multiple GPIOs,
timers, and communication interfaces,
including UART, I2C, SPI, CAN, and USB.
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Nucleo-64: F446RE
Overview
STM32F411RE MCU:
• Core: ARM Cortex-M4
• Clock Speed: Up to 100 MHz
• Flash Memory: 512 KB
• SRAM: 128 KB
• FPU and DSP: Built-in single-precision
floating-point unit and digital signal
processing (DSP) instructions for efficient
real-time operations.
• Rich Peripheral Set: Multiple GPIOs,
timers, and communication interfaces,
including UART, I2C, SPI, CAN, and USB.
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Nucleo-64: F446RE
Arduino shields
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THANK YOU
univteknologimalaysia utm.my utmofficial
Dr Afzan Othman
