Course Title: Microcontrollers Course Code: BEC405A

SEM: IV Credits: 03 L:T:P:S = 3:0:0:x

Module – 1: Microcontroller Notes
Prepared By: Dr. G Prof. – ECE, Academic Dean
Babu N V,
MALASHREE

Syllabus:
Microcontroller:
Microprocessor Vs Microcontroller, Microcontroller & Embedded Processors, Processor Architectures-
Harvard Vs Princeton & RISC Vs CISC.
8051 Architecture- Registers, Pin diagram, I/O ports functions, Internal Memory organization. External
Memory (ROM & RAM) interfacing.
Refer: Textbook 1-1.1, Textbook 2-1.0,1.1,3.0,3.1,3.2,3.3 Textbook 3-Pg 5-9

E.1 Inside the Computer: [Additional topic for extended learning]

Fig. 1: Inside the computer

The internal working of every computer can be broken down into three parts: CPU (central processing
unit), memory, and I/O (input/ output) devices as shown in above fig.1. The function of the CPU is to
execute (process) information stored in memory. The function of I/O devices such as the keyboard and video
monitor is to provide a means of communicating with the CPU. The CPU is connected to memory and I/O
through strips of wire called a bus. The bus carries information from place to place inside a computer which
are of three types of buses: address bus, data bus, and control bus.
Data bus: Since data lines are used to carry information in and out of a CPU, the more data lines available,
the better the CPU. More data buses mean a more expensive CPU and computer. The grouping of data lines
is called data bus. The average size of data buses in CPUs varies between 8 and 64. Data buses are
bidirectional, since the CPU must use them either to receive or to send data. The processing power of a
computer is related to the size of its buses, since an 8-bit bus can send out 1 byte a time, but a 16-bit bus can
send out 2 bytes at a time, which is twice as fast.
Address bus: Since the address bus is used to identify the devices and memory connected to the CPU, the
more address buses available, the larger the number of devices that can be addressed. In other words, the
number of address lines for a CPU determines the number of locations with which it can communicate. The
number of locations is always equal to 2x where x is the number of address lines, regardless of the size of the

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data bus. The address bus is a unidirectional bus, which means that the CPU uses the address bus only to
send out addresses.
Control bus: The control buses are used to provide read or write signals to the device to indicate if the CPU
is asking for Information or sending it information.
Of the three buses, the address bus and data bus determine the capability of a given CPU.
CPU and its relation to RAM and ROM: For the CPU to process information, the data must be stored in
RAM or ROM. The function of ROM in computers is to provide information that is fixed and permanent. In
contrast, RAM is used to store information that is not permanent and can change with time. The CPU cannot
get the information directly from the disk since the disk is too slow. In other words, the CPU first seeks the
information to be processed from RAM (or ROM). Only if it is not there does the CPU seek it from a mass
storage device such as a disk, and then it transfers the information to RAM. For this reason, RAM and ROM
are sometimes referred to as primary memory and disks are called secondary memory.
Inside CPUs: A program stored in memory provides instructions to the CPU to perform an action. It is the
function of the CPU to fetch these instructions from memory and execute them. To perform the actions of
fetch and execute, all CPUs are equipped with resources such as the following:

Fig. 2: Internal Block diagram of a CPU

1. Number of registers: The CPU uses registers to store information temporarily. The information could be
two values to be processed, or the address of the value needed to be fetched from memory. Registers
inside the CPU can be 8-bit, 16-bit, 32-bit, or even 64-bit registers, depending on the CPU. In general, the
more and bigger the registers, the better the CPU. The disadvantage of more and bigger registers is the
increased cost of such a CPU
2. ALU (Arithmetic/Logic Unit): The ALU section of the CPU is responsible for performing arithmetic
functions such as add, subtract, multiply, and divide, and logic functions such as AND, OR, and NOT.
3. Program Counter (PC): The function of the program counter is to point to the address of the next
instruction to be executed. As each instruction is executed, the program counter is incremented to point to
the address of the next instruction to be executed. The contents of the program counter are placed on the
address bus to find and fetch the desired instruction. In the IBM PC, the program counter is a register
called IP, or the instruction pointer.
4. Instruction Decoder: The function of the instruction decoder is to interpret the instruction fetched into
the CPU. A CPU capable of understanding more instructions requires more transistors to design.

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1.1 Microcontrollers and Embedded Processors:

1.1.1 Microcontroller versus general- purpose microprocessor:

Fig. 3: GPP Vs Microcontroller

Table-1: GPP Vs Microcontroller

S.# General purpose processors (GPP) Microcontrollers (MC)
Has a CPU (a microprocessor) in addition to a
Do not contain RAM, ROM, and I/O ports on the
1. fixed amount of RAM, ROM, I/O ports,
chip itself.
and a timer all (peripherals) on a single chip.
A system designer using a general-purpose Designer need not add any external memory, I/O,
2. microprocessor must add RAM, ROM, I/O ports, or timer to it. ADC and many other peripherals are
and timers externally to make them functional. integrated inside.
Addition of external RAM, ROM, and I/O ports
Since memory & peripherals are integrated on
3. makes these systems bulkier and much more
chip, systems are smaller and cheaper.
expensive.
The fixed amount of on-chip ROM, RAM, and
GPP have the advantage of versatility such that the
number of I/O ports in microcontrollers makes
4. designer can decide on the amount of RAM, ROM,
them ideal for many applications in which cost,
and I/O ports needed to fit the task at hand.
and space are critical.
GPP has many instructions to move data between MC has less instructions to move data between
5.
external memory and CPU. memory and CPU.
6. GPP has less bit handling instructions MC has more bit handling instructions.
Less access time for built in memory & I/O
7. Access time for memory & I/O devices are more.
devices.

MC based system requires less hardware, reducing

8. GPP system requires more hardware.
the PCB size, thereby increasing the reliability.

9. GPP are more flexible in design point of view. MC are less flexible in design point of view.
10. GPP has single memory map for data & code MC has separate memory map for data & code.
11. GPP has less number of multifunctional pins. MC has more number of multifunctional pins.
Intel’s x86 family (8086, 80286, 80386, 80486, and
8051 family, PIC 16F8X, Hitachi H8, 68HC11xx,
12. the Pentium) or Motorola’s 680×0 family (68000,
etc.
68010, 68020, 68030, 68040, etc.)

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1.1.2 Microcontrollers for embedded systems:
An embedded product uses a microprocessor (or microcontroller) to do one task and one task
only. In an embedded system, there is only one application software that is typically burned into ROM.
Ex: A printer is an example of embedded system since the processor inside it performs only one task;
namely, getting the data and printing it.
In Contrast, a Personal Computer can be used for any number of applications such as word
processor, print server, bank teller terminal, video game player, network server, or internet terminal.
The reason a PC can perform myriad tasks is that it has RAM memory and an operating system that
loads the application software into RAM and lets the CPU run it.
An x86 PC contains or is connected to various embedded products such as the keyboard, printer,
modem, disk controller, sound card, CD-ROM drive, mouse, and so on. Each one of these peripherals
has a microcontroller inside it that performs only one task. For example, inside every mouse there is a
microcontroller that performs the task of finding the mouse position and sending it to the Pc. Table-2
below lists some embedded products.
One of the most critical needs of an embedded system is to decrease power consumption and
space. This can be achieved by integrating more functions into the CPU chip.

Table-2: Some Embedded Products using Microcontrollers

Home Office Auto
Appliances Telephones Trip computer
Intercom, Telephones, Fax machines,
Computers Engine control
Paging, Cellular phones
Camera, Camcorder Security systems Air bag
Security systems Fax machine ABS
Lighting control, Garage door openers Microwave Instrumentation
Answering machines Copier Security system
Home computers Laser printer Transmission control
TVs, Cable TV tuner, VCR, Video games Color printer Entertainment
Exercise equipment Paging Climate control
Remote controls, Toys Cellular phone
Musical instruments Keyless entry

Choosing a microcontroller:
Three criteria in choosing microcontrollers are as follows:
1) Meeting the computing needs of the task at hand efficiently and cost effectively:
a) Data handling size: an 8-bit, 16-bit, or 32-bit microcontroller can best handle the computing
needs of the task most effectively
b) Speed: highest speed that the microcontroller supports?
c) Packaging: Does it come in a 40-pin DIP (dual inline package) or a QFP (quad flat package), or
some other packaging format? This is important in terms of space, assembling, and prototyping
the end product.

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 d) Power consumption: This is especially critical for battery-powered products.
e) Memory: The amount of RAM and ROM on chip.
f) Peripheral needed: The number of I/O pins and the timer on the chip.
g) How easy it is to upgrade to higher-performance or lower power-consumption versions.
h) Cost per unit. This is important in terms of the final cost of the product in which a
microcontroller is used. For example, there are microcontrollers that cost 50 cents per unit when
purchased 100,000 units at a time.
2) Availability of software development tools such as compilers, assemblers, and debuggers:
Key considerations include the availability of an assembler, debugger, a code-efficient C
language compiler, emulator, technical support, and both in-house and outside expertise. In many
cases, third-party vendor (that is, a supplier other than the chip manufacturer) support for the chip
is as good as, if not better than, support from the chip manufacturer.
3) Wide availability and reliable sources of the microcontroller:
Ready availability in needed quantities both now and in the future. The 8051 family has the
largest number of diversified (multiple source) suppliers. By supplier is meant a producer besides
the originator of the microcontroller. In the case of the 8051, which was originated by Intel,
several companies also currently produce (or have produced in the past) the 8051. These
companies include: Intel, Atmel, Philips/Signetics, AMD, Infineon (formerly Siemens), Matra, and
Dallas Semiconductor.

1.1.3 Processor Architectures:

1) Princeton (Von Neumann) Vs Harvard:
i) Princeton (Von Neumann) architecture:
This architecture uses same memory space for both program and data.

Fig 4: Representing Princeton architecture

• The code storage is not optimal and requires multiple fetches to form the instruction.
• Program and data fetches are done using TDM which affects the performance.
• Ex: Motorola 68HC11, 8086, etc.

ii) Harvard architecture:

• This architecture uses separate memory space for program and data with their independent
address and data buses.
• Because of two different streams of data and address lines there is no need to have TDM of
address and data buses.
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 • Instructions can be prefetched and decoded while multiple data are being fetched and
operated on.
• Data bus may have different size than the address bus. This allows the optional bus widths of
data and addresses for fast execution of instructions.
• Ex.: MCS-51, DSPs, etc.

Fig 5: Representing Harvard architecture

2) RISC Vs CISC:

Table-3: RISC Vs CISC

Reduced Instruction Set Computer Complex Instruction Set Computer
S.#
(RISC) (CISC)
1. Less number of complex instructions More number of complex instructions

2. Instructions are executed in single cycles Instructions are executed in multiple cycles
3. Low hardware complexity High hardware complexity
4. Hardware based decoder and control unit Microprogrammed decoder and control unit
Instructions are of variable length &
5. Instructions are of fixed length & format
different format
6. Program consists of large code size Program consists of small code size.
Pipelining: different parts of an instruction Execution time for each instruction may be
7.
are executed simultaneously different.
8. Less number of addressing modes More number of addressing modes
CISC approach attempts to minimize the RISC approach to reduce the cycles per
9. no. of instructions per program sacrificing instruction at the cost of the number of
the no. of cycles per instruction. instructions per program.

10. Ex.: ARM (advanced RISC), etc. Ex.: Z80, 68000, 80286, 80386, etc.

1.2 8051 Architecture:

The below fig. 6 shows the architecture of classic 8051 microcontroller

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 Fig.6: Block diagram of 8051

Features of 8051:
1) An 8-bit ALU with A & B Registers, 8-bit PSW.
2) 16-bit address and 8-bit data bus.
3) 16-bit Program Counter (PC) & 16-bit Data Pointer (DPTR).
4) 8-bit Stack Pointer (SP), initial default value is 07h.
5) SFR: TCON, TMOD, SCON, PCON, SBUF, IP & IE, etc.
6) Two 16-bit timers/counters: T0 & T1
7) Two external interrupts INT0 & INT1 and three internal interrupts TO, T1 & SI.
8) Full duplex UART Serial interface.
9) 32 I/O pins arranged as 04 8-bit ports: P0 - P3.
10) Special bit manipulation instructions.
11) Internal ROM of 4 KB, 8751 - EPROM; 8951 - EEPROM 8031 – 0 bytes. Extendable up to 64 KB.
12) Internal RAM of 128 bytes, Extendable up to 64KB.
✓ Four register banks, each containing 8 registers (32 bytes)
✓ 16 bytes bit addressable memory
✓ 80 bytes of general-purpose data memory
13) Harvard memory architecture. The program memory and data memory have separate address spaces from
0000h and separate control signals.
14) CISC (Complex Instruction Set Computer) architecture.

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 15) Internal clock and oscillator circuit.
Classic version has no DAC, modem, watchdog timer, ADC, floating-point processor, cache, memory
management unit, DMA, pipelining.

8051 Block diagram explanation:

Arithmetic & Logic Unit (ALU):
The 8-bit ALU can perform arithmetic operations like addition, subtraction, multiplication & division and
logical operations like OR, AND, XOR, etc.
A & B CPU registers:
‘A’ & ‘B’ registers hold the results of many instructions, particularly math & logical operations.
‘A’ register called as accumulator is the most versatile of the two CPU registers & is used for many
operations, including addition, subtraction, integer multiplication and division, and Boolean bit
manipulations.
‘A’ register is also used for all data transfers between 8051 and the external memory.
‘B’ register is used with the ‘A’ register for multiplication and division operations and has no other function
other than as a location where data may be stored.
PSW and Flag bits:
The 8051 has a flag register to indicate arithmetic conditions such as the carry bit. The flag register in
the 8051 is called the program status word (PSW) register. The program status word (PSW) register is an 8-bit
register also referred to as the flag register. Although the PSW register is 8 bits wide, only 6 bits of it are
used by the 8051. The two unused bits are user-definable flags. Four of the flags are called conditional flags,
meaning that they indicate some conditions that result after an Instruction is executed, these four are CY
(carry), AC (auxiliary carry), P (parity), and OV (overflow).

CY AC F0 RS1 RS0 OV -- P

Carry flag; Sets or resets based on carry/borrow generated

CY PSW.7
during arithmetic or logical operations.
Auxiliary carry flag; sets or resets based on carry/borrow
AC PSW.6
generated b/w lower & higher nibble of a byte.
F0 PSW.5 Available to the user for general purpose.
RS1 PSW.4 Register Bank selector bit1.
RS0 PSW.3 Register Bank selector bit 0.
RS1 RS0 Register Bank Address
0 0 0 00H -07H
0 1 1 08H-0FH
1 0 2 10H – 17H
1 1 3 18H-1FH
OV PSW.2 Overflow flag.
-- PSW.1 User-definable bit.
Parity flag. Set/cleared by hardware on each instruction
P PSW.0 cycle to indicate an odd/even number of 1 bits in the
accumulator. 1 – Odd parity, 0 – Even parity

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 CY, the carry flag: This flag is set whenever there is a carry out from the D7 bit. This flag bit is
affected after an 8-bit addition or subtraction. It can also be set to 1 or 0 directly by an instruction such
as "SETB c" and "CLR C" where "SETB" stands for "set bit carry" and "CLR C" for "clear carry".
AC, the auxiliary carry flag: If there is a carry from D3 to D4 during an ADD or SUB operation, this
bit is set; otherwise, it is cleared. This flag is used by instructions that perform BCD (binary coded
decimal) arithmetic.
P, the parity flag: The parity flag reflects the number of 1s in the A (accumulator) register only. If the
A register contains an odd number of 1s, then P = 1. Therefore, P = 0 if A has an even number of 1s.
OV, the overflow flag: This flag is set whenever the result of a signed number operation is too large,
causing the high-order bit to overflow into the sign bit. In general, the carry flag is used to detect errors
in unsigned arithmetic operations. The overflow flag is only used to detect errors in signed arithmetic.
Program Counter (PC):
Program counter is a 16-bit register which addresses the instruction bytes that are to be fetched from
locations in program memory.
Program ROM may be on the chip at addresses 0000h to 0FFFh, external to the chip for addresses that
exceed 0FFFh, or totally external for all addresses from 0000h to FFFFh.
The PC is automatically incremented after every instruction byte is fetched and may also be altered by
certain instructions. The PC is the only register that doesn’t have an internal address.
Data Pointer (DPTR):
The data pointer (DPTR) is a 16-bit register made up of two 8-bit registers, named DPH & DPL, which are
used to furnish memory addresses for internal & external code access & data access.
The DPTR is under the control of program instructions and can be specified by its 16-bit name DPTR or by
each individual byte name DPH & DPL.
DPTR doesn’t have a single internal address; DPH & DPL are each assigned an address.

8051 oscillator and clock:

The heart of the 8051 is the circuitry that generates the clock pulses by which all internal operations are
synchronized. Pins XTAL1 & XTAL2 are provided for connecting a resonant network to form an oscillator.
Typically, a quartz crystal and capacitors are employed, as shown in fig. 7. The crystal frequency is the basic
internal clock frequency of the microcontroller. 8051 operates typically between 1 MHz to 16 MHz.
Serial data communication needs often dictate the frequency of the oscillator because of the requirement that
internal counters must divide the basic clock rate to yield standard communication bit per second (baud
rates). If the basic clock frequency is not divisible without a remainder, then the resulting communication
frequency is not standard.
The oscillator formed by the crystal, capacitors, and an on-chip inverter generates a pulse train at the
frequency of the crystal, as shown in fig.7. The clock frequency, f, establishes the smallest interval of time
within the microcontroller, called the pulse, P, time. The smallest interval of time to accomplish any simple
instruction, or part of a complex instruction is the machine cycle. The machine cycle is made up of six states.
Two oscillator pulses define each state. A state is the basic time interval for discrete operations of the

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microcontroller such as fetching an opcode byte, decoding an opcode, executing an opcode, or writing a data
byte.
Program instructions may require one, two, or four machine cycles to be executed, depending on the type of
instruction. Instructions are fetched and executed by the microcontroller automatically, beginning with the
instruction located at ROM memory address 0000h at the time the microcontroller is first reset.
Ex.: A 12 MHz crystal yields the convenient time of 1 µs per cycle. An 11.0592 MHz crystal yields a cycle
frequency of 921.6 KHz, which can be divided evenly by the standard communication baud rates of 19200,
9600, 4800, 2400, 1200 and 300.

Fig.7 Oscillator circuit and timing

There are two ALE pulses per machine cycle. The ALE pulse, which is primarily used as a timing pulse for
external memory access, indicates when every instruction byte is fetched. Two bytes of a single instruction
may thus be fetched, and executed, in one machine cycle. Single-byte instructions are not executed in a half
cycle, however, single-byte instructions “throw-away” the second byte (which is the first byte of the next
instruction). The next instruction is then fetched in the following cycle.
To calculate the time any particular instruction will take to be executed, find the number of cycles, C. The
time to execute that instruction is then found by multiplying C by 12 and dividing the product by the crystal
frequency:
𝐶 𝑥 12𝑑
Tinst =
𝑐𝑟𝑦𝑠𝑡𝑎𝑙 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦

1.2.1 Internal Memory Organization of 8051:

1) Internal ROM of 4K bytes for code or program.
2) Internal RAM of 128 bytes for data and Special Function Registers (SFR) area of 128 bytes of
RAM.
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 Fig. 8: Internal memory organization of 8051
1) Internal ROM:
The 8051 has 4K bytes of internal ROM, having the address space 0000h to 0FFFh. Program code address
higher than 0FFFh, which exceed the internal ROM capacity, will cause the 8051 to automatically fetch
code bytes from external program memory.
Code bytes can also be fetched exclusively from an external memory addresses 0000h to FFFFh by
connecting the external access pin (EA – pin 31) to ground.

2) Internal RAM Organization:

RAM memory space allocation in the 8051:
The 128 bytes of RAM inside the 8051 are assigned addresses 00 to 7FH. These 128 bytes are divided
into three different groups as follows. Fig 9 depicts the Internal RAM organization of 8051.
1. A total of 32 bytes from locations 00h to 1Fh are set aside for register banks and the stack.
2. A total of 16 bytes from locations 20h to 2Fh are set aside for bit-addressable read/write memory.
3. A total of 80 bytes from locations 30h to 7Fh are used for read and write storage, or what is normally
called a scratch pad. These 80 locations of RAM are widely used for the purpose of storing data and
parameters by 8051 programmers.

1. Register banks in the 8051:

➢ First 32-bytes from address 00h to 1Fh that make up 32 working registers organized as four banks of
eight registers each numbered 0 to 3 and registers in each are named as R0 to R7.
➢ The default register bank on reset will be Bank 0.
➢ Each register can be addressed by name (when its bank is selected) or by its RAM address. Ex: R0
of bank 3 is R0 if bank 3 is selected or address 18h, whether bank 3 is selected or not.
➢ At a time only one register bank can be selected, and it can be done through register bank select bits
RS0 & RS1 in PSW. Switching of register banks from one to other can be done through RS0 &
RS1.

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 Fig. 9: Internal RAM organization
2. Bit-addressable read/write memory:
A bit addressable area of 16 bytes occupies RAM byte address 20h to 2Fh, forming a total of 128
addressable bits. An addressable bit may be specified by its address of 00h to 7Fh or 8-bits may form
any byte address from 20h to 2Fh. Addressable bits are useful when the program need only remember
a binary event (ON, OFF, etc.)
3. General purpose area or scratch pad area:
A byte-addressable area from 30h to 7Fh is used as general-purpose RAM for data storage.

Stack in the 8051:

The stack is a section of RAM used by the CPU to store information temporarily. This information could be
data or address. The CPU needs this storage area since there are only a limited number of registers.
How stacks are accessed in the 8051:
➢ Stack in 8051 is accessed by using 8-bit pointer register called Stack Pointer (SP) and the operations
PUSH & POP.
➢ When the 8051 is powered up, the SP register contains value 07.
➢ The Storing of a CPU register in the stack is called a PUSH operation.
➢ The Pulling the contents off the stack back into a CPU register is called a POP.
Pushing onto the stack:
In the 8051 the stack pointer (SP) points to the last used location of the stack. As we push data onto the
stack, the stack pointer (SP) is incremented by one. For every PUSH operation, the SP is incremented by 1

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and then contents of the register are saved on the stack and. To PUSH the registers onto the stack we must
use their RAM addresses.
Popping from the stack:
Popping the contents of the stack back into a given register is the opposite process of pushing. With
every pop, the top byte of the stack is copied to the register specified by the instruction and the stack pointer
is decremented once.
The upper limit of the stack:
➢ Locations 08h to 1Fh and 30h to 7Fh in the 8051 RAM can be used for the stack.
➢ Locations 20h-2Fh of RAM are reserved for bit-addressable memory and must not be used by the stack.
➢ Stack location can be changed to a desired location by changing the address in stack pointer (SP).

Fig 10: Stack Operation

Special Function Registers (SFR) and their addresses:

Table-4: 8051 Special function register (SFR) Addresses
Symbol Name Address
ACC* Accumulator 0E0H
B* B register 0F0H
PSW* Program status word 0D0H
SP Stack pointer 81H
DPTR Data pointer 2 bytes
DPL Low byte 82H
DPH High byte 83H
P0* Port 0 80H
P1* Port 1 90H
P2* Port 2 0A0H
P3* Port 3 0B0H·
IP* Interrupt priority control 0B8H
IE* Interrupt enable control 0A8H
TMOD Timer/counter mode control 89H
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 TCON* Timer /counter control 88H
TH0 Timer /counter 0 high byte 8CH
TL0 Timer/counter 0 low byte 8AH
TH1 Timer/counter 1 high byte 8DH
TL1 Timer/counter 1 low byte 8BH
SCON* Serial control 98H
SBUF Serial data buffer 99H
PCON Power control 87H

There are many special function registers and they are widely used. The SFR can be accessed by their
names (which is much easier) or by their addresses.
Table-4 lists the 8051 special function registers (SFR) and their addresses. The following two points should
be noted about the SFR addresses. Fig 10 represents the SFRs as programming model.
1. The special function registers have addresses between 80h and FFh.
2. Not all the address space of 80h to FFh is used by the SFR. The unused locations 80h to FFh are reserved
and must not be used by the,8051 programmer.

Fig. 11: Programming model of 8051

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1.3 Pin Diagram of 8051 microcontroller:

Fig. 11: Pin diagram of 8051

Table-5: 8051 pins & its functions
Pin nos. Pin names Function
Pin 1 to 8 Port 1 (P1.0 to P1.7) It has 8 bidirectional I/O lines used only for I/O purpose.
Pin 9 RST Reset I/P, +5V applied across this pin causes the microcontroller to restart.
Pin 10 to pin Port 3 (P3.0 to P3.7) Port 3 is multifunctional. It is used as I/O and other function for individual
17 port pin.
Pin 10 (P3.0) RxD Acts as serial data receiver
Pin 11 (P3.1) TxD Used as serial data transmitting
Pin 12 (P3.2) /INT0 External interrupt 0
Pin 13 (P3.3) /INT1 External interrupt 1
Pin 14 (P3.4) T0 Clock input for Timer 0
Pin 15 (P3.5) T1 Clock input for Timer 1
Pin 16 (P3.6) /WR Write signal for external RAM
Pin 17 (P3.7) /RD Read signal for external RAM
Pin 18 & 19 XTAL2 & XTAL1 Clock input pins to connect internal oscillator circuit
Pin 20 GND (Vss)
Pin 21 to 28 Port 2 (P2.0 to P2.7) Port2 is multifuncitonal. It can be used as I/O as well as higher order
[A8 to A15] address lines (A8 – A15) for external memory if connected to 8051
Pin 29 PSEN Program store enable pin is used in conjunction with EA pin to read
external ROM if connected
Pin 30 ALE/PROG Address Latch Enable signal is used to demultiplex address & data during
external memory access. Other function is EPROM programming pulse
during program code burning into ROM
Pin 31 EA/Vpp – External External access pin is used to access exernal memory if connected, if not
Access/EPROM connected it is connected to Vpp. EA is made high for external memory
programming voltage. access
Pin 32 to 39 Port 0 / Address/data Multifunctional pins can be used as I/O or address/data multiplexed lines if
(P0.0 to P0.7 /AD0 to exernal memory is connected. Multiplexed lower address lines & data
AD7) lines can be demultiplexed using ALE signal
Power supply of +5V
Pin 40 Vcc

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1.4 IO ports fucntions:
I/0 port pins and their functions:
The four ports P0, P1, P2, and P3 each has 8 pins, making them 8-bit ports. All the ports upon RESET are
configured as output, ready to be used as output ports. To use any of these ports as an input port, it must be
programmed. To configure as an input, a 1 must be sent to the port.
i) Port 0:
Port 0 occupies a total of 8 pins (pins 32 - 39). It can be used for input or output. To use the pins of port 0 as
both input and output ports, each pin must be connected externally to a 10K-ohm pull-up resistor. This is due
to the fact that P0 is an open drain, unlike P1, P2, and P3.

Fig. 12: Port 0 with pull –up resistors

Ports 0 as input: With resistors connected to port 0, in order to make it an input, the port must be
programmed by writing 1 to all the bits.
Dual role of port 0: Port 0 is also designated as AD0 - AD7, allowing it to be used for both address and
data. When connecting an 8051/31 to an external memory, port 0 provides both address and data. The 8051
multiplexes address and data through port 0 to save pins.
ii) Port 1:
Port 1 occupies a total of 8 pins (pins 1 to 8). It can be used as input or output. In contrast to port 0, this port
does not need any pull-up resistors since it already has pull-up resistors internally. Upon reset, port 1 is
configured as an input port.
Port 1 as input: If port 1 has been configured as an output port, to make it an input port, it must be
programmed by writing 1 to all its bits.
iii) Port 2:
Port 2 occupies a total of 8 pins (pins 21 to 28). It can be used as input or output. Just like P1, port 2 does not
need any pull-up resistors since it already has pull-up resistors internally. On reset, port 2 is configured as an
input port.
Port 2 as input: To make port 2 an input, it must be programmed by writing 1 to all its bits.
Dual role of port 2: Port 2 is also designated as A8 - A15, indicating its dual function. When the 8051 is
connected to external memory, P2 is used for the upper 8 bits of the 16-bit address, and it cannot be used for
I/O.

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iv) Port 3:
Port 3 occupies a total of 8 pins, pins 10 through 17. It can be used as input or output. P3 does not need any
pull- up resistors, just as P1 and P2 did not. Port 3 has the additional function of providing some extremely
important signals such as interrupts. Table-6 provides these alternate functions of P3.

Table-6: Port 3 Alternate Function

P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INTO 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17

1.5 External Memory (ROM & RAM) Interfacing:

Fig. 13: Data, Address, and Control buses for the 8031/51
EA pin:
➢ The EA pin is connected to Vcc to indicate that the program code is stored in the microcontroller's on-chip
ROM.
➢ To indicate that the program code is stored in external ROM, this pin must be connected to GND.
P0 and P2 role in providing addresses:
➢ In the 8031/51, port 0 and port 2 provide the 16-bit address to access external memory.
➢ P0 provides the lower 8-bit addresses A0- A7, and P2 provides the upper 8-bit addresses A8 - A15.
➢ P0 is used for both the address and data paths. This is called address/ data multiplexing in chip design.
➢ The ALE signal is used to demultiplex the P0 into data path and address path. when ALE = 0 the 8031
uses P0 for the data path, and when ALE = 1, it uses it for the address path.
➢ To extract the addresses from the P0 pins, 74LS373 latch is used and the connection of P0 is as shown in
fig. 13.
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PSEN:
➢ PSEN is an output signal for the 8031/51 microcontroller uses to access external ROM containing
program code and must be connected to the OE pin of a ROM containing the program code.
➢ The role of EA and PSEN is significant when connecting the 8031/51 to external ROM.
✓ When the EA pin is connected to GND, the 8031/51 fetches opcode from external ROM by using
PSEN.
✓ When EA is connected to VCC, these chips do not activate the PSEN pin. This indicates that the on-
chip ROM contains program code.
Ex.:
Fig.14 shows the connections between an 8031 and an external memory configuration consisting of 16K of
EPROM and 8K of static RAM. The 8051 accesses external RAM whenever certain program instructions are
executed. External ROM is accessed whenever the /EA is connected to ground or when the PC contains an
address higher than the last address in the internal 4K ROM (0FFFh). 8051 designs can thus use internal and
external ROM automatically; the 8031, having no internal ROM, must have /EA grounded.

Fig.14: External memory connections

Fig.15 shows the timing associated with an external memory access cycle. During any memory access cycle,
port 0 is time multiplexed. That is, it provides the lower byte of the 16-bit memory address, then acts as bi-
directional data bus to write or read a byte of memory data. Port 2 proivdes the high byte of the memory
address during the entire memory read/write cycle.

The lower address byte from port 0 must be latched into an external register to save the byte. Address byte
save is accompished by the ALE clock pulse that provides the correct timing for the ‘373 type data latch. The
port 0 pins then become free to serve as a data bus.

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 Fig.15: External memory timing

If the memory access is for a byte of program code in the ROM, the /PSEN pin will go low to enable the
ROM to place a byte of program code on the data bus. If the access is for a RAM byte, the /WR (write) or
/RD (read) pins will go low, enabling data to flow between the RAM and the data bus.

Note that the /WR & /RD signals are alternate uses for port 3 pins 16 and 17. Also, port 0 is used for the
lower address byte and data; port 2 is used for upper address bits. The use of external memory consumes
many of the port pins, leaving only port 1 and parts of port 3 for general I/O.

E.2 Memory & interfacing: [Additional topic for extended learning]

Memory address decoding:

In addition to the internal memory of 4 Kbytes of ROM and 256 bytes of RAM, 64 Kbytes of ROM & 64
Kbytes of RAM can be interfaced to 8051 using Port 0 (AD0 – AD7), Port 2 (A8 – A15), P3.6 (/WR), P3.7
(/RD), /PSEN, ALE& EA pins.
Memory chips have one or more pins called CS (Chip Select), which must be activated for the memory’s
contents to be accessed. Sometimes the chip select is also referred to as chip enable (CE). As shown in fig.
16, connecting a memory chip to the CPU:

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 Fig.16: CPU connecting to memory chip

1. The data bus of the CPU is connected directly to the data pins of the memory chip.
2. Control signals RD (read) & WR (write) from the CPU are connected to the OE (output enable) & WE
(write enable) pins of the memory chip respectively.
3. The address bus of CPU is connected to address lines of the memory chip and also used to decode the
memory chip selection through CS pin of memory chip.

Chip select of a memory chip is normally active low and is activated by the output of the memory decoder.
Normally memories are divided into blocks, and the output of the decoder selects a given memory block.
There are three ways to generate a memory block selector:

1) Using simple logic gates

2) Using the 74LS138
3) Using programmable logics

1) Simple logic gate address decoder

The simplest method of constructing decoding circuitry is the use of a NAND gate. The output of a NAND gate is
active low, and the CS pin is also active low, which makes them a perfect match. In cases where the CS input is active
high, an AND gate must be used. Using combination of NAND gates & inverters, address range can be decoded. In the
pictorial example below fig. 11, A15 – A12 must be 0011 in order to select the chip resulting in the assignment of the
addresses 3000h to 3FFFh to this chip.

Fig. 17: Logic gate as decoder

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2) Using the 74LS138 3-8 decoder
This is one of the most widely used address decoders. The 3 inputs A, B, & C generate 8 active-low outputs
Y0-Y7 as shown in fig. 12. Each Y output is connected to CS of a memory chip, allowing control of 8 memory blocks
by a single 74LS138. In the 74LS138, where A, B & C select which output is activated, there are three additional
inputs, G2A, G2B, and G1. G2A & G2B are both active low, and G1 is active high. If any one of the inputs G1, G2A,
or G2B is not connected to an address signal, they must be activated permanently either by Vcc or ground, depending
on the activation level. Fig. 13 shows the connections to a decoder.

Fig. 18: 74LS138 decoder

3) Using programmable logic as an address decoder:

Other widely used decoders are programmbale logic chips such as PAL (Programmable Array Logic) &
GAL (Generic Array Logic) chips. One disadvantage of these chips is that they require PAL/GAL software
and a burner (programmer), whereas 74LS138 needs neither of these. The advantage of these chips is that
they can be programmed for any combination of address ranges, and so are much more versatile. PALs &
GALs have 10 or more inputs in contrast to 6 in 74LS138.

Fig. 19: 74LS138 as decoder

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On- chip and off-chip code ROM:
Both on-chip and off-chip ROM can be accessed at a time. When EA = Vcc, the 8051 executes the on-chip program
first; then, when it reaches the end of the on-chip ROM (0FFF) it switches to external ROM for the rest of the program
code automatically.

Fig. 20: on-chip and off-chip Program code access

Ex:
Discuss the program ROM space allocation for each of the following cases
(a) EA = 0 for the 8751 (89C51) chip.
(b) EA = Vcc with both on-chip and off-chip ROM for the 8751.
(c) EA = Vcc with both on-chip and off-chip ROM for the 8752.

Solution:
(a) When EA = 0, the EA pin is strapped to GND, and all program fetches are directed to external memory
regardless of whether or not the 8751 has some on-chip ROM for program code. This external ROM can be as
high as 64K bytes with address space of 0000 - FFFFH. In this case an 8751 (89C51) is the same as the
8031system.
(b) With the 8751 (89C51) system where EA = Vcc the microcontroller fetches the program code of addresses 0000 -
0FFFH from on-chip ROM since it has 4K bytes of on-chip program ROM and any fetches from addresses
1000H - FFFFH are directed to external ROM.
(c) With the 8752 (89C52) system where EA = V cc- themicrocontroller fetches the program code of addresses
0000 - 1FFFH from on-chip ROM since it has 8K bytes of on-chip program ROM and any, fetches from
addresses 2000H - FFFFH are directed to external ROM.
Ex:
Discuss the role of the PSEN pin in accessing on-chip and off-chip program codes.
Solution:
In the process of fetching the internal on-chip program code the PSEN pin is not used and is never activated.
However, PSEN is used for all external program fetches.
External ROM for data:
➢ To connect the 8031/51 to external ROM containing data, we use RD (pin P3.7).
➢ PSEN and RD signals play an important role in accessing ROM for code & data respectively. For the ROM
containing the program code, PSEN is used to fetch the code. For the ROM containing data, the RD signal is used
to fetch the data.
➢ MOVC instruction is used to access the data from ROM along with PC or DPTR.

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8051 Data memory space:
➢ In addition to its code space, the 8051 family also has 64K bytes of data memory space.
➢ The data memory space is accessed using the DPTR register and an instruction called MOVX, where X stands for
external (meaning that the memory space must be implemented externally).
External memory interfacing example:

Fig. 21: 8031 connection to External Program ROM, Data RAM, and Data ROM

Table 7: Memory address decoding

A15 A14( Address
Memory (B) A)
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
space

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h
16K Data
ROM ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFh
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000h
16K Data
RAM ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BFFFh
16K x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h
Program ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
ROM x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFh

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Review Questions for module – 1:

1. How many bytes is 24 kilobytes?

2. What does “RAM” & “ROM” stand for? How is it used in computer systems?
3. Why is RAM called volatile memory?
4. List the three major components of a computer system.
5. What does “CPU” stand for? Explain its function in a computer.
6. List the three types of buses found in computer systems and state briefly the purpose of each type of bus.
7. State which of the following is unidirectional and which is bidirectional. (a) Data bus (b) address bus.
8. If an address bus for a given computer has 16 lines, what is the maximum amount of memory it can access?
9. What does “ALU” stand for? What is its purpose?
10. How are registers used in computer systems?
11. What is the purpose of the program counter?
12. What is the purpose of the instruction decoder?
13. True or false. Microcontrollers are normally less expensive than microprocessors.
14. When comparing a system board based on a microcontroller and a general-purpose microprocessor, which one is
cheaper?
15. A microcontroller normally has which of the following devices on-chip?
(a) RAM (b) ROM (c) I/O (d) all of the above
16. A general-purpose microprocessor normally needs which of the following devices to be attached
(a) RAM (b) ROM . (c) I/O (d) all of the above
17. An embedded system is also called a dedicated system. Why?
18. What does the term embedded system mean?
19. True or false. DPTR is a 16-bit register that is also accessible in low-byte and high-byte formats.
20. Is the PC (program counter) also available in low-byte and high-byte formats?
21. What address is assigned to register R2 of bank 2?
22. What address is assigned to register A?
23. If EA = GND, indicate from what source the program code is fetched.
24. If EA = = Vcc, indicate from what source the program code is fetched.
25. Which port of the 8051 is used for address/ data multiplexing?
26. Which port of the 8051 provides D0 - D7?
27. Which port of the 8051 provides A0 - A7?
28. Which port of the 8051 provides A8 - A15?
29. True or false. In accessing externally stored program code, the PSEN signal is always activated.

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