COMPUTER

ORGANIZATION AND ARCHITECTURE

Execution Unit

Dr. Bore Gowda S B

Additional Professor
Dept. of ECE
MIT, Manipal
 Introduction
❑ A typical CPU model
• A typical CPU model is shown in figure
• A conventional CPU consists of the
following:
✓ General purpose registers
✓ Dedicated registers
✓ An ALU
✓ Dedicated hardware or firmware elements
that perform a special operations such as
multiplication or division
✓ A control unit

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 2

 Register Section
• CPU with many register reduces the number of memory access
• General purpose register: may be configured as an accumulator, address pointer or a data
pointer
• Dedicated register: used for some specific tasks

• Commonly known special purpose registers and their tasks rre:

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 3

 General Register Design
❑ Typical shift operations:
• GPR is to store address or data, then to be able to retrieve the data when needed
• GPR is also capable of manipulating the stored data by shift left or shift right operation
• Logical shift operations
• Arithmetic shift operations

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 4

 General Register Design
❑ Basic cell for designing GPR
• The hypothetical instruction set of a computer consists of eight instructions, I0, I1, I2,,,,,,I7. The
relative frequency of these instructions are as follows:

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 5

 General Register Design
❑ 4-bit GPR:
• Parallel load, shift left, shift right, serial loading of data

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 6

 General Register Design
❑ 4x4 Combinational shifter design:
• The speed of a flip flop-based shifter is a function of the clock frequency
• A high-speed shifter can be designed using combinational circuit components such as a
multiplexer

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 7

 General Register Design
❑ 4x4 Combinational shifter design:

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 8

 General Register Design
❑ Combinational shifter capable of rotating 16-bit data to the left by 0, 1, 2 and 3
positions:

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 9

 General Register Design
❑ 16x16 Barrel shifter:
• Capable of rotating the given 16-bit data to the left n position where 0 ≤ 𝑛 ≤ 15

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 10

 General Register Design
❑ Complete Logic diagram of full 16-bit Barrel shifter:

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 11

 Adder Design
❑ Full adder:
• Addition is the basic operation performed by an ALU
• Operation is versatile
• A- B = A + 2's complement of B
• B*C may be obtained by adding A to itself for C - 1 times
• The speed of the hardware unit is essential to the efficient operation
of execution unit
Xi Yi Ci Si Ci+1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0 𝑠𝑖 = 𝑥𝑖 . 𝑦𝑖 . 𝑐𝑖 + 𝑥𝑖 . 𝑦𝑖 . 𝑐𝑖 + 𝑥𝑖 . 𝑦𝑖 . 𝑐𝑖 + 𝑥𝑖 . 𝑦𝑖 . 𝑐𝑖
0 1 1 0 1
1 0 0 1 0
𝑐𝑖+1 = 𝑥𝑖 . 𝑦𝑖 +𝑥𝑖 . 𝑐𝑖 + 𝑦𝑖 . 𝑐𝑖
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 12
 Adder Design
❑ Full adder:

• To generate Ci+1 from Ci, 2 gate delays are required

• To generate sum Si from Ci, 3 gate delays are required
• Assume that the gate delay is ∆ time units and the actual value of it is decided by the
technology used
• For example, TTL logic circuits have a ∆ will be 10 ns

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 13

 Adder Design
❑ 4-bit ripple carry adder/Carry Propagate Adder(CPA)

Total delay = (n-1)* delay between each block + last block delay
Wnere n is number of Full Adders
For n = 4 and if gate delay is 0.5ns, we get
Delay = (4 – 1 ) * 1 + 1.5 = 4.5 ns

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 14

 Adder Design
❑ 16-bit adder using 4-bit ripple carry adder as basic block
• Design of an n-bit CPA is straightforward the carry propagation time limits the speed of
operation
• For example: 16-bit CPA when the addition operation is completed only when the sum bits S0
through are S15 available
• In the worst case carry propagate through 15 full adders
• Total Time delay= Time taken for carry to propagate through 15 full adder + Time taken to
generate S15 from C14 = 15 ∗ 2∆ + 3∆= 33∆

• Circuit is simple and easy to build

• Ripple of carry is causing delay and
it increases as n increases.

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 15

 Fast Adder Design
❑ Carry Look-Ahead Adder (CLA)
• It is a type of adder used in digital logic that improves the speed of arithmetic operations by
reducing the time it takes to calculate carry bits
• Key Concepts:
1. Carry Propagation: In a traditional ripple carry adder, each bit must wait for the carry bit
from the previous bit to be calculated, which can be slow.
2. Carry Look-Ahead: The CLA adder speeds up this process by calculating the carry bits in
advance, using the concepts of generate and propagate.

• How It Works:
1. Carry Generate (G): A bit generates a carry if both of its input bits are 1.
2. Carry Propagate (P): A bit propagates a carry if at least one of its input bits is 1.

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 16

 Adder Design
❑ Carry Look-Ahead Adder (CLA)
• For Full adder, we know that:
𝑐𝑖+1 = 𝑥𝑖 . 𝑦𝑖 +𝑥𝑖 . 𝑐𝑖 + 𝑦𝑖 . 𝑐𝑖

• Carry generate function

𝐺𝑖 = 𝑥𝑖 . 𝑦𝑖
• Carry propagate function
𝑃𝑖 = 𝑥𝑖 +𝑦𝑖
• Carry function
𝑐𝑖+1 = 𝐺𝑖 + 𝑃𝑖 . 𝐶𝑖
• These equations show that a carry signal will be generated in two cases:
1. if both bits xi and yi are 1
2. if either xi or yi is 1 and the carry-in Ci is 1.

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 17

 Adder Design
❑ 4-bit Carry Look-Ahead Adder (CLA)
• Apply these equations for a 4-bit adder:

• These expressions show that C2, C3 and C4 do not depend on its previous carry-in.
• Therefore C4 does not need to wait for C3 to propagate.
• As soon as C0 is computed, C4 can reach steady state.
• The same is also true for C2 and C3

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 18

 Adder Design
❑ 4-bit Carry Look-Ahead Adder (CLA)
• Apply these equations for a 4-bit adder:

• These expressions show that C2, C3 and C4 do not depend on its previous carry-in.
• Therefore C4 does not need to wait for C3 to propagate.
• As soon as C0 is computed, C4 can reach steady state.
• The same is also true for C2 and C3
• For these reason, the equations are called carry look ahead equations
• The hardware that implements these equations is called 4-stage carry-look ahead circuit (4
CLC)

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 19

 General Register Design
❑ 4-stage Carry Look-Ahead circuit(4-CLC)
• A 4-CLC can be implemented as a teo-level AND/OR logic
circuit
• To generate C4, 5-input AND gate and 4-input OR gate
required
• If 𝐺𝑖 ≤ 0 ≤ 𝑖 ≤ 3 is available, then all 𝐶𝑖 ’s with 1 ≤ 𝑖 ≤ 4
can be generated in 2 gate delays
• The output G0 and P0 are useful to obtain a higher order look
ahead system

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 20

 General Register Design
❑ 4-bit CLA using basic adder

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 21

 General Register Design
❑ 16-bit CLA using 4-bit CLA
• A 16-bit CLA is typically divided
into four 4-bit CLAs.
• Each 4-bit CLA generates its own
carry-out signals, which are then
used to compute the carry-out
for the next higher level.

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 22

 Multiplication of Binary numbers
Basic Concept

product of two 4-bit numbers

multiplicand 1101 (13) is an 8-bit number
multiplier * 1011 (11)
Binary multiplication is easy
1101
0 × multiplicand = 0
1101 1 × multiplicand = multiplicand
Partial products 0000
1101
It’s interesting to note that
These partial 10001111 (143) binary multiplication is a
products are added sequence of shifts and adds of
to get the final one number (depending on the
product. bits in the second number).

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 23

 Multiplication of Binary numbers
❑ 4x4 array multiplication

• Each cross-product term in this can be generated using an AND gate

• This requires 16 AND gate to generate all cross-product terms that are
summed by full adder arrays
• It is nonadditive multiplier(NM), since it does not include any additive inputs

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 24

 Multiplication of Binary numbers
❑ 4x4 array multiplication
• An additive multiplier(AM) includes an extra input, it computes products of the form
P = M*Q + R

• Both NM and an AM are available as standard IC blocks

• Simple and repetitive structure

• Can multiply only unsigned numbers
• Need additional logic to multiply signed numbers
• Too big circuit and utilization factor is too less
• Delay grows as the number of bits to be multiplied increases

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 25

 Multiplication of Binary numbers
❑ Read Only Memory

ROM is a combinational circuit; it’s a truth-table

lookup. • Can perform any combinational
logic function
• Address inputs = function
inputs
• Data outputs = function
outputs

you give input numbers to be

multiplied and it will give you
the product!!

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 26

 Multiplication of Binary numbers
❑ Read Only Memory A B Product
00 00 0000
00 01 0000
00 10 0000
A 00 11 0000
Look up 01 00 0000
P 01 01 0001

B
table 01 10 0010
01 11 0011

11 00 0000
Address input Data output
11 01 0011
11 10 0110
Consider A and B to be 2-bit numbers, How 11 11 1001
many bits will be in product, P?
What is the memory size of this ROM? 8 bytes!! 16 locations
Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 27
 Multiplication of Binary numbers
❑ 4x4 ROM based multiplier example
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
How many address and data lines?

What is the memory size

of this ROM?
265 bytes
Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 28
 Multiplication of Binary numbers
❑ Sequential multiplier
• Sequential multiplier use the fact that multiplication can be achieved using
repeated addition
• It can multiply unsigned integers
• Next slides has a flowchart that can multiply two 4-bit unsigned numbers
and a block diagram for implementing it
• 4x4 unsigned sequential multiplier

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 29

 Multiplication of Binary numbers
❑ Sequential multiplier
Algorithm to multiply two unsigned 4-bit numbers

P
Start

Shift Right (CAQ)

Size = 4
M = Multiplicand
Q= multiplier
A = 0, C = 0 Size = Size - 1

is NO is
Q[0] = C, A = A + M Size = 0
1 YES
NO YES
P Stop
Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 30
 Multiplication of Binary numbers
❑ Sequential multiplier
• Example: M = 1100, Q = 1001
Description C A Q Q[0]
Initialization 0 0000 1001 1
Ite-1, A = A+M 0 1100 1001 1
SHR CAQ 0 0110 0100 0
Ite-2, No add 0 0110 0100 0
SHR CAQ 0 0011 0010 0
Ite-3, No add 0 0011 0010 0
SHR CAQ 0 0001 1001 1
Ite-4, A=A+M 0 1101 1001 1
SHR CAQ 0 0110 1100 0
0xC*0x9 = 0x6C
Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 31
 Multiplication of Binary numbers
❑ Sequential multiplier
M = 01110, Q = 10100
Description C A Q Q[0]
Initialization 0 00000 10100 0
Ite-1, SHR CAQ 0 00000 01010 0
Ite-2, SHR CAQ 0 00000 00101 1
Ite-3 A=A+M 0 01110 00101 1
SHR CAQ 0 00111 00010 0
Ite-4, SHR CAQ 0 00011 10000 1
Ite- 5 A=A+M 0 10001 10000 1
SHR CAQ 0 01000 11000 0
Worst case: n additions and n right shift operations are needed
Speed increased
0x0E*0x14 = 0x118
Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 32
 Multiplication of Binary numbers
❑ Signed multiplication
• There are three possible cases:
1. M&Q are in signed magnitude form
2. M and Q are in one’s complement form
3. M and Q are in Two's complement form
• Case 1:
• Multiply the magnitudes either combinationally or sequentially
• Sign of the product = sign of Multiplier XOR sig of Multiplicand
• Case 2:
• Step 1: if multiplicand is negative, then compute the 1’s complement of M
• Step 2: if multiplier is negative, then compute the 1’s complement of Q
• Step 3: multiply the (n – 1) bits of the multiplier and the multiplicand either combinnationally or
sequentially
• Step 4: sign of the product = sign of multiplier XOR sign of multiplicand
• Step 5: if sign of the product is negative, then compute the 1’s of the result obtained in Step 3

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 33

 Multiplication of Binary numbers
❑ Signed multiplication
• Case 3:
• When M & Q are in 2's complement form, the same procedure as in Case 2 is repeated with the
following exception:
• Product must be 2’s complemented when
• both multiplicand and multiplier are negative or
• sign of Multiplicand XOR Sign of Multiplier = 1
• Example: M=1100 and Q=0111, take 2’c complement of M, then multiply with
Q. since sign of product is –ve, take 2’s complement of product.
• Result: 11100100
• Demerits:
• extra processing when they are represented in 1’s or 2’s complement form
• Overhead is maximum when multiplier and multiplicand are in 2’s complement form, since
incrementation is required besides the complementation.
• Overhead can be eliminated by recoded multiplication approach

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 34

 Multiplication of Binary numbers
❑ Booth’s Recoded multiplication approach
• String property:
• In a binary sequence a block of consecutive K ones may be replaced with a block of k - 1
ഥ
consecutive 0’s surrounded by the digits 1 and 𝟏
• String property increases the density of
zeros in a given multiplier
• number of additions operations to be
performed is reduced
• allows for quick multiplication

ഥ(over bar), assuming that the original sequence

• If a weight of -1 is assigned to the digit 𝟏
is in 2’s complement form, both represent same number

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 35

 Multiplication of Binary numbers
❑ Booth’s Recoded multiplication approach
• Booth Observed that a String of 1’s May be Replaced as: 2 j + 2 j −1 + + 2i +1 + 2i = 2 j +1 − 2i
xn xn-1 ... xi xi-1 ... x0 (0)
yi=xi-1 - xi
yn ... yi ... y0
Booth’s Recoding Drawbacks
• case can come up where number of 1s
xi xi-1 Comments yi originally will be less than the recoded 1’s
0 0 string of zeros 0
1 1 string of ones 0
1 0 beg. string of ones -1
0 1 end string of ones 1 Recode 15
EXAMPLE: 0 0 1 1 1 1 0 0 1 1(0) 01111 10001
ഥ 0 1 0 𝟏
0 1 0 0 0 𝟏 ഥ

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 36

 Multiplication of Binary numbers
❑ Booth’s Algorithm
• Booth's Algorithm is a technique used in binary multiplication to optimize the process,
especially for signed numbers.
• It reduces the number of partial products, which can simplify and speed up the
multiplication.

• Key Concepts
• Recoding: Booth's Algorithm recodes the multiplier to reduce the number of partial
products. This is done by examining pairs of bits in the multiplier.
• Handling Signed Numbers: It efficiently manages both positive and negative multipliers by
using 2's complement representation.
• Efficiency with Consecutive Ones: The algorithm is particularly effective when the
multiplier has consecutive ones, converting them into fewer operations.

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 37

 Multiplication of Binary numbers
❑ Booth’s Algorithm
1. Initialization:
• Set up the multiplicand (A) and the multiplier (B).
• Compute the negative of the multiplicand (-A) using 2's complement.

2. Recoding:
• Examine pairs of bits in the multiplier (B) along with an extra bit (initially 0).
• Depending on the pair of bits, decide whether to add, subtract, or do nothing with the
multiplicand.

3. Partial Product Generation:

• Generate partial products based on the recoding step.
• Shift the partial products appropriately.

4. Summation:
• Sum the partial products to get the final result.

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 38

 Multiplication of Binary numbers
❑ Booth’s Algorithm

• Starting from right to left, look at two adjacent bits of the

multiplier
• Before starting, place a zero at the right of the LSB
• If bits = 00, do nothing
• If bits = 10 [read from LSB side], subtract the
multiplicand from the product
• Beginning of a string of 1’s
• If bits = 11, do nothing
• Middle of a string of 1’s
• If bits = 01 [read from LSB side], add the multiplicand to
the product
• End of a string of 1’s
• apply arithmetic right shift by one bit on product register

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 39

 Multiplication of Binary numbers
❑ Booth’s Algorithm
• Example: Multiply the numbers -- M = 0101, Q = 0111

Description A Q q-1
Initialization 0000 0111 0
1: A = A - M (subtract) 1011 0111 0
ASR AQ 1101 1011 1

2: ASR AQ 1110 1101 1

3: ASR AQ 1111 0110 1

4: A = A + M (Addition) 0100 0110 1

ASR AQ 0010 0011 0 5*7 = 23H
Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 40
 Multiplication of Binary numbers
❑ Booth’s Algorithm
• Example: Multiply M=-9 and Q=-13
• 2’s complement of -13 = 10011 and 2’s complement of -9 = 10111
A Q Q--1 M Operation
00000 10011 0 10111 initial stage
01001 10011 0 10111 A<-A-M
00100 11001 1 10111 ASR (1st iteration)
00010 01100 1 10111 ASR (2nd iteration)
11001 01100 1 10111 A<-A+M
11100 10110 0 10111 ASR (3rd iteration)
11110 01011 0 10111 ASR (4th iteration)
00111 01011 0 10111 A<-A-M
00011 10101 1 10111 ASR (5th iteration)

• Product : 0001110101 = (117)10

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 41

 Multiplication of Binary numbers
❑ Booth’s Algorithm
• Example: Multiply -8 and 12
• 2’s complement of -8 = 11000 and 12 = 01100
A Q Q-1 M operation
00000 01100 0 11000 initial stage
00000 00110 0 11000 ASR (1st iteration)
00000 00011 0 11000 ASR (2nd iteration)
01000 00011 0 11000 A<-A-M
00100 00001 1 11000 ASR (3rd iteration)
00010 00000 1 11000 ASR (4th iteration)
11010 00000 1 11000 A<-A+M
11101 00000 0 11000 ASR (5th iteration)

• Product : 2’s complement of (1110100000)2 = (-96)10

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 42

 Multiplication of Binary numbers
❑ Drawbacks to Booth's Algorithm
• Variable number of add/subtract operations and of shift operations between two
consecutive add/subtract operations
o Inconvenient when designing a synchronous multiplier
• Algorithm inefficient with isolated 1's
• Example:
• recoded as , requiring 8 instead of 4 operations
• Situation can be improved by examining 3 bits at a time rather than 2

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 43

 Adder Design
❑ Carry Look-Ahead Adder (CLA)

Dr. Bore Gowda S B, Additional Professor, Dept. of ECE, MIT, Manipal 44