Digital Logic Design I

Gate-Level Minimization

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 3-1 Introduction

 Gate-level minimization refers to the design task of

finding an optimal gate-level implementation of Boolean
functions describing a digital circuit.
 Formation of standard form of expression with minimum
number of literals

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 3-2 The Map Method
 The complexity of the digital logic circuit depends on
 The complexity of the algebraic expression
 Logic minimization
 Algebraic approaches: lack specific rules
 The Karnaugh map or K map
 A simple straight forward procedure
 A pictorial form of a truth table
 Applicable for the logic expression with variables < 7
 A diagram made up of squares
 Each square represents one minterm

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Review of Boolean Function
 Boolean function
 Sum of minterms
 Sum of products (or product of sum) in the simplest
form
 A minimum number of terms
 A minimum number of literals
 The simplified expression may not be unique
 It means one function may be represented by more
than one expression

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Two-Variable Map


Figure 3.1 Two-variable Map

x y
0 0 m0 = x’.y’
0 1 m1= x’.y
1 0 m2=x.y’
1 1 m3= x.y

Figure 3.2 Representation of functions in the map

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A Three-variable Map
 A three-variable map
 Eight minterms
 The Gray code sequence
 Any two adjacent squares in the map differ by only on variable
 Primed (complemented) in one square and
unprimed(uncomplemented) in the other
 e.g., m5 and m7 can be simplified
 m5+ m7 = xy'z + xyz = xz (y'+y) = xz

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Figure 3.3 Three-variable Map
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A Three-variable Map
 m0 and m2 (m4 and m6) are adjacent
 m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
 m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'

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 Example 3.1
 Example 3.1: simplify the Boolean function F(x, y, z) =
S(2, 3, 4, 5)
 F(x, y, z) = S(2, 3, 4, 5) = x'y + xy'

Figure 3.4 Map for Example 3.1, F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy'

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 Example 3.2
 Example 3.2: simplify F(x, y, z) = S(3, 4, 6, 7)
 F(x, y, z) = S(3, 4, 6, 7) = yz+ xz'

Figure 3.5 Map for Example 3-2; F(x, y, z) = Σ(3, 4, 6, 7) = yz + xz'

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Four adjacent Squares
 Consider four adjacent squares
 2, 4, and 8 squares
 m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz' = x'z'(y'+y) +xz'(y'+y) =
x'z' + xz‘ = z'
 m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz =x'z(y'+y) + xz(y'+y) =x'z +
xz = z

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Figure 3.3 Three-variable Map
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Four adjacent Squares
 Consider four adjacent squares
 2, 4, and 8 squares
 m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz' = x'z'(y'+y) +xz'(y'+y) =
x'z' + xz‘ = z'
 m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz =x'z(y'+y) + xz(y'+y) =x'z +
xz = z
yz 00 01 11 10

x 0 m0 m1 m3 m2

x 1 m4 m5 m7 m6

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Figure 3.3 Three-variable Map
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 Example 3.3
 Example 3.3: simplify F(x, y, z) = S(0, 2, 4, 5, 6)
 F(x, y, z) = S(0, 2, 4, 5, 6) = z'+ xy'

Figure 3.6 Map for Example 3-3, F(x, y, z) = Σ(0, 2, 4, 5, 6) = z' +xy'
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Example 3.4
 Example 3.4: let F = A'C + A'B + AB'C + BC
a) Express it in sum of minterms.
b) Find the minimal sum of products expression.
Ans:
F(A, B, C) = S(1, 2, 3, 5, 7) = C + A'B

Figure 3.7 Map for Example 3.4, A'C + A'B + AB'C + BC = C + A'B
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3.3 Four-Variable Map
 The map 1001 = m8
 16 minterms
 Combinations of 2, 4, 8, and 16 adjacent squares

March 24, 2024 Figure 3.8 Four-variable Map 14

 Example 3.5
 Example 3.5: simplify F(w, x, y, z) = S(0, 1, 2, 4, 5, 6, 8,
9, 12, 13, 14)

F = y'+w'z'+xz'

Figure 3.9 Map for Example 3-5; F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y' + w' z' +xz'
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 Example 3.6
 Example 3-6: simplify F = ABC (D+D’)+ (A+A’)BCD +
ABCD + ABC’(D+D’) = B’.C’ + B’.D’+A’.C.D’
 (m0,m2,m8,m10), (m2,m6)

Figure 3.9 Map for Example 3-6; ABC + BCD + ABCD

+ ABC= BD + BC +ACD

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Prime Implicants(P.I) and procedures
 All the minterms with 1’s are covered.
 Minimize the number of terms and number of variables.
 Simplified expression may not be unique
 A prime implicant: a product term obtained by combining the
maximum possible number of adjacent squares (combining all
possible maximum numbers of squares).
 Essential P.I.: a minterm is covered by only one prime implicant.
 The essential P.I. must be included.
 A single one is a prime implicant if it is not adjacent to any one.
 Two adjacent 1’s form a prime implicant provided they are not
within a group of four adjacent 1’s and so on.
 Essential prime implicant is found by looking at each square with a
1 and checking the number of prime implicants that cover it.
 The prime implicant is essential if it is the only prime implicant that
covers the minterm
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Algorithym of K map expression
 Step 1: Identify the ones that can not be combined with any other
ones. Encircle them. They are essential prime implicants.
 Step 2: Identify the ones that can be combined in a group of two
adjacent ones in only one way. Encircle such groups of ones.
 Step 3: Identify the ones that can be combined in a group of four
adjacent ones in only one way. Encircle such groups of ones.
 Step 4: Identify the ones that can be combined in a group of eight
adjacent ones in only one way. Encircle such groups of ones.
 Step 5After identifying the essential groups of 2, 4 and 8 ones, if
there are still some ones that not have been encircled, then these
are to be combined with each other or other already encircled ones.
But leftover ones should be encircled in a largest possible groups
and in as few groupings as possible.
 Form the logic expression

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 Prime Implicants
 Consider F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
 The simplified expression may not be unique
 F = BD+B'D'+CD+AD = BD+B'D'+CD+AB'
= BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'

March 24, 2024 Figure 3.11 Simplification Using Prime Implicants 19

3.4 Five-Variable Map=(ABCDE)
 Map for more than four variables becomes complicated
 Five-variable map: two four-variable map (one on the top of the
other). 2^5 = 32
 16 squares, A = 0, 16 squares A = 1, m15 = 01111
 m16 = 10000

March 24, 2024 Figure 3.12 Five-variable Map 20

Example 3.7 (cont.)
 Another Map for Example 3-7 00000 10000
 m0 and m16 are adjacent

March 24, 2024 Figure 3.13 Map for Example 3.7, F = A'B'E'+BD'E+ACE 21
 Table 3.1 shows the relationship between the number
of adjacent squares and the number of literals in the
term.

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 Example 3.7
 Example 3.7: simplify F = S(0, 2, 4, 6, 9, 13, 21, 23, 25,
29, 31), m0 to m15, have A = 0, m16 to m31 , A = 1
 (m0,m2,m4,m6), (m9,m13,m29,m25), (21,23,29,31)
 = A’.B’.E’ +B.D’E+ACE

F = A'B'E'+BD'E+ACE
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Example 3.7 (cont.)
 Another Map for Example 3-7

March 24, 2024 Figure 3.13 Map for Example 3.7, F = A'B'E'+BD'E+ACE 24
 Is it possible to get POS form or
maxterm form using K Map

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 let F(A, B, C) = S(1, 2, 3, 5, 7), it means for m0, m4 and
m6, F = 0 , F’ = Complement of F = Σ(0,4,6)
A\BC 00 01 11 10

0 0 1 1 1

1 0 1 1 0

F’= B’.C’ + ABC’

(F’)’ = F = (B+C)(A’+B’+C)
F= C + A'B
F': sum of products → F: product of sums
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Is it possible to get POS form or
maxterm form using K Map

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 3-5 Product of Sums Simplification
 Approach #1
 Obtain and simplify F' in the form of sum of products
 Apply DeMorgan's theorem F = (F')'
 F': sum of products → F: product of sums
 Approach #2: Form K map
 Obtain expression in POS considering squares with zero values
 Write each term in sum form
 Combinations of maxterms (it was minterms)
 M0M1 = (A+B+C+D)(A+B+C+D') = (A+B+C)+(DD') = A+B+C
CD
AB 00 01 11 10
00 M0 M1 M3 M2
01 M4 M5 M7 M6
11 M12 M13 M15 M14
10 M8 M9 M11 M10
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 Example 3.8
 Example 3.8: simplify F = S(0, 1, 2, 5, 8, 9, 10) into (a)
sum-of-products form, and (b) product-of-sums form:
F’ = (CD+ BD’+AB), (F’)’ = (CD+BD’+AB)’ = (C’+D’)(B’+D)(A’+B’)

a) F(A, B, C, D)= S(0, 1, 2, 5, 8,

9, 10) = B'D'+B'C'+A'C'D
SOP
a) F' = AB+CD+BD'
» Apply DeMorgan's theorem;
F=(A'+B')(C'+D')(B'+D)
» Or think in terms of maxterms
» POS

Figure 3.14 Map for Example 3.8, F(A, B, C, D)= S(0, 1,

2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D
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Hardware implementation of the SOP/POS

 Gate implementation of the function of Example 3.8

 In SOP, Product term and OR operation
 SOP/POS can be implemented two levels of logi gates

Sum-of products form Product-of sums form

Figure 3.15 Gate Implementation of the Function of Example 3.8

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 Sum-of-Minterm Procedure
 Consider the function defined in Table 3.2.
 In sum-of-minterm:

F ( x, y, z ) =  (1,3,4,6)

 In sum-of-maxterm:

F ( x, y, z ) = (0,2,5,7)

 Taking the complement of F

F ( x, y, z ) = ( x  z)( x  z )

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 Sum-of-Minterm Procedure
 Consider the function defined in Table 3.2.
 Combine the 1’s: F ( x, y, z ) =  (1,3,4,6)

F ( x, y , z ) = xz  xz 
 Combine the 0’s : 0

F'( x, y, z ) = xz  xz
F = (x+z)(x’+z’)

(F’)’ = (xz + x’z’)’ F ( x, y, z ) = (0,2,5,7)

F = (x’+z’)(x+z)
Figure 3.16 Map for the function of Table 3.2

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Is it possible to further simply the function

Yes by Don’t care condition

Don’t care condition is represented as d( )

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 3-6 Don't-Care Conditions
 The value of a function is not specified for certain
combinations of variables
 For BCD code; binary combinations from 1010-1111: don't care
 The don't-care conditions can be utilized in logic for
further minimization of the logic circuit
 In K map, don’t care condition is represented by x
symbol
 X can be treated as 1 for SOP form of equation
 X can be treated as 0 for POS form of equation
 X terms will be considered for grouping adjacent squares
provided it simplifies the logic expression
 In a given problem, don’t care terms are represented by d(x,y,z)

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 3-6 Don't-Care Conditions
 Example 3.9:
 Simplify F(w, x, y, z) = S(1, 3, 7, 11, 15) which has the
don't-care conditions d(w, x, y, z) = S(0, 2, 5).
 K(w,x,y,z) = π(-----) , d(w,x,y,z) = π(-----)

 Sol. In this problem, F function is essential minterms

that must be groped
 d is the don’t care conditioned will be used provided
logic expression can be further simplified.

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Example 3.9 (cont.)
 F = S(0, 1, 3, 7, 11, 15) ; logic expression using K map is F =
y.z + w‘.x'; F = w’.z + yz
 Find POS form of expression.

 F = S(1, 3, 5, 7, 11, 15), logic expression using K map

 F = yz + w'z

 Either expression is acceptable

Figure 3.17 Example with don't-care Conditions

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3-7 NAND and NOR Implementation
 NAND gate is a universal gate
 Can implement any digital system

Y=X

Figure 3.18 Logic Operations with NAND Gates

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NAND Gate
 Two graphic symbols for a NAND gate

Figure 3.19 Two Graphic Symbols for NAND Gate

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Two-level Implementation
 Two-level logic implementation

 NAND-NAND = sum of products

 Example: F = AB+CD
 (F’)’ = F = ((AB + CD)’)’ = ((AB)’.(CD)’)’
 F = ((AB)' (CD)' )' =AB+CD

March 24, 2024 Figure 3.20 Three ways to implement F = AB + CD 39

 Example 3.10
 Example 3-10: implement F(x, y, z) =

F ( x, y, z ) =  (1,2,3,4,5,7) F ( x, y, z ) = xy  xy  z

March 24, 2024 Figure 3.21 Solution to Example 3-10 40

Procedure with Two Levels NAND
 The procedure
 Simplified in the form of sum of products;
 A NAND gate for each product term; the inputs to
each NAND gate are the literals of the term (the first
level);
 A single NAND gate for the second sum term (the
second level);
 A term with a single literal requires an inverter in the
first level.

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Multilevel NAND Circuits
 Boolean function implementation
 AND-OR logic → NAND-NAND logic
 AND → AND + inverter
 OR: inverter + OR = NAND
 For every bubble that is not compensated by another small circle
along the same line, insert an inverter.

March 24, 2024 Figure 3.22 Implementing F = A(CD + B) + BC 42

NAND Implementation

March 24, 2024 Figure 3.23 Implementing F = (AB +AB)(C+ D) 43

NOR Implementation
 NOR function is the dual of NAND function.
 The NOR gate is also universal.

March 24, 2024 Figure 3.24 Logic Operation with NOR Gates
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 Two Graphic Symbols for a NOR Gate

Figure 3.25 Two Graphic Symbols for NOR Gate

Example: F = (A + B)(C + D)E POS form of expression

implementation

March 24, 2024 Figure 3.26 Implementing F = (A + B)(C + D)E 45

 Example

Example: F = (AB +AB)(C + D)

Figure 3.27 Implementing F = (AB +AB)(C + D) with NOR gates

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 3-8 Other Two-level Implementations (
 Wired logic
 A wire connection between the outputs of two gates
 Open-collector TTL NAND gates: wired-AND logic
 The NOR output of ECL gates: wired-OR logic

F = ( AB )  (CD ) = ( AB  CD ) = ( A  B)(C   D) AND-OR-INVERT function

F = ( A  B )  (C  D ) = [( A  B )(C  D )] OR-AND-INVERT function

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Figure 3.28 Wired Logic
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Non-degenerate Forms
 16 possible combinations of two-level forms
 Eight of them: degenerate forms = a single operation
 AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-
NOR, NOR-AND, NOR-NAND.
 The eight non-degenerate forms
 AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-
AND, OR-NAND, AND-NOR.
 AND-OR and NAND-NAND = sum of products.
 OR-AND and NOR-NOR = product of sums.
 NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?

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AND-OR-Invert Implementation
 AND-OR-INVERT (AOI) Implementation
 NAND-AND = AND-NOR = AOI
 F = (AB+CD+E)'
 F' = AB+CD+E (sum of products)
 (X’.y’.z’) = (x + y + z)’ =

Figure 3.29 AND-OR-INVERT circuits, F = (AB +CD +E)

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OR-AND-Invert Implementation
 OR-AND-INVERT (OAI) Implementation
 OR-NAND = NOR-OR = OAI
 F = ((A+B)(C+D)E)'
 F' = (A+B)(C+D)E (product of sums)

Figure 3.30 OR-AND-INVERT circuits, F = ((A+B)(C+D)E)'

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 Tabular Summary and Examples
 Example 3-11: F = x'y'z'+xyz'
 F' = x'y+xy'+z (F': sum of products)

 F = (x'y+xy'+z)' (F: AOI implementation)

 F = x'y'z' + xyz' (F: sum of products)

 F' = (x+y+z)(x'+y'+z) (F': product of sums)
 F = ((x+y+z)(x'+y'+z))' (F: OAI)

 F = Z’(x’y’ + xy)
 F’ = Z + (x+y)(x’+y’) = z + xx’ + xy’ + yx’ + yy’
 = z + xy’ + yx’

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Tabular Summary and Examples

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March 24, 2024 Figure 3.31 Other Two-level Implementations 53
3-9 Exclusive-OR Function
 Exclusive-OR (XOR)
 xy = xy'+x'y
 Exclusive-NOR (XNOR)
 (xy)' = xy + x'y'
 Some identities
 x0 = x , = x’0 + 0’.x = 0 + 1.x = x
 x1 = x‘ = x’1 + x.1’ = x’ + x.0 = x’
 xx = 0
 xx' = 1
 xy' = (xy)'
 x'y = (xy)'
 Commutative and associative
 AB = BA
 (AB) C = A (BC) = ABC

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Exclusive-OR Implementations
 Implementations
 (x'+y')x + (x'+y')y = xy'+x'y = xy

March 24, 2024 Figure 3.32 Exclusive-OR Implementations 55

Odd Function
 ABC = (AB'+A'B)C' +(AB+A'B')C = AB'C'+A'BC'+ABC+A'B'C
= S(1, 2, 4, 7)
 XOR is a odd function → an odd number of 1's, then F = 1.
 XNOR is a even function → an even number of 1's, then F = 1.

Figure 3.33 Map for a Three-variable Exclusive-OR Function

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XOR and XNOR
 Logic diagram of odd and even functions

Figure 3.34 Logic Diagram of Odd and Even Functions

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Four-variable Exclusive-OR function

 Four-variable Exclusive-OR function

 ABCD = (AB'+A'B)(CD'+C'D) =
(AB'+A'B)(CD+C'D')+(AB+A'B')(CD'+C'D)

Figure 3.35 Map for a Four-variable Exclusive-OR Function

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Parity Generation and Checking
 Parity Generation and Checking
 A parity bit: P = xyz
 Parity check: C = xyzP
 C=1: one bit error or an odd number of data bit error
 C=0: correct or an even # of data bit error

Figure 3.36 Logic Diagram of a Parity Generator and Checker

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Parity Generation and Checking

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Parity Generation and Checking

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 3.10 Hardware Description Language
(HDL)
 Describe the design of digital systems in a textual form
 Hardware structure
 Function/behavior
 Timing
 VHDL and Verilog HDL

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A Top-Down Design Flow

Specification

RTL design and

Simulation

Logic Synthesis

Gate Level Simulation

ASIC Layout FPGA Implementation

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Module Declaration
 Examples of keywords:
module, end-module, input, output, wire, and, or,
and not

Figure 3.37 Circuit to demonstrate an HDL

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 HDL Example 3.1
 HDL description for circuit shown in Fig. 3.37

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Gate Displays
 Example: timescale directive
 ‘timescale 1 ns/100ps

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 HDL Example 3.2
 Gate-level description with propagation delays for
circuit shown in Fig. 3.37

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 HDL Example 3.3
 Test bench for simulating the circuit with delay

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Simulation output for HDL
Example 3.3

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 Boolean Expression
 Boolean expression for the circuit of Fig. 3.37

 Boolean expression:

HDL Example 3.4

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HDL Example 3.4

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 User-Defined Primitives
 General rules:

 Declaration:

Implementing the hardware in Fig. 3.39

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 HDL Example 3.5

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 HDL Example 3.5 Continued)

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 Figure 3.39 Schematic for circuit with_UDP_02467

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