Lecture 3 – language

of the computer (Part

A)
Dr Joni Zhong
[email protected]
ISA
❑ISA: an abstract interface between the hardware and the lowest-level
software that encompasses all the information necessary to write a
machine language program that will run correctly, including instructions,
register, memory access, I/O, and so on.
❑To command a computer’s hardware, you must speak its language. The
words of a computer’s language are called instructions, and its vocabulary
is called instruction set.

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Crafting an ISA
❑We’ll look at some of the decisions facing an instruction set architect, and
❑How those decisions were made in the design of the MIPS instruction set.
❑MIPS is a RISC (Reduced Instruction Set Computer) ISA:
• Fixed instruction length
• Few instruction formats
• Load/store architecture
❑RISC architectures worked because they enabled pipelining.

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RISC vs CISC

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Assembly Language Instructions
❑The language of the machine
• Want an ISA that makes it easy to build the hardware and the
compiler while maximizing performance and minimizing cost.
❑Stored-program (Von Neumann) concept
• Instructions are stored in memory (as the data)

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The MIPS Instruction Set
❑MIPS: Microprocessor without Interlocked Pipeline Stages
❑Use as the example throughout the book
❑Stanford MIPS commercialized by MIPS Technologies (www.mips.com)
❑Large share of embedded core market
• Applications in consumer electronics, network/storage equipment,
cameras, printers,…

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Below the Program
❑High-level language program (in C)
swap (int v[], int k)
{ int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
❑Assembly language program (for MIPS)
swap: sll $2, $5, 2
add $2, $4,$2
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31
❑Machine (object) code for (MIPS)
000000 00000 00101 0001000010000000
000000 00100 00010 0001000000100000
100011 00010 01111 0000000000000000
100011 00010 10000 0000000000000100
101011 00010 10000 0000000000000000
101011 00010 01111 0000000000000100
000000 11111 00000 0000000000001000 7
How instructions are executed by computer?

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Input device inputs
swap (int v[], int
k)
{ int temp;
the program
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}

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Object code stored in Memory

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Processor fetches an instruction
❑Processor fetches an instruction from memory

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Control decodes the instruction
❑Control decodes the instruction to determine what to execute

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Datapath executes the instruction
❑Datapath executes the instruction as directed by control

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What happens next?

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What happens next?
❑Processor fetches the next instruction from memory.

Instruction Execution
Cycle
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Output data stored in Memory
❑At program completion the data to be output resides in memory

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Output device outputs data

0000010001010000000000000
00000000000000001001111000
000000000010000000011111000
000000000000001000
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Instruction execution cycle

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Von Neumann Architecture (FYI)

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BUS

❑In the computer, bus is a subsystem

that transfer data between different
components of the computer.
✧ Early computer use electrical wire
to connect between components.
✧ Today’s computer uses parallel
and bit serial connection.
❑Bus can be characterized by amount
of information that can transfer in a
certain period of time. This is
expressed in a bit.
✧ A 32-wire ribbon cable can
transmit 32 bit in parallel.

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System bus
Three types of system buses:
✧ Address bus: also called memory bus. It
transfers the memory address to the
memory in which CPU wants to access.
This is a unidirectional bus.
✧ Data bus: It is bidirectional bus, means
data or electronic signal can transfer in
both side. It can transfer data between
different component.
✧ Control bus: also called command bus. It
transports command and synchronization
signal those coming from control unit and
going towards hardware component. This
is a bidirectional bus. It transmits
response signal also.

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 The Central Processing Unit (CPU)

❑Control Unit needs to have circuitry to

• Decide which is the next instruction and input it from memory
• Decode the instruction
• Issue signals that control the way information flows between datapath
components
• Control what operations the datapath’s functional units perform
❑Datapath needs to have circuitry to
• Execute instructions - functional units (e.g. adder) and storage
locations (e.g. register file)
• Interconnect the functional units so that the instructions can be
executed as required
• Load data from and store data to memory

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The Central Processing Unit (CPU)

Registers

ALU

Control Unit

Program Counter

CPU
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 Registers
• Registers are fast storage devices used
inside processors
• Used to store computation results of a
running program etc.
Registers
• Numbers stored in registers are either
unsigned or signed ALU

Arithmetic logic unit (ALU)

• ALU is a combinational digital circuit that Control Unit
performs arithmetic and bitwise Program Counter
operations on integer binary numbers.
CPU
Program Counter (PC)
• The program counter is a 32-bit register
that contains the address pointer value of
the current instruction. 24
Memory Organization
❑The segment of the stack containing
a procedure’s saved registers and local
variables is its procedure frame
# last word alloc on stack
❑There is a static data segment area
for storing constants and other static
variables (e.g. arrays) # ptr into global data

❑And a dynamic data segment (aka

heap) area for structures that grow
and shrink (e.g. lined lists)
# ptr to next instruction

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Connection between processor and
memory
CPU Memory

Data
Registers bus

ALU

Control
Control Unit bus

Program Address
bus
Counter
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The MIPS ISA - Register File
❑When writing assembly, these registers can be referenced by their address
(number) or name
❑General purpose and special purpose registers
# Name Purpose # Name Purpose
$0 $zero Constant zero $16 $s0 Temporary – Callee saves
(Caller can clobber)
$1 $at Reserved by assembler $17 $s1
$2 $v0 Function Return value $18 $s2
$3 $v1 $19 $s3
$4 $a0 Function parameter $20 $S4
$5 $a1 $21 $s5
$6 $a2 $22 $s6
$7 $a3 $23 $s7
$8 $t0 Temporary – Caller saves $24 $t8 Temporary – Caller saves
(Callee can clobber) (Cont’d)
$9 $t1 $25 $t9
$10 $t2 $26 $k0 Reserved for OS
$11 $t3 $27 $k1
$12 $t4 $28 $gp Global pointer Register addresses
$13 $t5 $29 $sp Stack pointer are indicated by
$14 $t6 $30 $fp Frame pointer using $
$15 $t7 $31 $ra Function return address $t0, $s0, …

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MIPS Register File
❑Operands of arithmetic instructions must be from a limited
number of special locations contained in the datapath’s
register file
✧ Thirty-two 32-bit registers Register File
• Two reads ports
• One write port
❑A 32-bit data is called a “word”

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Key ISA decisions
Destination Operation
❑Operations operand
• How many?
• Which ones? y=x+b
❑Operands Source
• How many? operands
Compiler
• Location
• Types
add $t0, $s1, $s2
• How to specify? $t0 = $s1 + $s2
❑Instruction format How does the computer know
• Size what
0000 0010 0011 0010 0100 0000
• How many formats? 0010 0000 means?

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The Four Design Principles
1. Simplicity favors regularity.
2. Smaller is faster.
3. Make the common case fast
4. Good design demands good compromises.

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MIPS Instruction Set
Design Principle 1:
Simplicity favors
regularity

• Each instruction is
32 bits long.
• Opcode is 6 bits
long.
• Only three kinds of
instruction formats

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Arithmetic Instructions
(no need to memorize all, but should know
the main categories)

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Logical Instructions
Conditional Branch Instructions
Unconditional Jump Instructions
Data Transfer Instructions
Exercise
Identify the instruction format for each instruction and write down the
values of the opcode, register numbers, and immediates/jump targets (if
applicable)

❑add $t0, $s1, $s2

❑lw $t1, 4($s3)
❑j label

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MIPS Instructions Examples

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MIPS Arithmetic Instructions
❑MIPS assembly language arithmetic statement
add $t0, $s1, $s2 $t0=$s1+$s2
sub $t0, $s1, $s2
$t0=$s1-$s2
❑Each arithmetic instruction performs only one operation
❑Each arithmetic instruction specifies exactly three operands

• Operand order is fixed (the destination is specified first)

op dest, src1, src2
• Meaning: dest = src1 op src2
❑The operands are contained in the datapath’s register file
($t0, $s1, $s2)

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Compiling More Complex statements
❑Assuming variable b is stored in register $s1, c is
stored in $s2, and d is stored in $s3 and the result is
to be left in $s0, what is the assembler equivalent to
the C statement
h = (b - c) + d ;

$s0 = ($s1 - $s2) + $s3

$s0 = $s1 - $s2 sub $s0,$s1,$s2

$s0 = $s0 + $s3 add $s0,$s0,$s3
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Exercise
❑Assume that A -> $s0, B -> $s1, C -> $s2, D -> $s3, E -> $s4, F -> $s5
❑How to convert the equation in C below into MIPS?

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Exercise
❑Translating C code to MIPS assembly

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Representing Instructions in the
Machine
❑Remember the MIPS-32 instruction fields, R format
op rs rt rd shamt funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

❑Instruction fields
• op: operation code (opcode)
• rs: address of the first register source operand
• rt: address of the second register source operand
• rd: the register destination address
• shamt: shift amount (for shift instructions)
• funct: function code (extends opcode)

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R-format Example
❑Arithmetic instructions
add $t0, $s1, $s2

0x00 17 18 8 0 0x20

000000 10001 10010 01000 00000 100000

sub $t0, $s1, $s2

0x00 17 18 8 0 0x22

000000 10001 10010 01000 00000 100010

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How MIPS Register File reads/writes
data?
Assume:
$s1 = 3
$s2 = 9

00…………………1001
Register File 00…………………0011
10001 Src1 Src2
data data
10010 18 00…………………1001

01000 17 00…………………0011
8 00…………………1100 opcod + status
e

Result
00…………………1100
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Design Principle 1:
Simplicity favors regularity
The natural number of operands for an operation like
addition is three: the two numbers being added
together and a place to put the sum.
Requiring every instruction to have exactly three
operands, no more and no less, conforms to the
philosophy of keeping the hardware simple:
hardware for a variable number of operands is more
complicated than hardware for a fixed number.
This situation illustrates the first of three underlying
principles of hardware design:
Design Principle 1: Simplicity favors regularity.

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Registers vs. Memory
❑Arithmetic instructions operands must be in registers
❑Only 32 registers are provided

What about programs with lots of variables?

❑Compiler associates variables with registers

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Processor – Memory Interconnection
❑Memory is a large, single-dimensional array
❑An address acts as the index into the memory array

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Processor – Memory Interconnection
❑Memory is a large, single-dimensional array
❑An address acts as the index into the memory array

232 Bytes (4GB)

→
230 Words (1GW)

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50

Register File in CPU Memory

ASCII – communicating with people
❑Most computers use 8-bit bytes to represent characters, with the
American Standard Code for Information Interchange (ASCII)
❑ The following declarations are used to define a string “message” and
initialize it to “Hello World”.
✧ message: .asciiz “Hello World\n”
✧ .ascii defines an ASCII string
✧ .asciiz defines a NULL terminated ASCII string

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52
ASCII String
❑“Hello World” The MIPS architecture is usually big-endian by
default.
Note: The MIPS architecture as simulated in QtSpim
is little-endian.

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Word Addresses vs.
Byte Addresses
❑Alignment restriction - A requirement that data be aligned in memory
on natural boundaries.
✧ Since 8-bit bytes are so useful, most architectures also support
addressing individual bytes in memory
✧ Therefore, the address of a word matches the address of one of the 4
bytes within the word, the addresses of sequential words differ by 4.
✧ In MIPS, words must start at addresses that are multiple of 4.
❑Big Endian: most-significant byte is word address.
IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
❑Little Endian: least-significant byte is word address.
Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

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Memory Operands
❑Programming languages also have more complex data structures –
arrays and structures.
✧ These complex data structures can contain many more data elements
than there are registers in a computer.
✧ How can a computer represent and access such large structures?
❑Arithmetic operations occur only on registers in MIPS instructions
❑MIPS must include instructions that transfer data between memory and
registers.
✧ Such instructions are called data transfer instructions.

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MIPS Instructions

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Load/Store
❑The data transfer instruction that copies from memory to a register is
traditionally called load.
❑The instruction complementary to load is traditionally called store; it
copies data from a register to memory.

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Example 1
❑Let’s assume that A is an array of 100 words and that the
compiler has associated the variables g and h with the
registers $s1 and $s2. Let’s also assume that the starting
address, or base address, of the array A is in $s3. Compile
this C assignment statement:
g = h + A[8] ; Memory

❑Compiled MIPS code: A[8]

• Index 8 requires offset of 32 … …
• 4 bytes per word
A[1]
lw $t0, 32($s3) #load word from A[0]
memory
add $s1, $s2, $t0

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Example 2
❑C code:
A[12] = h + A[8] ;
✧ h in $s2, base address of A in $s3
❑Compiled MIPS code:
✧ Index 8 requires offset of 32
lw $t0, 32($s3) #load word from memory
add $s1, $s2, $t0
sw $s1, ?($s3) #store word to memory

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Memory Accessing
❑The memory address is formed by summing a constant (offset)
and the content of a register (base register).
…0110 24

…0101 20
Memor …1100 16
y
…0001 12

…0010 8

…1000 4

…0100 0
If $s3 holds 8, then Data Word Address

lw $t0, 4($s3) #what is loaded into $t0?

sw $t0, 8($s3) #the content of $t0 is stored
where?
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Register vs. Memory
❑Registers are faster to access than memory
❑Operating on memory data requires loads and stores
✧ More instructions to be executed
❑Compiler must use registers for variables as much as possible
✧ Only spill to memory for less frequently used variables
✧ Register Optimization is important!

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MIPS Instructions

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Immediate Operands
❑Constant data specified in an instruction
addi $s3,$s3,4
❑No subtract immediate instruction
❑Just use a negative constant
addi $s2,$s1,-1
❑Design Principle 3: Make the common case fast
✧ Small constants are common
✧ Immediate operand avoids a load instruction

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The Constant Zero
❑MIPS register 0 ($zero) is the constant 0
✧ Cannot be overwritten
❑Useful for common operations
✧ e.g. move between registers
add $t2,$s1,$zero

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MIPS Instructions so far

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Machine Language - Arithmetic
❑Instructions are encoded in binary
✧ Called machine code
❑MIPS instructions
✧ Encoded as 32-bit instructions words
✧ Small number of formats encoding operation code (opcode), register
numbers, …
✧ Regularity
• Example: add $t0,$s1,$s2
Registers have numbers $t0=$8,$s1=$17,$s2=18

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Representing Instructions in the
Machine
❑Remember the MIPS-32 instruction fields, R format
op rs rt rd shamt funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

❑Instruction fields
• op: operation code (opcode)
• rs: address of the first register source operand
• rt: address of the second register source operand
• rd: the register destination address
• shamt: shift amount (for shift instructions)
• funct: function code (extends opcode)

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R-format Example
❑Arithmetic instructions
add $t0, $s1,
$s2
000000 10001 10010 01000 00000 100000

0x00 17 18 8 0 0x20

sub $t0, $s1,

$s2

000000 10001 10010 01000 00000 100010

0x00 17 18 8 0 0x22

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I-format Instructions
❑Remember the MIPS-32 instruction fields, I format
❑Data transfer instructions
Base
two’s complement
op registe rt
r
number

6 bits 5 bits 5 bits 16 bits

lw $t0, 24($s2)
0x23 18 8 24

100011 10010 01000 0000 0000 0001 1000

sw $t0, 24($s2)
0x2b 18 8 24

101011 10010 01000 0000 0000 0001 1000

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 I-format Instructions
❑Remember the MIPS-32 instruction fields, I format
two’s complement
op rs rt
number
6 bits 5 bits 5 bits 16 bits

❑Immediate instructions
addi $t0, $s2, 4
001000 10010 01000 0000 0000 0000 0100

0x08 18 8 4

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Summary

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MIPS-32 ISA
❑Instruction Categories
✧ Computational
✧ Load/Store
✧ Jump and Branch
✧ Floating Point
• coprocessor
✧ Memory Management
✧ Special
❑3 Instruction Formats: all 32 bits wide
R
op rs rt rd sa funct
format

I
op rs rt immediate
format

op Jump target J format 72