COMPUTER ORGANIZATION AND DESIGN 5th
Edition
The Hardware/Software Interface
Chapter 2
Instructions: Language
of the Computer
Instruction - Introduction
Instruction Set Architecture (ISA) refers to
actual programmer visible instruction set.
It acts as a boundary between hardware
and software
Instruction : It is a command given to the
computer’s hardware(processor)
Chapter 2 — Instructions: Language of the Computer — 2
§2.1 Introduction
Instruction Set
Instruction Set : A Group of instructions
designed for a particular hardware
Different computers have different
instruction sets
But with many aspects in common
Early computers had very simple
instruction sets
Simplified implementation
Many modern computers also have simple
instruction sets
Chapter 2 — Instructions: Language of the Computer — 3
§2.1 Introduction
Instruction Set
Goal of Computer Designer : To find a language
that makes it easy to build the hardware and the
compiler to maximize performance & minimize
the cost and power
MIPS is the most popular embedded core
Chapter 2 — Instructions: Language of the Computer — 4
The MIPS Instruction Set
Used as the example throughout the book
Stanford MIPS commercialized by MIPS
Technologies (www.mips.com)
Large share of embedded core market
Applications in consumer electronics, network/storage
equipment, cameras, printers, …
Typical of many modern ISAs
See MIPS Reference Data tear-out card, and
Appendixes B and E
Chapter 2 — Instructions: Language of the Computer — 5
The MIPS Instruction Set
It has
32 programmer visible registers
32 floating registers
Status register
Program counter
Every assembly language instruction is preceded by $
Special registers Lo and Hi used to store result of
multiplication and division and not directly
addressable
Contents accessed with special instrction mfhi(“move
from Hi”) and mflo(“move from Lo”)
In MIPS, stack grows from high memory to low
memory
Chapter 2 — Instructions: Language of the Computer — 6
MIPS Registers
MIPS Registers
21 - 25
MIPS Registers Summary
Name Register number Usage
$zero 0 the constant value 0
$v0-$v1 2-3 values for results and expression evaluation
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved (by callee)
$t8-$t9 24-25 more temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 return address
H.Corporaal 5MD00 9
Operations of the Computer Hardware
To perform arithmetic operations such as
ADD rd, r1, r2 ( where rd = r1 + r2 )
SUB rd, r1, r2 ( where rd = r1 - r2 )
So it needs 3 operands : one for destination (rd)
and the other two for sources (r1 and r2)
Operand order are fixed.
Chapter 2 — Instructions: Language of the Computer — 10
Operations of the Computer Hardware
Operand order are fixed . How?
Example : Given C code : a = b + c,
Compiler is used to translate the c code to
MIPS assembly language instruction
MIPS Code : ADD $s1, $s2, $s3; the sum
of b and c is placed in a
Assumption : a, b and c are stored in register
$s1, $s2, $s3
Chapter 2 — Instructions: Language of the Computer — 11
Main Types of Instructions
Arithmetic
Integer
Floating Point
Memory access instructions
Load & Store
Control flow
Jump
Conditional Branch
Call & Return
H.Corporaal 5MD00 12
MIPS arithmetic
Most instructions have 3 operands
Operand order is fixed (destination first)
Example:
C code: A = B + C
MIPS code: add $s0, $s1, $s2
($s0, $s1 and $s2 are associated with variables by
compiler)
H.Corporaal 5MD00 13
MIPS arithmetic
C code: A = B + C + D;
E = F - A;
MIPS code: add $t0, $s1, $s2
add $s0, $t0, $s3
sub $s4, $s5, $s0
Operands must be registers, only 32 registers provided
14
§2.2
2.2 Operations of the Computer Hardware
Arithmetic Operations
Design Principle 1: Simplicity favours
regularity
Regularity makes implementation simpler
Simplicity enables higher performance at
lower cost
Chapter 2 — Instructions: Language of the Computer — 15
Example
C code:
f = (g + h) - (i + j);
f, …, j in $s0, …, $s4
Compiled MIPS code:
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
Chapter 2 — Instructions: Language of the Computer — 16
§2.2
2.2 Operations of the Computer Hardware
Arithmetic Operations
Assumption: g, h, i, j are stored in $s1,
$s2, $s3, $s4 and
temporary register $t0 and $t1 are used to
store intermediate result
Compiler must break this statement into
several assembly instructions
Chapter 2 — Instructions: Language of the Computer — 17
§2.2
2.2 Operations of the Computer Hardware
Arithmetic Operations
Since only one operation is performed per
MIPS instruction
Step 1 : Calculate the sum of g and h &
place the result in temporary register $t0
Step 2: Calculate the difference of I and j &
place the result in temporary register $t1
Step 3: Finally take the difference between
$t0 and $t1, to get the final result
Chapter 2 — Instructions: Language of the Computer — 18
§2.3
2.3 Operands of the Computer Hardware
1. Register Operands
In MIPS ISA, operand can either in register or memory
Arithmetic instructions use register
operands
Very limited no. of registers built on hardware and they
are visible to the programmer
MIPS has a 32 × 32-bit register file
Use for frequently accessed data
Numbered 0 to 31
32-bit data called a “word”
Chapter 2 — Instructions: Language of the Computer — 19
§2.3
2.3 Operands of the Computer Hardware
Register Operands
Assembler names
$t0, $t1, …, $t9 for temporary values
$s0, $s1, …, $s7 for saved variables
Design Principle 2: Smaller is faster
Larger the no. of registers, more will be the clock
cycle time
Use fewer registers to conserve energy
Chapter 2 — Instructions: Language of the Computer — 20
Register Operand Example
C code:
f = (g + h) - (i + j);
f, …, j in $s0, …, $s4
Compiled MIPS code:
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
Chapter 2 — Instructions: Language of the Computer — 21
2. Memory Operands
Main memory used for composite(complex)data
Arrays, structures, dynamic data
To apply arithmetic operations
Load values from memory into registers
Store result from register to memory
Memory is byte addressed
Each address identifies an 8-bit byte
Words are aligned in memory
Address must be a multiple of 4 bytes
MIPS is Big Endian
Most-significant byte at least address of a word
c.f. Little Endian: least-significant byte at least address
Chapter 2 — Instructions: Language of the Computer — 22
Memory Operand Example 1
C code:
g = h + A[8];
g in $s1, h in $s2, base address of A in $s3
Compiled MIPS code:
Index 8 requires offset of 32
4 bytes per word
lw $t0, 32($s3) # load word
add $s1, $s2, $t0
offset base register
Chapter 2 — Instructions: Language of the Computer — 23
Memory Operand Example 2
C code:
A[12] = h + A[8];
h in $s2, base address of A in $s3
Compiled MIPS code:
Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word
Chapter 2 — Instructions: Language of the Computer — 24
Registers vs. Memory
Arithmetic instruction operands must be registers,
— only 32 registers provided
Compiler associates variables with registers
What about programs with lots of variables ?
CPU Memory
register file
IO
25
Register allocation
Compiler tries to keep as many variables in registers as
possible
Some variables can not be allocated
large arrays (too few registers)
aliased variables (variables accessible through
pointers in C)
dynamic allocated variables
heap
stack
Compiler may run out of registers => spilling
Register optimization is important!
H.Corporaal 5MD00 26
3. Immediate Operands
Constant is a designated value, which will
not be changed and also not allowed to
change during program execution
More than 50% of MIPS arithmetic &
logical instructions have a constant as an
operand
It includes constant as a part of the
instruction, called immediate operand
Chapter 2 — Instructions: Language of the Computer — 27
Immediate Operands
Constant data specified in an instruction
addi $s3, $s3, 4
No subtract immediate instruction
Just use a negative constant
addi $s2, $s1, -1
Design Principle 3: Make the common
case fast
Small constants are common
Immediate operand avoids a load instruction
and uses less energy
Chapter 2 — Instructions: Language of the Computer — 28
Immediate Operands
What is the MIPS assembly code for the C
assignment statement below?
A = h+ 25 ; assume variable h is associated
with register $s2 and a is associated with $s3
Chapter 2 — Instructions: Language of the Computer — 29
Immediate Operands
What is the MIPS assembly code for the C
assignment statement below?
A = h+ 25 ; assume variable h is associated
with register $s2 and a is associated with $s3
// MIPS code
Addi $s3, s2, 25; # Given constant is added
to register $s2 and place the result in $s3
Chapter 2 — Instructions: Language of the Computer — 30
The Constant Zero
MIPS register 0 ($zero) is the constant 0
Cannot be overwritten
Useful for common operations
E.g., move between registers
add $t2, $s1, $zero
Chapter 2 — Instructions: Language of the Computer — 31
Memory Organization
Chapter 2 — Instructions: Language of the Computer — 32
Memory Organization
Viewed as a large, single-dimension array, with an
address
A memory address is an index into the array
"Byte addressing" means that successive addresses are
one byte apart
0 8 bits of data
1 8 bits of data
2 8 bits of data
3 8 bits of data
4 8 bits of data
5 8 bits of data
6 8 bits of data
...
H.Corporaal 5MD00 33
Memory Organization
Bytes are nice, but most data items use larger "words"
For MIPS, a word is 32 bits or 4 bytes.
0 32 bits of data
4 32 bits of data Registers hold 32 bits of data
8 32 bits of data
...
12 32 bits of data
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
H.Corporaal 5MD00 34
Memory layout: Alignment
31 23 15 7 0
0 this word is aligned; the others are not!
4
8
address
12
16
20
24
Words are aligned
What are the least 2 significant bits of a word
address?
H.Corporaal 5MD00 35
Representing Instruction in Computer
In Stored computer concept, computers
built on 2 key principles :
Instructions are represented as numbers
Therefore, entire programs can be stored in
memory to be read or written just like numbers
(data)
Chapter 2 — Instructions: Language of the Computer — 36
Instruction Format - Introduction
Machine Code : Each instruction is encoded in
binary ( machine readable form)
All MIPS instructions, encoded as 32-bit
instruction words & it is divided into small
segment called “fields” and each field has
something about instruction.
Also can reuse fields across instructions as
much as possible
This layout of instruction is called Instruction
Format
Chapter 2 — Instructions: Language of the Computer — 37
MIPS Fields : Instruction Format
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op : Basic operation of instruction – opcode
specify partially what instruction is it
rs : The first register source operand
rt : The second register source operand
shamt : Shift amount used in shift instructions
funct : Function. This field selects the specific variant of
the operation in op field and is so called Function code
ie. Combine with opcode, this number exactly specify
the instruction
MIPS Fields : Instruction Format
Translate a MIPS Assembly Instruction into a Machine
Instruction:
add $t0, $s1, $s2
Solution : First as a combination of decimal numbers & then
of binary numbers
Op $s1 $s2 $t0 0 add
Decimal : 0 17 18 8 0 32
Binary : 000000 10001 10010 01000 00000 100000
000000100011001001000000001000002 = 0232402016
Machine code
Signed & Unsigned Number
Computers represent numbers in binary
Hexadecimal notation is sometimes used to represent
binary as it is more concise
Binary : 2 possible digit or bits : 0 and 1
Computers represent both positive & negative numbers
Example : 124 – 237 = - 113
So need a method to represent negative numbers in binary
computer arithmetic operations
One of the digits of binary number is used to represent the sign
of the number
Chapter 2 — Instructions: Language of the Computer — 40
Signed & Unsigned Number
3 Methods
Sign and magnitude representation
One’s complement method
Two’s complement method
Chapter 2 — Instructions: Language of the Computer — 41
§2.4
2.4 Signed and Unsigned Numbers
Unsigned Binary Integers
Given an n-bit number
x = x n−1 2n−1 + x n−2 2n−2 + L + x1 21 + x 0 20
Range: 0 to +2n – 1
Example
0000 0000 0000 0000 0000 0000 0000 10112
= 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
Using 32 bits Since 232 – 1 = 4,294,967,295
0 to +4,294,967,295
Chapter 2 — Instructions: Language of the Computer — 42
2s-Complement Signed Integers
Given an n-bit number
x = − x n−1 2n−1 + x n−2 2n−2 + L + x1 21 + x 0 20
Range: –2n – 1 to +2n – 1 – 1
Example
1111 1111 1111 1111 1111 1111 1111 11002
= –1×231 + 1×230 + … + 1×22 +0×21 +0×20
MSB =
sign bit
= –2,147,483,648 + 2,147,483,644 = –410
Using 32 bits Since 232-1 = 231 = 2,147,483,648
–2,147,483,648 to +2,147,483,647
Chapter 2 — Instructions: Language of the Computer — 43
Signed Negation
Complement and add 1
Complement means 1 → 0, 0 → 1
x + x = 1111...1112 = −1
x + 1 = −x
1’s complement
Example: negate +2
+2 = 0000 0000 … 00102
–2 = 1111 1111 … 11012 + 1
= 1111 1111 … 11102
Chapter 2 — Instructions: Language of the Computer — 44
2s-Complement Signed Integers
Bit 31 is sign bit
1 for negative numbers
0 for non-negative numbers
–(–2n – 1) can’t be represented
Non-negative numbers have the same unsigned
and 2s-complement representation
Some specific numbers
0: 0000 0000 … 0000
–1: 1111 1111 … 1111
Most-negative: 1000 0000 … 0000
Most-positive: 0111 1111 … 1111
Chapter 2 — Instructions: Language of the Computer — 45
§2.5
2.5 Representing Instructions in the Computer
Representing Instructions
Instructions are encoded in binary
Called machine code
MIPS instructions
Encoded as 32-bit instruction words
Small number of formats encoding operation code
(opcode), register numbers, …
Regularity!
32 Registers can be accessed by name or number
Register
Name Register numbers Register No
$t0 – $t7 are reg’s 8 – 15
$t8 – $t9 are reg’s 24 – 25
$s0 – $s7 are reg’s 16 – 23
Chapter 2 — Instructions: Language of the Computer — 46
Instructions: load and store
Example:
C code: A[8] = h + A[8];
MIPS code: lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 32($s3)
Store word operation has no destination (reg) operand
Remember arithmetic operands are registers, not
memory!
H.Corporaal 5MD00 47
Our First C code translated
Can we figure out the code?
swap(int v[], int k);
{ int temp;
temp = v[k]
swap:
v[k] = v[k+1];
muli $2 , $5, 4
v[k+1] = temp;
add $2 , $4, $2
}
lw $15, 0($2)
Explanation: lw $16, 4($2)
index k : $5 sw $16, 0($2)
base address of v: $4
address of v[k] is $4 + 4.$5 sw $15, 4($2)
jr $31
H.Corporaal 5MD00 48
So far we’ve learned:
MIPS
— loading words but addressing bytes
— arithmetic on registers only
Instruction Meaning
add $s1, $s2, $s3 $s1 = $s2 + $s3
sub $s1, $s2, $s3 $s1 = $s2 – $s3
lw $s1, 100($s2) $s1 = Memory[$s2+100]
sw $s1, 100($s2) Memory[$s2+100] = $s1
H.Corporaal 5MD00 49
Machine Language: R-type instr
Instructions, like registers and words of data, are also 32 bits long
Example: add $t0, $s1, $s2
Registers have numbers: $t0=9, $s1=17, $s2=18
Instruction Format:
op rs rt rd shamt funct
000000 10001 10010 01000 00000 100000
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Can you guess what the field names stand for?
H.Corporaal 5MD00 50
MIPS R-format (for register) Instructions
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Instruction fields
op: operation code (opcode)
rs: first source register number
rt: second source register number
rd: destination register number
shamt: shift amount (00000 for now)
funct: function code (extends opcode)
Chapter 2 — Instructions: Language of the Computer — 51
MIPS R-format (for register) Instructions
To specify an operand, these instructions include
Arithmetic & logic with all operands in registers
Shift instructions
Register direct jump instructions( jalr and jr )
To specify an operand, these instructions do not require
an immediate value
target offset
Memory address displacement
Need to
Branch address or memory address compromise
Unused fields are coded with all 0 bits
All R-type instructions use a Opcode 000000
Operation is specified by the function fields
MIPS R-format (for register) Instructions
In MIPS, 32 – 32 bit general purpose registers are
available
These registers can be accessed by name or number
Registers $s0 to $s7 map onto register no. 16 to 23
Registers $t0 to $t7 map onto register no. 8 to 15
Register $s0 maps to register16
Register $s1 maps to register17 and so on
Similarly for $t0 means register 8 and so on
R-format Example
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
add $t0, $s1, $s2
Op $s1 $s2 $t0 0 add
0 17 18 8 0 32
000000 10001 10010 01000 00000 100000
000000100011001001000000001000002 = 0232402016
Chapter 2 — Instructions: Language of the Computer — 54
Hexadecimal
Base 16 ( to represent binary more concise)
Compact representation of bit strings
4 bits per hex digit
0 0000 4 0100 8 1000 c 1100
1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111
Example: eca8 6420
1110 1100 1010 1000 0110 0100 0010 0000
Chapter 2 — Instructions: Language of the Computer — 55
MIPS I-format Instructions
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits
Immediate arithmetic and load/store instructions
rt: destination or source register number
Constant: –215 to +215 – 1
Address: offset added to base address in rs
Design Principle 4: Good design demands good
compromises
Different formats complicate decoding, but allow 32-bit
instructions uniformly
Keep formats as similar as possible
MIPS I-format (for Immediate) Instructions
To specify an operand, these instructions include
an immediate operand
data transfer instructions
displacement for a memory operand
Branch target offset or memory address
In MIPS architecture, all memory accesses are handled
by the main processor
So it includes coprocessor load and store instructions
First 3 fields of I and R format are the same size, have
the same names
Length of last 3 fields of R-format = length of 4th field in I-
type
Adv:
Reduce the complexity in design
Machine Language: I-type instr
Example: lw $t0, 32($s2)
35 18 9 32
op rs rt 16 bit number
H.Corporaal 5MD00 62
Memory Operand Example 2
C code:
A[300] = h + A[300];
h in $s2, base address of A in $s3
Compiled MIPS code:
Index 8 requires offset of 32
lw $t0, 1200($s3) # load word
add $t0, $s2, $t0
sw $t0, 1200($s3) # store word
Chapter 2 — Instructions: Language of the Computer — 68
Memory Operand Example 2
Op rs rt rd shamt funct lw $t0, 1200($s3)
add $t0, $s2, $t0
sw $t0, 1200($s3)
35 19 8 1200
Register Mapping
0 18 8 8 0 32 8 – 15 = t0 – t7
16 – 23 = s0 – s7
43 19 8 1200
100011 01001 01000 0000 0100 1011 0000
000000 10010 01000 01000 00000 100000
101011 01001 01000 0000 0100 1011 0000
Chapter 2 — Instructions: Language of the Computer — 69
Examples : 32bit immediate
lui register, immediate
bit MIPS register ( r1)
Loading 32 bit Immediates in Two Instructions
This is an I-type instruction.
R[t] = IR15-0 016
It loads the upper 16 bits of R[t] with the 16 bit immediate,
and the lower 16 bits with all 0's.
Example : 0xABABCDCD Since, Immediate field supports only
32-bit
16bits, but to support 32-bits constant
Lui $at, 0xABAB value, how?
0xABAB : 1010 1011 1010 1011 0000 0000 0000 0000
Perform ori with the above and rest of 4 bytes(0xCDCD)
ori $at, $at, 0xCDCD
Examples
Lui $at, 0xABAB
0xABAB : 1010 1011 1010 1011 0000 0000 0000 0000
Perform Bitwise ori with the above and rest of 4
bytes(0xCDCD) => 32-bit constant value obtained
ori $at, $at, 0xCDCD
0xABAB : 1010 1011 1010 1011 0000 0000 0000 0000
0xCDCD: 1100 1101 1100 1101
0xABABCDCD : 1010 1011 1010 1011 1100 1101 1100 1101
Examples
lui register, immediate
Stands for load upper immediate, takes 16-bit immediate and puts
these bits in the upper half(high order half) of the specified register
and sets lower half to 0s
Since, Immediate field supports only 16bits,
but to support 32-bits constant value, how?
Example:
addi $t0, $t0, 0xABABCDCD
becomes : pseudo-instruction
lui $at, 0xABAB
ori $at, $at, 0xCDCD
add $t0, $t0, $at
Chapter 2 — Instructions: Language of the Computer — 72
Examples
Reason:
Each I-format instruction has only a 16-bit
immediate.
An instruction that must be broken up is
called a pseudo-instruction
So $at (assembler temporary register)
was used in this code
Chapter 2 — Instructions: Language of the Computer — 73
Examples
Translate MIPS Assembly Language into
Machine Language for the given
instruction :
lw $t0, 32($s3)
Chapter 2 — Instructions: Language of the Computer — 74
Examples
Translate MIPS Assembly Language into
Machine Language for the given
instruction :
lw $t0, 32($s3)
Op $s1 $s2 Constant or Address
35 19 8 32
Chapter 2 — Instructions: Language of the Computer — 75
Summary : Represent instruction in a
computer
Instruction Format
Registers
Machine Language
MIPS : R-type and I-type
Chapter 2 — Instructions: Language of the Computer — 76
Summary
Name Example Comments
32 Registers $s0, $s1 … $s7 Fast locations for data in MIPS,
Data must be in registers to perform
arithmetic.
Registers $s0 - $s7 map to 16 – 23 and
$t0 - $t7 map to 8 – 15
230 memory Memory[0], Accessed only by data transfer instructions in
words Memory[4],… MIPS.
Memory[4,294,967,292] MIPS uses byte addresses.
So sequential words differ by 4
Memory holds data structures, such as
arrays and spilled registers
Chapter 2 — Instructions: Language of the Computer — 77
Summary
Category Instruction Example Meaning Comments
Add add $s1, $s2, $s3 $s1 = $s2 + $s3 3 operands;
data in
Arithmetic registers
Subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 3 operands;
data in
registers
load word lw $s1, 100($s2) $s1 = Memory[$s2+100] Data from
memory to
Data register
Transfer Store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Data from
register to
memory
Chapter 2 — Instructions: Language of the Computer — 78
Summary
Name Format Example Comments
add R 0 18 19 17 0 32 add $s1, $s2, $s3
sub R 0 18 19 17 0 34 sub $s1, $s2, $s3
lw I 35 18 17 100 lw $s1, 100($s2)
Sw I 43 18 17 100 sw $s1, 100($s2)
Field 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS
Size instruction 32 bits
R-format R op rs rt rd shamt Funct Arithmetic
instruction format
I-format I op rs rt address Data transfer
format
Chapter 2 — Instructions: Language of the Computer — 79
