Computer Organization

Instructor: Dr. Raqibul Hasan

Slide Sources: Patterson &
Hennessy COD book website
(copyright Morgan Kaufmann)
adapted and supplemented
 The Five Classic Components
of a Computer
■ Input (mouse, keyboard, …)
■ Output (display, printer, …)
■ Memory Input
■ main (DRAM), cache (SRAM)
■ secondary (disk,
CD, DVD, …) Outpu
■ Datapath Processor t
Processor
■ Control (CPU)
Control
Memory
10010100101100
00101001010100
00
01
11110111011001
10
10010100101100
00
10010100101100
Datapath 00
10010100101100
00
 The Instruction Set:
a Critical Interface

software

instruction set

hardware
 What is Computer Architecture?
Easy Answer

Computer Architecture =
Instruction Set Architecture +
Machine Organization (datapath & cotrol)
COD Ch. 2
Instructions: Language of the
Machine
Instructions: Overview
■ Language of the machine
■ More primitive than higher level languages
■ Collection of bits that a computer understands
■ e.g., MIPS arithmetic instructions
■ We’ll be working with the MIPS instruction set architecture
■ inspired most architectures developed since the 80's
■ used by NEC, Nintendo, Silicon Graphics, Sony
■ it stands for microcomputer without interlocked pipeline stages !
■ Design goals: maximize performance and minimize cost
and reduce design time
 MIPS Arithmetic
■ All MIPS arithmetic instructions have 3 operands
■ Operand order is fixed (e.g., destination first)
■ Assembly instruction: symbolic representation of an instruction.

■ Example:
compiler’s job to associate
C code: A = B + C variables with registers

MIPS code: add $s0, $s1, $s2

MIPS Arithmetic
■ Design Principle 1: simplicity favors regularity .
Translation: Regular instructions make for simple hardware!

■ Simpler hardware reduces design time and manufacturing cost.

Allowing variable number
■ Of course this complicates some things... of operands would
simplify the assembly
C code: A = B + C + D; code but complicate the
E = F - A; hardware.

MIPS code add $t0, $s1, $s2

(arithmetic): add $s0, $t0, $s3
sub $s4, $s5, $s0
MIPS Arithmetic
■ Operands must be in registers – only 32 registers provided
(which require 5 bits to select one register). Reason for small
number of registers:

■ Design Principle 2: smaller is faster . Why?

■ Electronic signals have to travel further on a physically larger chip
increasing clock cycle time.
■ Smaller is also cheaper!
Registers vs. Memory
■ Arithmetic instruction operands must be in registers
■ MIPS has 32 registers
■ Compiler associates variables with registers
■ What about programs with lots of variables (arrays, etc.)?
Use memory , load/store operations to transfer data from
memory to register.

Control Input
Memory
Datapath Output

Processor I/O
Memory Organization
■ Viewed as a large single-dimension array with access by address
■ A memory address is an index into the memory array
■ Byte addressing means that the index points to a byte of
memory, and that the unit of memory accessed by a load/store
is a byte

0 8 bits of data
1 8 bits of data

2 8 bits of data

3 8 bits of data

4 8 bits of data

5 8 bits of data
6 8 bits of data

...
 Memory Organization: Word
■ Bytes are load/store units, but most data items use larger words
■ For MIPS, a word is 32 bits or 4 bytes.

0 32 bits of data
4 32 bits of data Registers correspondingly hold 32 bits of data

8 32 bits of data
12 32 bits of data

...

■ 232 bytes with byte addresses from 0 to 232-1

■ 230 words with byte addresses 0, 4, 8, ... 232-4
■ i.e., words are aligned
■ what are the least 2 significant bits of a word address?
Load/Store Instructions
■ Load and store instructions
■ Example:

C code: A[8] = h + A[8];

value offset address

MIPS code (load): lw $t0, 32($s3)

(arithmetic): add $t0, $s2, $t0
(store): sw $t0, 32($s3)

■ Load word has destination first (brings data to register from

memory)
■ Store has destination last (stores value of a register to a
memory location/address)
So far we’ve learned:
■ MIPS
■ loading words
■ arithmetic on registers only

■ Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3

sub $s1, $s2, $s3 $s1 = $s2 – $s3
lw $s1, 100($s2) $s1 = Memory[$s2+100]
sw $s1, 100($s2) Memory[$s2+100]= $s1
 Machine Language
■ Instructions, like registers and words of data, are also 32 bits long
■ Example : add $t0, $s1, $s2
■ registers are numbered, e.g., $t0 is 8, $s1 is 17, $s2 is 18

■ Instruction Format R-type (“R” for aRithmetic):

$s1 $s2 $t0

000000 10001 10010 01000 00000 100000
op rs rt rd shamt funct
opcode – first second registe shift function field
operatio registe registe r amoun -
n r r destin- t selects variant
source source ation of operation
operand operand operand
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Machine Language
■ Consider the load-word and store-word instructions,
■ what would the regularity principle have us do?
■ we would have only 5 or 6 bits to determine the offset from a base
register - too little…

■ Design Principle 3: Good design demands a compromise

■ Introduce a new type of instruction format
■ I-type (“I” for Immediate) for data transfer instructions
■ Example : lw $t0, 1002($s2)

$s2 $t0 1002

100011 10010 01000 0000001111101010
6 bits 5 bits 5 bits 16 bits
op rs rt 16 bit offset
Stored Program Concept
■ Instructions are bit sequences, just like data
■ Programs are stored in memory
■ to be read or written just like data

memory for data, programs,

Processor Memory compilers, editors, etc.
 Control: Conditional Branch Instruction

■ Decision making instructions

■ alter the control flow,
■ i.e., change the next instruction to be executed

■ MIPS conditional branch instructions:

bne $t0, $t1, Label I-type instructions
beq $t0, $t1, Label

■ Example: if (i==j) h = i + j;

bne $s0, $s1, Label

add $s3, $s0, $s1
Label:....
 Addresses in Branch
■ Instructions:
bne $t4,$t5,Label Next instruction is at Label if $t4 != $t5
beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5
■ Format:

I op rs rt 16 bit
offset

■ 16 bits is too small a reach in a 232 address space

 Control: Conditional Branch Instruction

■ Example: if (i==j) h = i + j;

bne $s0, $s1, Label

add $s3, $s0, $s1
Label:....

$t0 $t1 beq $t0, $t1, Label

000100 01000 01001 0000000000000001
(offset)

How many instructions we have

between the branch instruction
and the instruction at Label
 Program Counter (PC)
■ Holds the address of the instruction
which is currently in execution
■ Typically update PC:
■ PC=PC+4
■ If branch condition is true
■ PC=branch destination address
 Addresses in Branch
■ PC: Program Counter
■ 32 bit register
■ Hods the address of the instruction which is currently in execution
■ MIPS branch destination address = (PC + 4) + (4 * offset)

■ so offset = (branch destination address – PC – 4)/4

■ If branch condition is true

■ PC== (PC + 4) + (4 * offset)
■ Else
■ PC=PC+4
Control: Unconditional Branch
(Jump)
■ MIPS unconditional branch instructions:
j Label
■ Example:
if (i!=j) beq $s4, $s5, Lab1
h=i+j; add $s3, $s4, $s5
else j Lab2
h=i-j; Lab1: sub $s3, $s4, $s5
Lab2: ...
■ J-type (“J” for Jump) instruction format
word-relative
■ Example: j Label # addr. Label = 100
addressing:
25 words = 100 bytes
000010 0000000000000000000001100
6 bits
1 26 bits
op 26 bit number
 Addresses in Jump
■ Word-relative addressing also for jump instructions

J op 26 bit
address
■ MIPS jump j instruction replaces lower 28 bits of the PC with
A00 where A is the 26 bit address; it never changes upper 4 bits
■ (Most significant 4 bits of PC) (LSB 26 bits from the inst.)(00)
Immediate (constant) Operands
■ Make operand part of instruction itself!

■ Design Principle 4: Make the common case fast

■ Example: addi $s2, $s1, 4 # $s2 = $s1 + 4

001000 10001 10010 0000000000000100

6 bits 5 bits 5 bits 16 bits

op rs rt 16 bit number
 So far
■ Instruction Format Meaning
add $s1,$s2,$s3 R $s1 = $s2 + $s3
sub $s1,$s2,$s3 R $s1 = $s2 – $s3
lw $s1,100($s2) I $s1 = Memory[$s2+100]
sw $s1,100($s2) I Memory[$s2+100] = $s1
bne $s4,$s5,Lab1I Next instr. is at Lab1 if $s4 != $s5
beq $s4,$s5,Lab2I Next instr. is at Lab2 if $s4 = $s5
j Lab3 J Next instr. is at Lab3

■ Formats:
R op rs rt rd shamt funct

I op rs rt 16 bit address
op 26 bit address
J
 Policy-of-Use Convention for
Registers

Register 1, called $at, is reserved for the assembler; registers 26-27,

called $k0 and $k1 are reserved for the operating system.
Assembly Language vs.
Machine Language
■ Assembly provides convenient symbolic representation
■ much easier than writing down numbers
■ regular rules: e.g., destination first

■ Machine language: zeros and ones.

Procedures
■ Example C code:

// procedure adds 10 to input parameter

int main()
{ int i, j;
i = 5;
j = add10(i);
i = j;
return 0;}

int add10(int i)
{ return (i + 10);}
 Procedures
■ Translated MIPS assembly
■ Note more efficient use of registers possible! save register
in stack, see
.text figure below
.globl main add10:
addi $sp, $sp, -4
main: sw $s0, 0($sp)
addi $s0, $0, 5
add $a0, $s0, $0 addi $s0, $a0, 10
argument add $v0, $s0, $0
to callee jal add10 result
control returns here to caller
jump and link lw $s0, 0($sp)
add $s1, $v0, $0 restore
addi $sp, $sp,
values 4
add $s0, $s1, $0

return
jr $ra

MEMORY High address

$sp
Content of $s0
Low address
MIPS Addressing Modes
■ Tells how operands and addresses are
represented
■ Register addressing (R-type)
■ Base addressing (lw, sw)
■ Immediate addressing (addi)
■ PC-relative addressing (beq, bne)
■ Pseudodirect addressing (Jump inst.)
 MIPS Addressing Modes
addi

add

lw/sw
MIPS Addressing Modes

beq

j (jump)
 Overview of MIPS
■ Simple instructions – all 32 bits wide
■ Very structured – no unnecessary baggage
■ Only three instruction formats

op rs rt rd shamt funct
R

I op rs rt 16 bit address

op 26 bit address
J
Summarize MIPS:
Alternative Architectures
■ Design alternative:
■ provide more powerful operations
■ goal is to reduce number of instructions executed
■ danger is a slower cycle time and/or a higher CPI

■
Summary
■ Instruction complexity is only one variable
■ lower instruction count vs. higher CPI / lower clock rate

■ Design Principles:
■ simplicity favors regularity
■ smaller is faster
■ good design demands compromise
■ make the common case fast

■ Instruction set architecture

■ a very important abstraction indeed!