Unit 4:

Sequential Logic
(LH – 7)
Compiled by: Madan Nath
BMC BIM-TU

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Contents:
q Latches
q Edge-Triggered Flip-Flops
q Flip-Flop Operating Characteristics
q Flip-Flop Application

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 Latches
• They are also known as basic flip-flop circuit.
• Latches are the basic building blocks of sequential circuit.
• They are basic storage elements that operate with signal levels
(rather than signal transitions).
• They are controlled by a clock transition are flip-flops.
• They are level-sensitive devices.
• They are useful for the design of the asynchronous sequential
circuit.
• It consists of two inputs namely “SET” and “RESET” and two
outputs, which are complement to each other.

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 SR (Set-Reset) Latch
• RS Latch with NOR Gate:
1. 2 cross-coupled NOR gate.
2. 2 input R for “RESET” and S for “SET”
3. 2 output Q and Q’.

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 SR (Set-Reset) Latch
• Case-4: S’= R’= 0 (S=R=1) –
When S=R=1, both Q and Q’ becomes 1 which is not allowed.
So, the input condition is prohibited.
• The SR Latch using NOR gate is shown below:

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 SR (Set-Reset) Latch
• SR Latch is with NAND:
1. 2 cross-coupled NAND gate.
2. 2 input S for “SET” and R for “RESET”.
3. 2 output Q and Q’.

• Under normal conditions, both the input remains 0.

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 SR (Set-Reset) Latch
• Case-1: S’=R’=1 (S=R=0) –
If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1
respectively.

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 SR (Set-Reset) Latch
• Case-2: S’=0, R’=1 (S=1, R=0) –
As S’=0, the output of 1st NAND gate, Q = 1(SET state). In
2nd NAND gate, as Q and R’ inputs are 1, Q’=0.

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 SR (Set-Reset) Latch
• Case-3: S’= 1, R’= 0 (S=0, R=1) –
As R’=0, the output of 2nd NAND gate, Q’ = 1. In 1st NAND
gate, as Q and S’ inputs are 1, Q=0(RESET state).

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 Gated SR Latch
• A Gated SR latch is a SR latch with enable input which works
when enable is 1 and retain the previous state when enable is 0.

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 Gated D Latch
• D latch is similar to SR latch with some modifications made.
Here, the inputs are complements of each other. The design of
D latch with Enable signal is given below:

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 Gated D Latch
• Truth Table:

Enable D Q(n) Q(n+1) STATE

1 0 x 0 RESET

1 1 x 1 SET

0 x x Q(n) No Change

As the output is same as the input D, D latch is also called

as Transparent Latch. Considering the truth table, the
characteristic equation for D latch with enable input can be
given as:
Q(n+1) = EN.D + EN'.Q(n)

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 Difference between Flip-flop and Latch:
SNO Flip-flop Latch
1. Flip-flop is a bistable device Latch is also a bistable
i.e., it has two stable states that device whose states are also
are represented as 0 and 1. represented as 0 and 1.
2. It checks the inputs but changes It checks the inputs
the output only at times defined continuously and responds
by the clock signal or any other to the changes in inputs
control signal. immediately.

3. It is a edge triggered device. It is a level triggered device.

4. Gates like NOR, NOT, AND, These are also made up of

NAND are building blocks of gates.
flip flops.
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 Difference between Flip-flop and Latch:
They are classified into
There is no such
5. asynchronous or
classification in latches.
synchronous flipflops.
These can be used for the
It forms the building
designing of sequential
6. blocks of many sequential
circuits but are not generally
circuits like counters.
preferred.
a, Flip-flop always have a latche doesn’t have a clock
7.
clock signal signal
Flip-flop can be build from Latches can be build from
8.
Latches gates
ex:D Flip-flop, JK Flip-
9. ex: SR Latch, D Latch etc.
flop etc.
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 Flip-flops
• Flip-flop is a basic digital memory circuit, which stores 1-bit of
information and it is used in clocked sequential circuit.
• The output is obtained in a sequential circuit from combinational
circuit or flip-flop or both.
• The state of flip-flop changes at active state of clock pulses and
remains unaffected when the clock pulse is not active. The two
stable states are High (logic 1) and Low (logic 0).
• They can switch between the states under the influence of a
control signal (clock or enable) i.e. they can ‘flip’ to one state
and ‘flop’ back to other state.
• They are binary storage devices because they can store binary
data (0 or 1).
• Flip-flops are also used to control the digital circuit’s
functionality. They can change the operation of a digital circuit
depending on the state
 Flip-flops
• Q is called the state of the flip-flop whereas Q’ is called
complementary state of the flip-flop.
• When the output Q is either 0 or 1, it remains in that state
unless one or more inputs are excited to effect the change on
the output.

fig: block diagram of flip-flop

 Flip-flops
• The two outputs are complementary to each other.
1. If Q is 1 that is set Q’ to 0.
2. If Q is 0, reset Q’ to 1. (Q and Q’ can’t be at the same
state simultaneously. If it happens, it will violate the
definition of the flip-flop and hence is called undefined
condition).

• A basic flip-flop can be constructed using 4-NAND or 4-NOR

gates.

• Types of flip-flops:
• SR Flip Flop
• JK Flip Flop
• D Flip Flop
• T Flip Flop
 S-R FLIP FLOP
• The S-R flip-flop consist of the basic NAND latch and
two other NAND gates to provide clock pulse as shown
in fig.

• Clock pulse is used for the synchronous and act as an

additional control input.
 S-R FLIP FLOP
• Using NOR gate: • Using NAND gate:

S R Q(n) Q(n+1)
0 0 0 0 (Qn) S R Q(n) Q(n+1)
0 0 1 1 (Qn) 0 0 x Qn
0 1 0 0
0 1 x 0(reset)
0 1 1 0
1 0 0 1 1 0 x 1(set)
1 0 1 1 1 1 x 1(Indetermin
1 1 0 x ate state)
1 1 1 x
 S-R FLIP FLOP
From the diagram it is evident that the flip flop has mainly
four states. They are
• S=1, R=0 à Q=1, Q’=0 (This state is also called the SET state)
• S=0, R=1 à Q=0, Q’=1 (This state is k nown as the RESET
state)
In both the states ,the outputs are just compliments of each other
and that the value of Q follows the value of S.
• S=0, R=0 à Q & Q’= Remember
If both the values of S and R are switched to 0, then the circuit
remembers the value of S and R in their previous state.
• S=1, R=1à Q=0, Q’=0 [Invalid]
• This isan invalid state because the values of both Q and Q’are
0.
• They are supposed to be compliments of each other. Normally,
this state must be avoided.
S-R Characteristics equation
00 01 11 10

0
1

There for, Q(n+1) = S + QR’

 JK-FLIP FLOP
• J-K term has come form engineer name Jack kilby.
• The J-K flip-flop is the refinement of the SR flip-fop to solve
the problem of indeterminate sate when both input are 1.
• In J-K flip-flop inputs J and K behave like inputs S and R to
Set and Reset the flip-flop.
 JK-FLIP FLOP
• Using NOR gate: J K Q(n) Q(n+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
 JK-FLIP FLOP
• Using NAND gate:

J K Q(n) Q(n+1)
0 0 x Qn
0 1 x 0 à Reset
1 0 x 1 à Set
1 1 x Q(n)’ à Toggle
 JK flip-flop Characteristics equation
00 01 11 10

0
1

Q(n+1)= K’Q(n) + JQ(n)’

 WORKING
• Q and Q' are feedback to the pulse-steering
NAND gates.
• No invalid state.
• Include a toggle (switch) state.
• J=HIGH (and K=LOW) - a SET state
• K=HIGH (and J=LOW) - a RESET state
• both inputs LOW - a no change
• both inputs HIGH - a toggle
 D-FLIP FLOP
• A D flip flop is like SR flip-flop.
• The D flip-flop is widely used. It is also known as a
"data" or "delay" flip-flop and negative edge
triggered flip flop.
• By comparing S-R, J-K, and D flip-flops one can
see that the D flip-flop never has an unknown state,
unlike the S-R and J-K.

• single input D (data)

• D=HIGH - a SET state
• D=LOW - a RESET state
 D-FLIP FLOP using NAND gate

D Q(n) Q(n+1)
Data(D) Q(n) Q(n+1)
0 0 0
0 x 0 (Reset)
0 1 0
1 x 1(set)
1 0 1
1 1 1
NOTE: Clock is always on is = 1
Characteristics equation for D flip-flop
Q(n)’ Q(n)

D’

Q(n+1) = D
D-FLIP FLOP using NOR gate

CLK D J K Q Q’
1 1 0 1 0 1
1 1 1 0 1 0
 T-FLIP FLOP
• A Toggle (T) flip flop is like JK flip-flop.
• These are basically a single input version of JK flip flop.
• This modified form of JK flip-flop is obtained by
connecting both inputs J and K together.
• This flip-flop has only one input along with the
clock input.
 T-FLIP FLOP Using NAND gate

T Q(n) Q(n+1)
T Q(n) Q(n+1)
0 0 0
0 x Q(n) àNo Change
0 1 1
1 x Q(n)’
1 0 1
1 1 0 NOTE: Clock is always on is = 1

Fig Excitation table

 T-FLIP FLOP for NOR gate

T Q(n) Q(n+1) T Q(n) Q(n+1)

0 0 0 0 x Q(n) àNo Change
0 1 1 1 x Q(n)’
1 0 1
1 1 0
Fig Excitation table NOTE: Clock is always on is = 1
Characteristics equation for T flip-flop

Q(n)’ Q(n)

D’
D
 THE USE OF FLIP FLOP
• For Register Devices:
Flip flops can store a single bit of data i.e. 1 or 0.
Registers are used to store multiple bits of data. So flip
flops are used to design Registers. According to digital
electronics, a Register is a device which is used to store
the information.

• Data Transfer
The process of transferring the data from one
register to another register
 i) Convert SR To JK FlipFlop
Let there be required flipflop to be constructed using sub-flipflop:
1. Draw the truth table of required flipflop.
2. Write the corresponding outputs of sub-flipflop to be used from
the excitation table.
3. Draw K-Maps using required flipflop inputs and obtain
excitation functions for sub-flipflop inputs.
4. Construct logic diagram according to the functions obtained.
i) Convert SR To JK FlipFlop
 i) Convert SR To JK FlipFlop
Excitation Functions:
ii) Convert SR To D Flip-Flop:
Excitation Functions:
S=D
R = D‘
 Applications of Flip-Flops
These are the various types of flip-flops being used in digital
electronic circuits and the applications of Flip-flops are as
specified below.
• Counters
• Frequency Dividers
• Shift Registers
• Storage Registers
• Bounce elimination switch
• Data storage
• Data transfer
• Latch
• Registers
• Memory
 Assignment !!
• What is the advantage of flip flop over latch?
• What is the difference between Latch and flip flop?
• Identify and state the similarities between Latch and flipflop.
• “Flip-flop is 1 bit memory”. Justify
• Explain setup time, Hold time, Propagation delay, Power
dissipation and Maximum clock frequency of flip flop.
• How many Flip-flops are required to divide a frequency by
16?
• Illustrate the difference between T and D flip flop along with
it’s characteristics table excitation table and characteristics
equation.
• Differentiate between T and D flip-flop along with its truth
table and circuit diagram.
• Design and explain the operational characteristics of flip-flop
which solve the problem of closed JK flipflop.
 Assignment !!
• Design and explain the operational characteristics of flip flop
that is single input version of JK flip flop .
• Design and explain the flip flop which complements its
present state when the clock is triggered with both input
HIGH.
• It is possible to implement counting function using data flip-
flop? Support your answer.
• Discuss flip flop operating characteristics.
• Make distinction between RS and D flip flop along with its
circuit diagram, characteristic equation and characteristic
table.
~ The End ~

Thank u !!